Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T52,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T52,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T53,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T52,T53
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T52,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T53,T54
0	1	Covered	T8,T90,T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T53,T54
0	1	Covered	T8,T53,T54
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T53,T54
1	-	Covered	T8,T53,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T52,T53
DetectSt	168	Covered	T8,T53,T54
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T53,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T53,T54
DebounceSt->IdleSt	163	Covered	T8,T52,T55
DetectSt->IdleSt	186	Covered	T8,T90,T114
DetectSt->StableSt	191	Covered	T8,T53,T54
IdleSt->DebounceSt	148	Covered	T8,T52,T53
StableSt->IdleSt	206	Covered	T8,T53,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T52,T53
0	1	Covered	T8,T52,T53
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T53,T54
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T52,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T53,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T52,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T52,T53
DetectSt	-	-	-	-	1	-	-	Covered	T8,T90,T114
DetectSt	-	-	-	-	0	1	-	Covered	T8,T53,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T53,T54
StableSt	-	-	-	-	-	-	0	Covered	T8,T53,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	277	0	0
CntIncr_A	7461812	197373	0	0
CntNoWrap_A	7461812	6763238	0	0
DetectStDropOut_A	7461812	3	0	0
DetectedOut_A	7461812	797	0	0
DetectedPulseOut_A	7461812	124	0	0
DisabledIdleSt_A	7461812	6559914	0	0
DisabledNoDetection_A	7461812	6562303	0	0
EnterDebounceSt_A	7461812	153	0	0
EnterDetectSt_A	7461812	127	0	0
EnterStableSt_A	7461812	124	0	0
PulseIsPulse_A	7461812	124	0	0
StayInStableSt	7461812	673	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	7035	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	124	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	277	0	0
T8	26040	11	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	3	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	4	0	0
T100	0	4	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	197373	0	0
T8	26040	2376	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T52	0	20	0	0
T53	0	34	0	0
T54	0	95	0	0
T55	0	65186	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	36141	0	0
T100	0	24	0	0
T101	0	77	0	0
T102	0	13	0	0
T103	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763238	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	3	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T90	0	1	0	0
T114	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	797	0	0
T8	26040	25	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T53	0	6	0	0
T54	0	4	0	0
T55	0	7	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	18	0	0
T100	0	6	0	0
T101	0	12	0	0
T102	0	5	0	0
T116	0	19	0	0
T117	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	124	0	0
T8	26040	4	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6559914	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6562303	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	153	0	0
T8	26040	7	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	127	0	0
T8	26040	5	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	124	0	0
T8	26040	4	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	124	0	0
T8	26040	4	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	673	0	0
T8	26040	21	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T53	0	5	0	0
T54	0	3	0	0
T55	0	6	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	16	0	0
T100	0	4	0	0
T101	0	11	0	0
T102	0	4	0	0
T116	0	17	0	0
T117	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	7035	0	0
T1	635	0	0	0
T2	16315	19	0	0
T3	693	0	0	0
T4	503	5	0	0
T5	524	5	0	0
T6	490	0	0	0
T14	12958	12	0	0
T15	0	14	0	0
T16	0	6	0	0
T18	0	31	0	0
T21	504	5	0	0
T22	6629	25	0	0
T23	494	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	124	0	0
T8	26040	4	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T28,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T42,T82
0	1	Covered	T8,T68,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T42,T82
0	1	Unreachable
1	0	Covered	T28,T42,T82

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T28
DetectSt	168	Covered	T8,T28,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T28,T42,T82

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T28,T42
DebounceSt->IdleSt	163	Covered	T27,T68,T84
DetectSt->IdleSt	186	Covered	T8,T68,T96
DetectSt->StableSt	191	Covered	T28,T42,T82
IdleSt->DebounceSt	148	Covered	T8,T27,T28
StableSt->IdleSt	206	Covered	T28,T42,T82

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T27,T28
0	1	Covered	T8,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T28,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T28,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T68,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T8,T68,T96
DetectSt	-	-	-	-	0	1	-	Covered	T28,T42,T82
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T42,T82
StableSt	-	-	-	-	-	-	0	Covered	T28,T42,T82
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	166	0	0
CntIncr_A	7461812	161761	0	0
CntNoWrap_A	7461812	6763349	0	0
DetectStDropOut_A	7461812	12	0	0
DetectedOut_A	7461812	248769	0	0
DetectedPulseOut_A	7461812	52	0	0
DisabledIdleSt_A	7461812	5904605	0	0
DisabledNoDetection_A	7461812	5907049	0	0
EnterDebounceSt_A	7461812	103	0	0
EnterDetectSt_A	7461812	64	0	0
EnterStableSt_A	7461812	52	0	0
PulseIsPulse_A	7461812	52	0	0
StayInStableSt	7461812	248717	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	7035	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_sticky_sva.StableStDropOut_A	7461812	330432	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	166	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	5	0	0
T28	0	2	0	0
T42	0	2	0	0
T62	410	0	0	0
T68	0	8	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	4	0	0
T83	0	4	0	0
T84	0	5	0	0
T85	0	3	0	0
T86	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	161761	0	0
T8	26040	72	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	225	0	0
T28	0	19	0	0
T42	0	68	0	0
T62	410	0	0	0
T68	0	50	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	118	0	0
T83	0	150	0	0
T84	0	79385	0	0
T85	0	42	0	0
T86	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763349	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	12	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T62	410	0	0	0
T68	0	3	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T96	0	1	0	0
T119	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	2	0	0
T129	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	248769	0	0
T28	792	112	0	0
T42	10472	331	0	0
T49	10167	0	0	0
T58	113683	0	0	0
T76	499	0	0	0
T82	0	320	0	0
T83	0	1036	0	0
T95	0	738	0	0
T96	0	117	0	0
T115	4398	0	0	0
T118	0	253	0	0
T119	0	134	0	0
T120	0	352	0	0
T121	0	13	0	0
T122	502	0	0	0
T123	615	0	0	0
T124	871	0	0	0
T125	726	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	52	0	0
T28	792	1	0	0
T42	10472	1	0	0
T49	10167	0	0	0
T58	113683	0	0	0
T76	499	0	0	0
T82	0	2	0	0
T83	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T115	4398	0	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T124	871	0	0	0
T125	726	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5904605	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5907049	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	103	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	5	0	0
T28	0	1	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	5	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	5	0	0
T85	0	3	0	0
T86	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T28	0	1	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	3	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	2	0	0
T83	0	2	0	0
T95	0	1	0	0
T96	0	2	0	0
T118	0	2	0	0
T119	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	52	0	0
T28	792	1	0	0
T42	10472	1	0	0
T49	10167	0	0	0
T58	113683	0	0	0
T76	499	0	0	0
T82	0	2	0	0
T83	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T115	4398	0	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T124	871	0	0	0
T125	726	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	52	0	0
T28	792	1	0	0
T42	10472	1	0	0
T49	10167	0	0	0
T58	113683	0	0	0
T76	499	0	0	0
T82	0	2	0	0
T83	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T115	4398	0	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	502	0	0	0
T123	615	0	0	0
T124	871	0	0	0
T125	726	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	248717	0	0
T28	792	111	0	0
T42	10472	330	0	0
T49	10167	0	0	0
T58	113683	0	0	0
T76	499	0	0	0
T82	0	318	0	0
T83	0	1034	0	0
T95	0	737	0	0
T96	0	116	0	0
T115	4398	0	0	0
T118	0	251	0	0
T119	0	133	0	0
T120	0	351	0	0
T121	0	12	0	0
T122	502	0	0	0
T123	615	0	0	0
T124	871	0	0	0
T125	726	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	7035	0	0
T1	635	0	0	0
T2	16315	19	0	0
T3	693	0	0	0
T4	503	5	0	0
T5	524	5	0	0
T6	490	0	0	0
T14	12958	12	0	0
T15	0	14	0	0
T16	0	6	0	0
T18	0	31	0	0
T21	504	5	0	0
T22	6629	25	0	0
T23	494	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	330432	0	0
T28	792	128	0	0
T42	10472	82	0	0
T49	10167	0	0	0
T58	113683	0	0	0
T76	499	0	0	0
T82	0	292	0	0
T83	0	207	0	0
T95	0	95	0	0
T96	0	58	0	0
T115	4398	0	0	0
T118	0	415	0	0
T119	0	233	0	0
T120	0	139	0	0
T121	0	128	0	0
T122	502	0	0	0
T123	615	0	0	0
T124	871	0	0	0
T125	726	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T21
1	1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T28,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T42
0	1	Covered	T95,T96,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T42
0	1	Unreachable
1	0	Covered	T8,T28,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T28
DetectSt	168	Covered	T8,T28,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T28,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T28,T42
DebounceSt->IdleSt	163	Covered	T27,T82,T95
DetectSt->IdleSt	186	Covered	T95,T96,T97
DetectSt->StableSt	191	Covered	T8,T28,T42
IdleSt->DebounceSt	148	Covered	T8,T27,T28
StableSt->IdleSt	206	Covered	T8,T28,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T27,T28
0	1	Covered	T8,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T28,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T28,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T82,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T95,T96,T97
DetectSt	-	-	-	-	0	1	-	Covered	T8,T28,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T28,T42
StableSt	-	-	-	-	-	-	0	Covered	T8,T28,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	165	0	0
CntIncr_A	7461812	57173	0	0
CntNoWrap_A	7461812	6763350	0	0
DetectStDropOut_A	7461812	7	0	0
DetectedOut_A	7461812	152713	0	0
DetectedPulseOut_A	7461812	46	0	0
DisabledIdleSt_A	7461812	5904605	0	0
DisabledNoDetection_A	7461812	5907049	0	0
EnterDebounceSt_A	7461812	113	0	0
EnterDetectSt_A	7461812	53	0	0
EnterStableSt_A	7461812	46	0	0
PulseIsPulse_A	7461812	46	0	0
StayInStableSt	7461812	152667	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_sticky_sva.StableStDropOut_A	7461812	375229	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	165	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	5	0	0
T28	0	4	0	0
T42	0	2	0	0
T62	410	0	0	0
T68	0	2	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	7	0	0
T83	0	4	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	57173	0	0
T8	26040	23	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	315	0	0
T28	0	32	0	0
T42	0	33	0	0
T62	410	0	0	0
T68	0	13	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	203	0	0
T83	0	24	0	0
T84	0	70	0	0
T85	0	68	0	0
T86	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763350	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	7	0	0
T87	8364	0	0	0
T95	24241	2	0	0
T96	0	1	0	0
T97	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	893	0	0	0
T134	30579	0	0	0
T135	5171	0	0	0
T136	733	0	0	0
T137	10425	0	0	0
T138	491	0	0	0
T139	637	0	0	0
T140	33803	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	152713	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T28	0	111	0	0
T42	0	276	0	0
T62	410	0	0	0
T68	0	87	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T83	0	181	0	0
T84	0	354	0	0
T85	0	307	0	0
T86	0	411	0	0
T95	0	52	0	0
T119	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	46	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5904605	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5907049	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	113	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	5	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	7	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	53	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	3	0	0
T96	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	46	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	46	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	152667	0	0
T28	792	109	0	0
T42	10472	275	0	0
T49	10167	0	0	0
T58	113683	0	0	0
T68	0	86	0	0
T76	499	0	0	0
T83	0	179	0	0
T84	0	353	0	0
T85	0	306	0	0
T86	0	410	0	0
T95	0	51	0	0
T115	4398	0	0	0
T119	0	115	0	0
T120	0	257	0	0
T122	502	0	0	0
T123	615	0	0	0
T124	871	0	0	0
T125	726	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	375229	0	0
T8	26040	81	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T28	0	166	0	0
T42	0	182	0	0
T62	410	0	0	0
T68	0	86	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T83	0	1173	0	0
T84	0	79037	0	0
T85	0	65	0	0
T86	0	219	0	0
T95	0	283	0	0
T119	0	430	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Covered	T68,T82,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Unreachable
1	0	Covered	T8,T27,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T28
DetectSt	168	Covered	T8,T27,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T27,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T27,T28
DebounceSt->IdleSt	163	Covered	T82,T84,T85
DetectSt->IdleSt	186	Covered	T68,T82,T94
DetectSt->StableSt	191	Covered	T8,T27,T28
IdleSt->DebounceSt	148	Covered	T8,T27,T28
StableSt->IdleSt	206	Covered	T8,T27,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T27,T28
0	1	Covered	T8,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T27,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T84,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T68,T82,T94
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T28
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	170	0	0
CntIncr_A	7461812	138784	0	0
CntNoWrap_A	7461812	6763345	0	0
DetectStDropOut_A	7461812	13	0	0
DetectedOut_A	7461812	122514	0	0
DetectedPulseOut_A	7461812	50	0	0
DisabledIdleSt_A	7461812	5904605	0	0
DisabledNoDetection_A	7461812	5907049	0	0
EnterDebounceSt_A	7461812	108	0	0
EnterDetectSt_A	7461812	63	0	0
EnterStableSt_A	7461812	50	0	0
PulseIsPulse_A	7461812	50	0	0
StayInStableSt	7461812	122464	0	0
gen_high_event_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_sticky_sva.StableStDropOut_A	7461812	513927	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	170	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	2	0	0
T28	0	4	0	0
T42	0	2	0	0
T62	410	0	0	0
T68	0	4	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	8	0	0
T83	0	4	0	0
T84	0	5	0	0
T85	0	3	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	138784	0	0
T8	26040	15	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	43	0	0
T28	0	60	0	0
T42	0	62	0	0
T62	410	0	0	0
T68	0	22	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	168	0	0
T83	0	196	0	0
T84	0	405	0	0
T85	0	156	0	0
T86	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763345	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	13	0	0
T41	33410	0	0	0
T45	799	0	0	0
T68	638	1	0	0
T82	0	1	0	0
T94	0	1	0	0
T100	592	0	0	0
T126	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	420	0	0	0
T147	522	0	0	0
T148	402	0	0	0
T149	521	0	0	0
T150	404	0	0	0
T151	433	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	122514	0	0
T8	26040	6	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	203	0	0
T28	0	171	0	0
T42	0	292	0	0
T62	410	0	0	0
T68	0	37	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	31	0	0
T83	0	1093	0	0
T85	0	81	0	0
T86	0	455	0	0
T95	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	50	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5904605	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5907049	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	108	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	2	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	6	0	0
T83	0	2	0	0
T84	0	5	0	0
T85	0	2	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	63	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	2	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	2	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	50	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	50	0	0
T8	26040	1	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T42	0	1	0	0
T62	410	0	0	0
T68	0	1	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	122464	0	0
T8	26040	5	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	202	0	0
T28	0	169	0	0
T42	0	291	0	0
T62	410	0	0	0
T68	0	36	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	30	0	0
T83	0	1091	0	0
T85	0	80	0	0
T86	0	454	0	0
T95	0	81	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	513927	0	0
T8	26040	95	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	0	0	0
T27	0	258	0	0
T28	0	94	0	0
T42	0	140	0	0
T62	410	0	0	0
T68	0	115	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T82	0	173	0	0
T83	0	112	0	0
T85	0	145	0	0
T86	0	153	0	0
T95	0	839	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T46,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T46,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T46,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T27
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T46,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T46,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T46,T48
0	1	Covered	T152,T95,T153
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T46,T48
1	-	Covered	T152,T95,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T46,T48
DetectSt	168	Covered	T11,T46,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T46,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T46,T48
DebounceSt->IdleSt	163	Covered	T87,T88
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T46,T48
IdleSt->DebounceSt	148	Covered	T11,T46,T48
StableSt->IdleSt	206	Covered	T46,T48,T152

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T46,T48
0	1	Covered	T11,T46,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T46,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T46,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T46,T48
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T46,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T46,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T152,T95,T153
StableSt	-	-	-	-	-	-	0	Covered	T11,T46,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	68	0	0
CntIncr_A	7461812	45235	0	0
CntNoWrap_A	7461812	6763447	0	0
DetectStDropOut_A	7461812	0	0	0
DetectedOut_A	7461812	14530	0	0
DetectedPulseOut_A	7461812	33	0	0
DisabledIdleSt_A	7461812	6589567	0	0
DisabledNoDetection_A	7461812	6591963	0	0
EnterDebounceSt_A	7461812	35	0	0
EnterDetectSt_A	7461812	33	0	0
EnterStableSt_A	7461812	33	0	0
PulseIsPulse_A	7461812	33	0	0
StayInStableSt	7461812	14479	0	0
gen_high_level_sva.HighLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	68	0	0
T11	673	2	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T87	0	1	0	0
T95	0	2	0	0
T152	0	4	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	405	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	45235	0	0
T11	673	31	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	52	0	0
T48	0	21	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T87	0	44	0	0
T95	0	39	0	0
T152	0	150	0	0
T153	0	27	0	0
T154	0	39	0	0
T155	0	192	0	0
T156	0	144	0	0
T157	405	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763447	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	14530	0	0
T11	673	175	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	37	0	0
T48	0	37	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T95	0	113	0	0
T152	0	199	0	0
T153	0	41	0	0
T154	0	59	0	0
T155	0	85	0	0
T156	0	151	0	0
T157	405	0	0	0
T158	0	168	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	33	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T95	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	405	0	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6589567	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6591963	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	35	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T87	0	1	0	0
T95	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	405	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	33	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T95	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	405	0	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	33	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T95	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	405	0	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	33	0	0
T11	673	1	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T95	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	405	0	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	14479	0	0
T11	673	173	0	0
T12	23922	0	0	0
T13	15640	0	0	0
T36	631	0	0	0
T46	0	35	0	0
T48	0	35	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T74	497	0	0	0
T95	0	112	0	0
T152	0	196	0	0
T153	0	40	0	0
T154	0	57	0	0
T155	0	82	0	0
T156	0	147	0	0
T157	405	0	0	0
T158	0	166	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	15	0	0
T90	9782	0	0	0
T95	0	1	0	0
T152	1014	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	34700	0	0	0
T165	422	0	0	0
T166	404	0	0	0
T167	436	0	0	0
T168	522	0	0	0
T169	405	0	0	0
T170	20365	0	0	0
T171	193522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T13
1	0	Covered	T4,T5,T21
1	1	Covered	T8,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T13
0	1	Covered	T172,T173
1	0	Covered	T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T13
0	1	Covered	T8,T11,T174
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T13
1	-	Covered	T8,T11,T174

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T13
DetectSt	168	Covered	T8,T11,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T11,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T13
DebounceSt->IdleSt	163	Covered	T174,T175,T155
DetectSt->IdleSt	186	Covered	T87,T172,T173
DetectSt->StableSt	191	Covered	T8,T11,T13
IdleSt->DebounceSt	148	Covered	T8,T11,T13
StableSt->IdleSt	206	Covered	T8,T11,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T13
0	1	Covered	T8,T11,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T88
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T174,T175,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T87,T172,T173
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T174
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461812	142	0	0
CntIncr_A	7461812	205270	0	0
CntNoWrap_A	7461812	6763373	0	0
DetectStDropOut_A	7461812	2	0	0
DetectedOut_A	7461812	5274	0	0
DetectedPulseOut_A	7461812	64	0	0
DisabledIdleSt_A	7461812	6369069	0	0
DisabledNoDetection_A	7461812	6371462	0	0
EnterDebounceSt_A	7461812	76	0	0
EnterDetectSt_A	7461812	67	0	0
EnterStableSt_A	7461812	64	0	0
PulseIsPulse_A	7461812	64	0	0
StayInStableSt	7461812	5181	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461812	2725	0	0
gen_low_level_sva.LowLevelEvent_A	7461812	6765961	0	0
gen_not_sticky_sva.StableStDropOut_A	7461812	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	142	0	0
T8	26040	6	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	2	0	0
T13	0	2	0	0
T27	0	2	0	0
T47	0	2	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	5	0	0
T175	0	3	0	0
T176	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	205270	0	0
T8	26040	215	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	31	0	0
T13	0	64	0	0
T27	0	27	0	0
T47	0	61	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	216	0	0
T175	0	114720	0	0
T176	0	52	0	0
T177	0	198	0	0
T178	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6763373	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	2	0	0
T114	661	0	0	0
T172	1162	1	0	0
T173	0	1	0	0
T179	417	0	0	0
T180	4780	0	0	0
T181	17091	0	0	0
T182	502	0	0	0
T183	408	0	0	0
T184	218459	0	0	0
T185	710	0	0	0
T186	28390	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5274	0	0
T8	26040	443	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	25	0	0
T13	0	90	0	0
T27	0	41	0	0
T47	0	42	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	32	0	0
T175	0	38	0	0
T176	0	111	0	0
T177	0	534	0	0
T178	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64	0	0
T8	26040	3	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	1	0	0
T13	0	1	0	0
T27	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6369069	0	0
T1	635	234	0	0
T2	16315	15073	0	0
T3	693	292	0	0
T4	503	102	0	0
T5	524	123	0	0
T6	490	89	0	0
T14	12958	12538	0	0
T21	504	103	0	0
T22	6629	6228	0	0
T23	494	93	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6371462	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	76	0	0
T8	26040	3	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	1	0	0
T13	0	1	0	0
T27	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	3	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	67	0	0
T8	26040	3	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	1	0	0
T13	0	1	0	0
T27	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64	0	0
T8	26040	3	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	1	0	0
T13	0	1	0	0
T27	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	64	0	0
T8	26040	3	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	1	0	0
T13	0	1	0	0
T27	0	1	0	0
T47	0	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	5181	0	0
T8	26040	439	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	24	0	0
T13	0	88	0	0
T27	0	39	0	0
T47	0	40	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T174	0	30	0	0
T175	0	36	0	0
T176	0	109	0	0
T177	0	531	0	0
T178	0	68	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	2725	0	0
T1	635	1	0	0
T2	16315	6	0	0
T3	693	1	0	0
T4	503	5	0	0
T5	524	6	0	0
T6	490	0	0	0
T14	12958	0	0	0
T16	0	4	0	0
T19	0	6	0	0
T20	0	1	0	0
T21	504	5	0	0
T22	6629	0	0	0
T23	494	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	6765961	0	0
T1	635	235	0	0
T2	16315	15079	0	0
T3	693	293	0	0
T4	503	103	0	0
T5	524	124	0	0
T6	490	90	0	0
T14	12958	12542	0	0
T21	504	104	0	0
T22	6629	6229	0	0
T23	494	94	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461812	35	0	0
T8	26040	2	0	0
T9	9027	0	0	0
T10	13667	0	0	0
T11	673	1	0	0
T62	410	0	0	0
T69	426	0	0	0
T70	425	0	0	0
T71	422	0	0	0
T72	451	0	0	0
T73	507	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T156	0	3	0	0
T158	0	1	0	0
T174	0	2	0	0
T177	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0