Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T42,T43,T107

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T42,T43,T107

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T43,T107,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T107
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T107

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T107,T25
0	1	Covered	T125,T130
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T107,T25
0	1	Covered	T43,T107,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T107,T25
1	-	Covered	T43,T107,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T43,T107
0	1	Covered	T42,T43,T107
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T107,T25
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T43,T107
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T107,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T43,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T43,T107
DetectSt	-	-	-	-	1	-	-	Covered	T125,T130
DetectSt	-	-	-	-	0	1	-	Covered	T43,T107,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T107,T25
StableSt	-	-	-	-	-	-	0	Covered	T43,T107,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	264	0	0
CntIncr_A	7802930	131232	0	0
CntNoWrap_A	7802930	7196167	0	0
DetectStDropOut_A	7802930	2	0	0
DetectedOut_A	7802930	795	0	0
DetectedPulseOut_A	7802930	120	0	0
DisabledIdleSt_A	7802930	7059071	0	0
DisabledNoDetection_A	7802930	7061277	0	0
EnterDebounceSt_A	7802930	144	0	0
EnterDetectSt_A	7802930	122	0	0
EnterStableSt_A	7802930	120	0	0
PulseIsPulse_A	7802930	120	0	0
StayInStableSt	7802930	675	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802930	7688	0	0
gen_low_level_sva.LowLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	120	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	264	0	0
T16	625	0	0	0
T25	0	4	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T42	1536	1	0	0
T43	681	3	0	0
T44	503	0	0	0
T67	0	2	0	0
T71	0	4	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	4	0	0
T107	0	2	0	0
T108	0	5	0	0
T109	0	6	0	0
T110	0	4	0	0
T111	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	131232	0	0
T16	625	0	0	0
T25	0	122	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T42	1536	93	0	0
T43	681	135	0	0
T44	503	0	0	0
T67	0	24	0	0
T71	0	174	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	128	0	0
T107	0	23	0	0
T108	0	139	0	0
T109	0	148	0	0
T110	0	120	0	0
T111	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196167	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	333	0	0
T43	681	277	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	2	0	0
T125	658	1	0	0
T126	43392	0	0	0
T130	0	1	0	0
T137	715	0	0	0
T138	90396	0	0	0
T139	555	0	0	0
T140	446	0	0	0
T141	803	0	0	0
T142	423	0	0	0
T143	707	0	0	0
T144	5019	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	795	0	0
T16	625	0	0	0
T25	0	8	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T43	681	3	0	0
T44	503	0	0	0
T67	0	3	0	0
T71	0	17	0	0
T83	0	16	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	21	0	0
T107	0	2	0	0
T108	0	15	0	0
T109	0	10	0	0
T110	0	14	0	0
T111	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	120	0	0
T16	625	0	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T43	681	1	0	0
T44	503	0	0	0
T67	0	1	0	0
T71	0	2	0	0
T83	0	2	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	2	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	3	0	0
T110	0	2	0	0
T111	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7059071	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	218	0	0
T43	681	55	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7061277	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	219	0	0
T43	681	55	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	144	0	0
T16	625	0	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T42	1536	1	0	0
T43	681	2	0	0
T44	503	0	0	0
T67	0	1	0	0
T71	0	2	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	2	0	0
T107	0	1	0	0
T108	0	3	0	0
T109	0	3	0	0
T110	0	2	0	0
T111	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	122	0	0
T16	625	0	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T43	681	1	0	0
T44	503	0	0	0
T67	0	1	0	0
T71	0	2	0	0
T83	0	2	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	2	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	3	0	0
T110	0	2	0	0
T111	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	120	0	0
T16	625	0	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T43	681	1	0	0
T44	503	0	0	0
T67	0	1	0	0
T71	0	2	0	0
T83	0	2	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	2	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	3	0	0
T110	0	2	0	0
T111	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	120	0	0
T16	625	0	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T43	681	1	0	0
T44	503	0	0	0
T67	0	1	0	0
T71	0	2	0	0
T83	0	2	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	2	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	3	0	0
T110	0	2	0	0
T111	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	675	0	0
T16	625	0	0	0
T25	0	6	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T43	681	2	0	0
T44	503	0	0	0
T67	0	2	0	0
T71	0	15	0	0
T83	0	14	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	19	0	0
T107	0	1	0	0
T108	0	13	0	0
T109	0	7	0	0
T110	0	12	0	0
T111	522	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7688	0	0
T16	625	1	0	0
T29	500	0	0	0
T30	2227	12	0	0
T31	526	5	0	0
T33	0	3	0	0
T42	1536	3	0	0
T43	681	3	0	0
T44	503	4	0	0
T91	482	15	0	0
T103	525	7	0	0
T111	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	120	0	0
T16	625	0	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T43	681	1	0	0
T44	503	0	0	0
T67	0	1	0	0
T71	0	2	0	0
T83	0	2	0	0
T91	482	0	0	0
T103	525	0	0	0
T105	0	2	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	3	0	0
T110	0	2	0	0
T111	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T104,T105,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T104,T105,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T105,T57,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T104,T105,T57
1	0	Covered	T42,T43,T44
1	1	Covered	T104,T105,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T57,T58,T59
0	1	Covered	T105,T69,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T57,T58,T59
0	1	Unreachable
1	0	Covered	T57,T58,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T104,T105,T57
0	1	Covered	T104,T105,T57
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T105,T57,T58
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T104,T105,T57
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T105,T57,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T104,T69,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T104,T105,T57
DetectSt	-	-	-	-	1	-	-	Covered	T105,T69,T79
DetectSt	-	-	-	-	0	1	-	Covered	T57,T58,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T57,T58,T59
StableSt	-	-	-	-	-	-	0	Covered	T57,T58,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	197	0	0
CntIncr_A	7802930	97607	0	0
CntNoWrap_A	7802930	7196234	0	0
DetectStDropOut_A	7802930	48	0	0
DetectedOut_A	7802930	232261	0	0
DetectedPulseOut_A	7802930	34	0	0
DisabledIdleSt_A	7802930	6564484	0	0
DisabledNoDetection_A	7802930	6566739	0	0
EnterDebounceSt_A	7802930	115	0	0
EnterDetectSt_A	7802930	82	0	0
EnterStableSt_A	7802930	34	0	0
PulseIsPulse_A	7802930	34	0	0
StayInStableSt	7802930	232227	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802930	7688	0	0
gen_low_level_sva.LowLevelEvent_A	7802930	7198689	0	0
gen_sticky_sva.StableStDropOut_A	7802930	134814	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	197	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	4	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	8	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	12	0	0
T80	0	4	0	0
T104	1386	5	0	0
T105	2729	6	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	97607	0	0
T57	0	13	0	0
T58	0	39	0	0
T59	0	86	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	486	0	0
T77	0	84	0	0
T78	0	78	0	0
T79	0	102	0	0
T80	0	102	0	0
T104	1386	470	0	0
T105	2729	204	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196234	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	48	0	0
T69	12228	2	0	0
T79	0	6	0	0
T81	0	4	0	0
T96	26492	0	0	0
T105	2729	3	0	0
T106	570	0	0	0
T146	0	2	0	0
T149	0	8	0	0
T162	17511	0	0	0
T168	11702	0	0	0
T169	434	0	0	0
T170	0	3	0	0
T171	0	1	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	422	0	0	0
T175	425	0	0	0
T176	539	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	232261	0	0
T57	14272	66	0	0
T58	770	82	0	0
T59	0	353	0	0
T77	0	463	0	0
T78	0	347	0	0
T80	0	470	0	0
T82	0	137	0	0
T83	16728	0	0	0
T84	482	0	0	0
T85	503	0	0	0
T86	483	0	0	0
T87	406	0	0	0
T88	6078	0	0	0
T89	402	0	0	0
T90	20977	0	0	0
T147	0	140	0	0
T148	0	246	0	0
T150	0	17	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	34	0	0
T57	14272	1	0	0
T58	770	1	0	0
T59	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T82	0	1	0	0
T83	16728	0	0	0
T84	482	0	0	0
T85	503	0	0	0
T86	483	0	0	0
T87	406	0	0	0
T88	6078	0	0	0
T89	402	0	0	0
T90	20977	0	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6564484	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6566739	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	115	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	6	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	6	0	0
T80	0	2	0	0
T104	1386	5	0	0
T105	2729	3	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	82	0	0
T57	14272	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T69	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	6	0	0
T80	0	2	0	0
T81	0	4	0	0
T83	16728	0	0	0
T96	26492	0	0	0
T105	2729	3	0	0
T106	570	0	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T175	425	0	0	0
T176	539	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	34	0	0
T57	14272	1	0	0
T58	770	1	0	0
T59	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T82	0	1	0	0
T83	16728	0	0	0
T84	482	0	0	0
T85	503	0	0	0
T86	483	0	0	0
T87	406	0	0	0
T88	6078	0	0	0
T89	402	0	0	0
T90	20977	0	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	34	0	0
T57	14272	1	0	0
T58	770	1	0	0
T59	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T82	0	1	0	0
T83	16728	0	0	0
T84	482	0	0	0
T85	503	0	0	0
T86	483	0	0	0
T87	406	0	0	0
T88	6078	0	0	0
T89	402	0	0	0
T90	20977	0	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	232227	0	0
T57	14272	65	0	0
T58	770	81	0	0
T59	0	351	0	0
T77	0	462	0	0
T78	0	346	0	0
T80	0	468	0	0
T82	0	136	0	0
T83	16728	0	0	0
T84	482	0	0	0
T85	503	0	0	0
T86	483	0	0	0
T87	406	0	0	0
T88	6078	0	0	0
T89	402	0	0	0
T90	20977	0	0	0
T147	0	138	0	0
T148	0	244	0	0
T150	0	16	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7688	0	0
T16	625	1	0	0
T29	500	0	0	0
T30	2227	12	0	0
T31	526	5	0	0
T33	0	3	0	0
T42	1536	3	0	0
T43	681	3	0	0
T44	503	4	0	0
T91	482	15	0	0
T103	525	7	0	0
T111	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	134814	0	0
T57	14272	511	0	0
T58	770	206	0	0
T59	0	348	0	0
T77	0	76	0	0
T78	0	127	0	0
T80	0	116	0	0
T82	0	48	0	0
T83	16728	0	0	0
T84	482	0	0	0
T85	503	0	0	0
T86	483	0	0	0
T87	406	0	0	0
T88	6078	0	0	0
T89	402	0	0	0
T90	20977	0	0	0
T147	0	756	0	0
T148	0	350	0	0
T150	0	117	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T44,T103,T91

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T44,T103,T91
1	1	Covered	T44,T103,T91

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T104,T105,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T104,T105,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T105,T58,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T104,T105,T57
1	0	Covered	T44,T103,T91
1	1	Covered	T104,T105,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T58,T59,T77
0	1	Covered	T105,T78,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T58,T59,T77
0	1	Unreachable
1	0	Covered	T58,T59,T77

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T104,T105,T57
0	1	Covered	T104,T105,T57
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T105,T58,T59
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T104,T105,T57
IdleSt	0	-	-	-	-	-	-	Covered	T44,T103,T91
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T105,T58,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T104,T57,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T104,T105,T57
DetectSt	-	-	-	-	1	-	-	Covered	T105,T78,T79
DetectSt	-	-	-	-	0	1	-	Covered	T58,T59,T77
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T58,T59,T77
StableSt	-	-	-	-	-	-	0	Covered	T58,T59,T77
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	199	0	0
CntIncr_A	7802930	60437	0	0
CntNoWrap_A	7802930	7196232	0	0
DetectStDropOut_A	7802930	48	0	0
DetectedOut_A	7802930	83474	0	0
DetectedPulseOut_A	7802930	31	0	0
DisabledIdleSt_A	7802930	6564484	0	0
DisabledNoDetection_A	7802930	6566739	0	0
EnterDebounceSt_A	7802930	120	0	0
EnterDetectSt_A	7802930	79	0	0
EnterStableSt_A	7802930	31	0	0
PulseIsPulse_A	7802930	31	0	0
StayInStableSt	7802930	83443	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_sticky_sva.StableStDropOut_A	7802930	322559	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	199	0	0
T57	0	5	0	0
T58	0	2	0	0
T59	0	4	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	4	0	0
T77	0	2	0	0
T78	0	6	0	0
T79	0	12	0	0
T80	0	14	0	0
T104	1386	5	0	0
T105	2729	6	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	60437	0	0
T57	0	490	0	0
T58	0	95	0	0
T59	0	86	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	155	0	0
T77	0	91	0	0
T78	0	69	0	0
T79	0	492	0	0
T80	0	287	0	0
T104	1386	490	0	0
T105	2729	141	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196232	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	48	0	0
T78	2098	3	0	0
T79	0	6	0	0
T80	0	7	0	0
T82	0	2	0	0
T96	26492	0	0	0
T105	2729	3	0	0
T106	570	0	0	0
T152	0	5	0	0
T153	0	2	0	0
T163	2509	0	0	0
T168	11702	0	0	0
T169	434	0	0	0
T170	0	3	0	0
T171	0	1	0	0
T174	422	0	0	0
T175	425	0	0	0
T176	539	0	0	0
T177	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	83474	0	0
T58	770	198	0	0
T59	1739	276	0	0
T69	0	549	0	0
T77	1564	336	0	0
T99	633	0	0	0
T146	0	73	0	0
T147	0	588	0	0
T148	0	345	0	0
T149	0	864	0	0
T150	0	64	0	0
T151	0	3	0	0
T154	714	0	0	0
T155	666	0	0	0
T156	483	0	0	0
T157	11005	0	0	0
T158	533	0	0	0
T159	14048	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	31	0	0
T58	770	1	0	0
T59	1739	2	0	0
T69	0	2	0	0
T77	1564	1	0	0
T99	633	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T154	714	0	0	0
T155	666	0	0	0
T156	483	0	0	0
T157	11005	0	0	0
T158	533	0	0	0
T159	14048	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6564484	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6566739	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	120	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	2	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	2	0	0
T77	0	1	0	0
T78	0	3	0	0
T79	0	6	0	0
T80	0	7	0	0
T104	1386	5	0	0
T105	2729	3	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	79	0	0
T58	770	1	0	0
T59	0	2	0	0
T69	0	2	0	0
T77	0	1	0	0
T78	0	3	0	0
T79	0	6	0	0
T80	0	7	0	0
T82	0	2	0	0
T96	26492	0	0	0
T105	2729	3	0	0
T106	570	0	0	0
T146	0	1	0	0
T154	714	0	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T175	425	0	0	0
T176	539	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	31	0	0
T58	770	1	0	0
T59	1739	2	0	0
T69	0	2	0	0
T77	1564	1	0	0
T99	633	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T154	714	0	0	0
T155	666	0	0	0
T156	483	0	0	0
T157	11005	0	0	0
T158	533	0	0	0
T159	14048	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	31	0	0
T58	770	1	0	0
T59	1739	2	0	0
T69	0	2	0	0
T77	1564	1	0	0
T99	633	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T154	714	0	0	0
T155	666	0	0	0
T156	483	0	0	0
T157	11005	0	0	0
T158	533	0	0	0
T159	14048	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	83443	0	0
T58	770	197	0	0
T59	1739	274	0	0
T69	0	547	0	0
T77	1564	335	0	0
T99	633	0	0	0
T146	0	72	0	0
T147	0	586	0	0
T148	0	343	0	0
T149	0	862	0	0
T150	0	63	0	0
T151	0	2	0	0
T154	714	0	0	0
T155	666	0	0	0
T156	483	0	0	0
T157	11005	0	0	0
T158	533	0	0	0
T159	14048	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	322559	0	0
T58	770	45	0	0
T59	1739	435	0	0
T69	0	155	0	0
T77	1564	196	0	0
T99	633	0	0	0
T146	0	39	0	0
T147	0	133	0	0
T148	0	193	0	0
T149	0	182	0	0
T150	0	39	0	0
T151	0	129	0	0
T154	714	0	0	0
T155	666	0	0	0
T156	483	0	0	0
T157	11005	0	0	0
T158	533	0	0	0
T159	14048	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T44,T103,T91

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T104,T105,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T104,T105,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T105,T57,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T104,T105,T57
1	0	Covered	T44,T103,T91
1	1	Covered	T104,T105,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T77,T69,T78
0	1	Covered	T105,T57,T58
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T77,T69,T78
0	1	Unreachable
1	0	Covered	T77,T69,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T104,T105,T57
0	1	Covered	T104,T105,T57
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T105,T57,T58
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T104,T105,T57
IdleSt	0	-	-	-	-	-	-	Covered	T44,T103,T91
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T105,T57,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T104,T59,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T104,T105,T57
DetectSt	-	-	-	-	1	-	-	Covered	T105,T57,T58
DetectSt	-	-	-	-	0	1	-	Covered	T77,T69,T78
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T77,T69,T78
StableSt	-	-	-	-	-	-	0	Covered	T77,T69,T78
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	177	0	0
CntIncr_A	7802930	35332	0	0
CntNoWrap_A	7802930	7196254	0	0
DetectStDropOut_A	7802930	36	0	0
DetectedOut_A	7802930	136335	0	0
DetectedPulseOut_A	7802930	30	0	0
DisabledIdleSt_A	7802930	6564484	0	0
DisabledNoDetection_A	7802930	6566739	0	0
EnterDebounceSt_A	7802930	111	0	0
EnterDetectSt_A	7802930	66	0	0
EnterStableSt_A	7802930	30	0	0
PulseIsPulse_A	7802930	30	0	0
StayInStableSt	7802930	136305	0	0
gen_high_event_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_sticky_sva.StableStDropOut_A	7802930	6698	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	177	0	0
T57	0	10	0	0
T58	0	4	0	0
T59	0	7	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	4	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	4	0	0
T80	0	4	0	0
T104	1386	5	0	0
T105	2729	6	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	35332	0	0
T57	0	110	0	0
T58	0	92	0	0
T59	0	651	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	115	0	0
T77	0	50	0	0
T78	0	100	0	0
T79	0	118	0	0
T80	0	86	0	0
T104	1386	295	0	0
T105	2729	81	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196254	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	36	0	0
T57	14272	5	0	0
T58	0	2	0	0
T82	0	2	0	0
T83	16728	0	0	0
T96	26492	0	0	0
T105	2729	3	0	0
T106	570	0	0	0
T146	0	2	0	0
T148	0	2	0	0
T151	0	1	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T175	425	0	0	0
T176	539	0	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	136335	0	0
T69	12228	371	0	0
T77	1564	261	0	0
T78	2098	421	0	0
T79	1188	390	0	0
T80	0	227	0	0
T81	0	95370	0	0
T147	0	100	0	0
T149	0	630	0	0
T152	0	423	0	0
T153	0	139	0	0
T160	525	0	0	0
T161	1287	0	0	0
T162	17511	0	0	0
T163	2509	0	0	0
T164	502	0	0	0
T165	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	30	0	0
T69	12228	2	0	0
T77	1564	1	0	0
T78	2098	1	0	0
T79	1188	2	0	0
T80	0	2	0	0
T81	0	1	0	0
T147	0	2	0	0
T149	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T160	525	0	0	0
T161	1287	0	0	0
T162	17511	0	0	0
T163	2509	0	0	0
T164	502	0	0	0
T165	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6564484	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6566739	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	111	0	0
T57	0	5	0	0
T58	0	2	0	0
T59	0	7	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	0	0	0
T69	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T104	1386	5	0	0
T105	2729	3	0	0
T166	484	0	0	0
T167	881	0	0	0
T168	11702	0	0	0
T169	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	66	0	0
T57	14272	5	0	0
T58	0	2	0	0
T69	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	16728	0	0	0
T96	26492	0	0	0
T105	2729	3	0	0
T106	570	0	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T175	425	0	0	0
T176	539	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	30	0	0
T69	12228	2	0	0
T77	1564	1	0	0
T78	2098	1	0	0
T79	1188	2	0	0
T80	0	2	0	0
T81	0	1	0	0
T147	0	2	0	0
T149	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T160	525	0	0	0
T161	1287	0	0	0
T162	17511	0	0	0
T163	2509	0	0	0
T164	502	0	0	0
T165	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	30	0	0
T69	12228	2	0	0
T77	1564	1	0	0
T78	2098	1	0	0
T79	1188	2	0	0
T80	0	2	0	0
T81	0	1	0	0
T147	0	2	0	0
T149	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T160	525	0	0	0
T161	1287	0	0	0
T162	17511	0	0	0
T163	2509	0	0	0
T164	502	0	0	0
T165	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	136305	0	0
T69	12228	369	0	0
T77	1564	260	0	0
T78	2098	420	0	0
T79	1188	388	0	0
T80	0	225	0	0
T81	0	95369	0	0
T147	0	98	0	0
T149	0	628	0	0
T152	0	422	0	0
T153	0	138	0	0
T160	525	0	0	0
T161	1287	0	0	0
T162	17511	0	0	0
T163	2509	0	0	0
T164	502	0	0	0
T165	405	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6698	0	0
T69	12228	392	0	0
T77	1564	314	0	0
T78	2098	41	0	0
T79	1188	110	0	0
T80	0	390	0	0
T81	0	86	0	0
T147	0	821	0	0
T149	0	415	0	0
T152	0	314	0	0
T153	0	111	0	0
T160	525	0	0	0
T161	1287	0	0	0
T162	17511	0	0	0
T163	2509	0	0	0
T164	502	0	0	0
T165	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T25,T68,T69

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T25,T68,T69

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T25,T68,T69

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T68,T57
1	0	Covered	T42,T43,T44
1	1	Covered	T25,T68,T69

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T68,T69
0	1	Covered	T181,T182
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T68,T69
0	1	Covered	T25,T68,T69
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T68,T69
1	-	Covered	T25,T68,T69

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T68,T69
0	1	Covered	T25,T68,T69
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T68,T69
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T68,T69
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T68,T69
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T68,T69
DetectSt	-	-	-	-	1	-	-	Covered	T181,T182
DetectSt	-	-	-	-	0	1	-	Covered	T25,T68,T69
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T68,T69
StableSt	-	-	-	-	-	-	0	Covered	T25,T68,T69
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	57	0	0
CntIncr_A	7802930	45417	0	0
CntNoWrap_A	7802930	7196374	0	0
DetectStDropOut_A	7802930	2	0	0
DetectedOut_A	7802930	1862	0	0
DetectedPulseOut_A	7802930	25	0	0
DisabledIdleSt_A	7802930	7083934	0	0
DisabledNoDetection_A	7802930	7086148	0	0
EnterDebounceSt_A	7802930	30	0	0
EnterDetectSt_A	7802930	27	0	0
EnterStableSt_A	7802930	25	0	0
PulseIsPulse_A	7802930	25	0	0
StayInStableSt	7802930	1825	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	57	0	0
T25	27520	2	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	4	0	0
T69	0	2	0	0
T97	0	1	0	0
T100	0	2	0	0
T105	2729	0	0	0
T163	0	2	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T183	0	1	0	0
T185	0	2	0	0
T186	0	4	0	0
T187	0	2	0	0
T188	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	45417	0	0
T25	27520	48	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	174	0	0
T69	0	89	0	0
T97	0	20	0	0
T100	0	89	0	0
T105	2729	0	0	0
T163	0	90	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T183	0	99	0	0
T185	0	71	0	0
T186	0	174	0	0
T187	0	94	0	0
T188	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196374	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	2	0	0
T127	24866	0	0	0
T177	1478	0	0	0
T181	865	1	0	0
T182	794	1	0	0
T189	829	0	0	0
T190	409	0	0	0
T191	523	0	0	0
T192	484	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1862	0	0
T25	27520	79	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	169	0	0
T69	0	6	0	0
T100	0	130	0	0
T105	2729	0	0	0
T163	0	134	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T185	0	43	0	0
T186	0	67	0	0
T187	0	180	0	0
T188	422	0	0	0
T193	0	40	0	0
T194	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	25	0	0
T25	27520	1	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	2	0	0
T69	0	1	0	0
T100	0	1	0	0
T105	2729	0	0	0
T163	0	1	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	0	1	0	0
T188	422	0	0	0
T193	0	1	0	0
T194	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7083934	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7086148	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	30	0	0
T25	27520	1	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	2	0	0
T69	0	1	0	0
T97	0	1	0	0
T100	0	1	0	0
T105	2729	0	0	0
T163	0	1	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T183	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	0	1	0	0
T188	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	27	0	0
T25	27520	1	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	2	0	0
T69	0	1	0	0
T100	0	1	0	0
T105	2729	0	0	0
T163	0	1	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T181	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	0	1	0	0
T188	422	0	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	25	0	0
T25	27520	1	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	2	0	0
T69	0	1	0	0
T100	0	1	0	0
T105	2729	0	0	0
T163	0	1	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	0	1	0	0
T188	422	0	0	0
T193	0	1	0	0
T194	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	25	0	0
T25	27520	1	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	2	0	0
T69	0	1	0	0
T100	0	1	0	0
T105	2729	0	0	0
T163	0	1	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	0	1	0	0
T188	422	0	0	0
T193	0	1	0	0
T194	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1825	0	0
T25	27520	78	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	166	0	0
T69	0	5	0	0
T100	0	129	0	0
T105	2729	0	0	0
T163	0	132	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T185	0	41	0	0
T186	0	64	0	0
T187	0	179	0	0
T188	422	0	0	0
T193	0	38	0	0
T194	0	76	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	12	0	0
T25	27520	1	0	0
T61	17339	0	0	0
T62	14326	0	0	0
T67	3184	0	0	0
T68	1088	1	0	0
T69	0	1	0	0
T100	0	1	0	0
T105	2729	0	0	0
T168	11702	0	0	0
T169	434	0	0	0
T174	422	0	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	422	0	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T16,T19,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T16,T19,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T16,T19,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T25
1	0	Covered	T42,T44,T103
1	1	Covered	T16,T19,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T25
0	1	Covered	T66,T187,T127
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T25
0	1	Covered	T16,T64,T66
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T19,T25
1	-	Covered	T16,T64,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T19,T25
0	1	Covered	T16,T19,T25
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T19,T25
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T19,T25
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T19,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T127,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T19,T25
DetectSt	-	-	-	-	1	-	-	Covered	T66,T187,T127
DetectSt	-	-	-	-	0	1	-	Covered	T16,T19,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T64,T66
StableSt	-	-	-	-	-	-	0	Covered	T16,T19,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	149	0	0
CntIncr_A	7802930	143917	0	0
CntNoWrap_A	7802930	7196282	0	0
DetectStDropOut_A	7802930	5	0	0
DetectedOut_A	7802930	72902	0	0
DetectedPulseOut_A	7802930	67	0	0
DisabledIdleSt_A	7802930	6585986	0	0
DisabledNoDetection_A	7802930	6588183	0	0
EnterDebounceSt_A	7802930	77	0	0
EnterDetectSt_A	7802930	72	0	0
EnterStableSt_A	7802930	67	0	0
PulseIsPulse_A	7802930	67	0	0
StayInStableSt	7802930	72802	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802930	2943	0	0
gen_low_level_sva.LowLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	149	0	0
T16	625	2	0	0
T19	0	2	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	3	0	0
T66	0	4	0	0
T69	0	6	0	0
T72	0	2	0	0
T97	0	1	0	0
T99	0	4	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	143917	0	0
T16	625	25	0	0
T19	0	65	0	0
T25	0	25	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	64	0	0
T66	0	176	0	0
T69	0	245	0	0
T72	0	47	0	0
T97	0	20	0	0
T99	0	30	0	0
T199	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196282	0	0
T16	625	222	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	5	0	0
T66	1060	1	0	0
T127	24866	1	0	0
T129	64121	1	0	0
T177	1478	0	0	0
T187	910	1	0	0
T200	0	1	0	0
T201	508	0	0	0
T202	422	0	0	0
T203	8764	0	0	0
T204	503	0	0	0
T205	551	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	72902	0	0
T16	625	9	0	0
T19	0	38	0	0
T25	0	163	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	12	0	0
T66	0	156	0	0
T69	0	261	0	0
T72	0	45	0	0
T99	0	80	0	0
T199	0	138	0	0
T206	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	67	0	0
T16	625	1	0	0
T19	0	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T69	0	3	0	0
T72	0	1	0	0
T99	0	2	0	0
T199	0	1	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6585986	0	0
T16	625	3	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6588183	0	0
T16	625	3	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	77	0	0
T16	625	1	0	0
T19	0	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	2	0	0
T66	0	2	0	0
T69	0	3	0	0
T72	0	1	0	0
T97	0	1	0	0
T99	0	2	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	72	0	0
T16	625	1	0	0
T19	0	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T66	0	2	0	0
T69	0	3	0	0
T72	0	1	0	0
T99	0	2	0	0
T199	0	1	0	0
T206	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	67	0	0
T16	625	1	0	0
T19	0	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T69	0	3	0	0
T72	0	1	0	0
T99	0	2	0	0
T199	0	1	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	67	0	0
T16	625	1	0	0
T19	0	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T69	0	3	0	0
T72	0	1	0	0
T99	0	2	0	0
T199	0	1	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	72802	0	0
T16	625	8	0	0
T19	0	36	0	0
T25	0	161	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	11	0	0
T66	0	155	0	0
T69	0	256	0	0
T72	0	43	0	0
T99	0	78	0	0
T199	0	136	0	0
T206	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	2943	0	0
T16	625	1	0	0
T29	500	0	0	0
T30	2227	4	0	0
T31	526	7	0	0
T32	8457	0	0	0
T33	505	6	0	0
T35	0	11	0	0
T36	0	3	0	0
T44	503	4	0	0
T91	482	4	0	0
T103	525	5	0	0
T111	522	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	33	0	0
T16	625	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T69	0	1	0	0
T99	0	2	0	0
T183	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T206	0	1	0	0
T207	0	1	0	0