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Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sysrst_ctrl_autoblock


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.89 100.00 94.44 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.89 100.00 94.44 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.89 100.00 94.44 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.89 100.00 94.44 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.67 100.00 93.33 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.67 100.00 93.33 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 95.65 100.00 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 95.65 100.00 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00

57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low 58 1/1 assign trigger_active = (trigger_i == 1'b0); Tests: T4 T12 T13  59 end else begin : gen_trigger_active_high 60 assign trigger_active = (trigger_i == 1'b1); 61 end 62 63 // In case of edge events, we also need to detect the transition. 64 logic trigger_event; 65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge 66 // This flop is always active, no matter the enable state. 67 logic trigger_active_q; 68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg 69 1/1 if (!rst_ni) begin Tests: T1 T2 T4  70 1/1 trigger_active_q <= 1'b0; Tests: T1 T2 T4  71 end else begin 72 1/1 trigger_active_q <= trigger_active; Tests: T1 T2 T4  73 end 74 end 75 76 1/1 assign trigger_event = trigger_active & ~trigger_active_q; Tests: T1 T2 T4  77 // In case of level events, the event is equal to the level being active. 78 end else begin : gen_trigger_event_level 79 assign trigger_event = trigger_active; 80 end 81 82 ///////////////// 83 // Timer Logic // 84 ///////////////// 85 86 // Take the maximum width of both timer values. 87 localparam int unsigned TimerWidth = 88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth; 89 90 logic cnt_en, cnt_clr; 91 logic [TimerWidth-1:0] cnt_d, cnt_q; 92 1/1 assign cnt_d = (cnt_clr) ? '0 : Tests: T4 T27 T58  93 (cnt_en) ? cnt_q + 1'b1 : 94 cnt_q; 95 96 97 logic cnt_done, thresh_sel; 98 logic [TimerWidth-1:0] thresh; 99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : Tests: T4 T27 T28  100 TimerWidth'(cfg_debounce_timer_i); 101 1/1 assign cnt_done = (cnt_q >= thresh); Tests: T4 T27 T28  102 103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg 104 1/1 if (!rst_ni) begin Tests: T1 T2 T4  105 1/1 cnt_q <= '0; Tests: T1 T2 T4  106 end else begin 107 1/1 cnt_q <= cnt_d; Tests: T1 T2 T4  108 end 109 end 110 111 ///////// 112 // FSM // 113 ///////// 114 115 typedef enum logic [1:0] { 116 IdleSt, 117 DebounceSt, 118 DetectSt, 119 StableSt 120 } state_t; 121 122 state_t state_d, state_q; 123 124 always_comb begin : p_fsm 125 1/1 state_d = state_q; Tests: T1 T2 T4  126 127 // Counter controls (clear has priority). 128 1/1 cnt_clr = 1'b0; Tests: T1 T2 T4  129 1/1 cnt_en = 1'b0; Tests: T1 T2 T4  130 131 // Detected outputs 132 1/1 event_detected_o = 1'b0; Tests: T1 T2 T4  133 1/1 event_detected_pulse_o = 1'b0; Tests: T1 T2 T4  134 135 // Threshold select 136 // 0: debounce 137 // 1: detect 138 1/1 thresh_sel = 1'b0; Tests: T1 T2 T4  139 140 1/1 unique case (state_q) Tests: T1 T2 T4  141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 1/1 if (trigger_event && cfg_enable_i) begin Tests: T1 T2 T4  148 1/1 state_d = DebounceSt; Tests: T4 T27 T58  149 1/1 cnt_en = 1'b1; Tests: T4 T27 T58  150 end MISSING_ELSE 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 1/1 cnt_en = 1'b1; Tests: T4 T27 T58  161 // Unconditionally go back to idle if the detector is disabled. 162 1/1 if (!cfg_enable_i) begin Tests: T4 T27 T58  163 1/1 state_d = IdleSt; Tests: T56  164 1/1 cnt_clr = 1'b1; Tests: T56  165 1/1 end else if (cnt_done) begin Tests: T4 T27 T58  166 1/1 cnt_clr = 1'b1; Tests: T4 T27 T58  167 1/1 if (trigger_active) begin Tests: T4 T27 T58  168 1/1 state_d = DetectSt; Tests: T4 T27 T58  169 end else begin 170 1/1 state_d = IdleSt; Tests: T61 T115 T123  171 end 172 end MISSING_ELSE 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 1/1 thresh_sel = 1'b1; Tests: T4 T27 T58  182 1/1 cnt_en = 1'b1; Tests: T4 T27 T58  183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 1/1 if (!cfg_enable_i || !trigger_active) begin Tests: T4 T27 T58  186 1/1 state_d = IdleSt; Tests: T63 T123 T135  187 1/1 cnt_clr = 1'b1; Tests: T63 T123 T135  188 // If the trigger is active, count up. 189 end else begin 190 1/1 if (cnt_done) begin Tests: T4 T27 T58  191 1/1 state_d = StableSt; Tests: T4 T27 T58  192 1/1 cnt_clr = 1'b1; Tests: T4 T27 T58  193 1/1 event_detected_o = 1'b1; Tests: T4 T27 T58  194 1/1 event_detected_pulse_o = 1'b1; Tests: T4 T27 T58  195 end ==> MISSING_ELSE 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin Tests: T4 T27 T58  206 1/1 state_d = IdleSt; Tests: T4 T27 T58  207 // Otherwise keep the event detected output signal high. 208 end else begin 209 1/1 event_detected_o = 1'b1; Tests: T4 T27 T58  210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; Exclude Annotation: VC_COV_UNR 215 endcase // state_q 216 end 217 218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg 219 1/1 if (!rst_ni) begin Tests: T1 T2 T4  220 1/1 state_q <= IdleSt; Tests: T1 T2 T4  221 end else begin 222 1/1 state_q <= state_d; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT4,T12,T13
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT4,T12,T13
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT4,T27,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT4,T27,T58

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT4,T27,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT4,T27,T58
10CoveredT4,T12,T13
11CoveredT4,T27,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT4,T27,T58
01CoveredT63,T123,T135
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT4,T27,T58
01CoveredT4,T27,T58
10CoveredT21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT4,T27,T58
1-CoveredT4,T27,T58

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T4,T27,T58
DetectSt 168 Covered T4,T27,T58
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T4,T27,T58


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T4,T27,T58
DebounceSt->IdleSt 163 Covered T61,T56,T131
DetectSt->IdleSt 186 Covered T63,T123,T135
DetectSt->StableSt 191 Covered T4,T27,T58
IdleSt->DebounceSt 148 Covered T4,T27,T58
StableSt->IdleSt 206 Covered T4,T27,T58



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00


92 assign cnt_d = (cnt_clr) ? '0 : -1- ==> 93 (cnt_en) ? cnt_q + 1'b1 : -2- ==> ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T27,T58
0 1 Covered T4,T27,T58
0 0 Excluded T1,T2,T4 VC_COV_UNR


99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T27,T58
0 Covered T1,T2,T4


104 if (!rst_ni) begin -1- 105 cnt_q <= '0; ==> 106 end else begin 107 cnt_q <= cnt_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


140 unique case (state_q) -1- 141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 if (trigger_event && cfg_enable_i) begin -2- 148 state_d = DebounceSt; ==> 149 cnt_en = 1'b1; 150 end MISSING_ELSE ==> 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 cnt_en = 1'b1; 161 // Unconditionally go back to idle if the detector is disabled. 162 if (!cfg_enable_i) begin -3- 163 state_d = IdleSt; ==> 164 cnt_clr = 1'b1; 165 end else if (cnt_done) begin -4- 166 cnt_clr = 1'b1; 167 if (trigger_active) begin -5- 168 state_d = DetectSt; ==> 169 end else begin 170 state_d = IdleSt; ==> 171 end 172 end MISSING_ELSE ==> 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 thresh_sel = 1'b1; 182 cnt_en = 1'b1; 183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 if (!cfg_enable_i || !trigger_active) begin -6- 186 state_d = IdleSt; ==> 187 cnt_clr = 1'b1; 188 // If the trigger is active, count up. 189 end else begin 190 if (cnt_done) begin -7- 191 state_d = StableSt; ==> 192 cnt_clr = 1'b1; 193 event_detected_o = 1'b1; 194 event_detected_pulse_o = 1'b1; 195 end MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin -8- 206 state_d = IdleSt; ==> 207 // Otherwise keep the event detected output signal high. 208 end else begin 209 event_detected_o = 1'b1; ==> 210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; ==> (Excluded) Exclude Annotation: VC_COV_UNR

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T4,T27,T58
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T56
DebounceSt - 0 1 1 - - - Covered T4,T27,T58
DebounceSt - 0 1 0 - - - Covered T61,T115,T123
DebounceSt - 0 0 - - - - Covered T4,T27,T58
DetectSt - - - - 1 - - Covered T63,T123,T135
DetectSt - - - - 0 1 - Covered T4,T27,T58
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T4,T27,T58
StableSt - - - - - - 0 Covered T4,T27,T58
default - - - - - - - Excluded VC_COV_UNR


219 if (!rst_ni) begin -1- 220 state_q <= IdleSt; ==> 221 end else begin 222 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


69 if (!rst_ni) begin -1- 70 trigger_active_q <= 1'b0; ==> 71 end else begin 72 trigger_active_q <= trigger_active; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7014086 336 0 0
CntIncr_A 7014086 231254 0 0
CntNoWrap_A 7014086 6364514 0 0
DetectStDropOut_A 7014086 5 0 0
DetectedOut_A 7014086 1016 0 0
DetectedPulseOut_A 7014086 152 0 0
DisabledIdleSt_A 7014086 6125799 0 0
DisabledNoDetection_A 7014086 6128131 0 0
EnterDebounceSt_A 7014086 184 0 0
EnterDetectSt_A 7014086 157 0 0
EnterStableSt_A 7014086 152 0 0
PulseIsPulse_A 7014086 152 0 0
StayInStableSt 7014086 864 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7014086 7110 0 0
gen_low_level_sva.LowLevelEvent_A 7014086 6367248 0 0
gen_not_sticky_sva.StableStDropOut_A 7014086 151 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 336 0 0
T3 481 0 0 0
T4 666 2 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 2 0 0
T22 491 0 0 0
T27 0 4 0 0
T31 448 0 0 0
T56 0 1 0 0
T58 0 4 0 0
T61 0 3 0 0
T62 0 2 0 0
T63 0 4 0 0
T64 0 4 0 0
T133 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 231254 0 0
T3 481 0 0 0
T4 666 56 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 15 0 0
T22 491 0 0 0
T27 0 86 0 0
T31 448 0 0 0
T56 0 33 0 0
T58 0 55 0 0
T61 0 74 0 0
T62 0 73 0 0
T63 0 174 0 0
T64 0 144 0 0
T131 0 42 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6364514 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 263 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 5 0 0
T52 494 0 0 0
T63 765 1 0 0
T79 493 0 0 0
T108 0 1 0 0
T123 0 1 0 0
T135 0 1 0 0
T141 0 1 0 0
T145 522 0 0 0
T146 401 0 0 0
T147 1460 0 0 0
T148 422 0 0 0
T149 419 0 0 0
T150 507 0 0 0
T151 710 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 1016 0 0
T3 481 0 0 0
T4 666 5 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 16 0 0
T22 491 0 0 0
T27 0 18 0 0
T31 448 0 0 0
T58 0 13 0 0
T61 0 6 0 0
T62 0 8 0 0
T63 0 7 0 0
T64 0 14 0 0
T133 0 7 0 0
T156 0 10 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 152 0 0
T3 481 0 0 0
T4 666 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T27 0 2 0 0
T31 448 0 0 0
T58 0 2 0 0
T61 0 1 0 0
T62 0 1 0 0
T63 0 1 0 0
T64 0 2 0 0
T133 0 1 0 0
T156 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6125799 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 161 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6128131 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 162 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 184 0 0
T3 481 0 0 0
T4 666 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T27 0 2 0 0
T31 448 0 0 0
T56 0 1 0 0
T58 0 2 0 0
T61 0 2 0 0
T62 0 1 0 0
T63 0 2 0 0
T64 0 2 0 0
T131 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 157 0 0
T3 481 0 0 0
T4 666 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T27 0 2 0 0
T31 448 0 0 0
T58 0 2 0 0
T61 0 1 0 0
T62 0 1 0 0
T63 0 2 0 0
T64 0 2 0 0
T133 0 1 0 0
T156 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 152 0 0
T3 481 0 0 0
T4 666 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T27 0 2 0 0
T31 448 0 0 0
T58 0 2 0 0
T61 0 1 0 0
T62 0 1 0 0
T63 0 1 0 0
T64 0 2 0 0
T133 0 1 0 0
T156 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 152 0 0
T3 481 0 0 0
T4 666 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 1 0 0
T22 491 0 0 0
T27 0 2 0 0
T31 448 0 0 0
T58 0 2 0 0
T61 0 1 0 0
T62 0 1 0 0
T63 0 1 0 0
T64 0 2 0 0
T133 0 1 0 0
T156 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 864 0 0
T3 481 0 0 0
T4 666 4 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T21 0 15 0 0
T22 491 0 0 0
T27 0 16 0 0
T31 448 0 0 0
T58 0 11 0 0
T61 0 5 0 0
T62 0 7 0 0
T63 0 6 0 0
T64 0 12 0 0
T133 0 6 0 0
T156 0 8 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 7110 0 0
T3 481 0 0 0
T4 666 3 0 0
T5 0 2 0 0
T12 747 5 0 0
T13 523 5 0 0
T14 412 2 0 0
T15 423 3 0 0
T16 1038 0 0 0
T17 426 1 0 0
T22 491 6 0 0
T23 0 7 0 0
T25 0 4 0 0
T31 448 0 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6367248 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 151 0 0
T3 481 0 0 0
T4 666 1 0 0
T12 747 0 0 0
T13 523 0 0 0
T14 412 0 0 0
T15 423 0 0 0
T16 1038 0 0 0
T17 426 0 0 0
T22 491 0 0 0
T27 0 2 0 0
T31 448 0 0 0
T55 0 3 0 0
T58 0 2 0 0
T61 0 1 0 0
T62 0 1 0 0
T63 0 1 0 0
T64 0 2 0 0
T133 0 1 0 0
T156 0 2 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00

57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low 58 1/1 assign trigger_active = (trigger_i == 1'b0); Tests: T4 T12 T13  59 end else begin : gen_trigger_active_high 60 assign trigger_active = (trigger_i == 1'b1); 61 end 62 63 // In case of edge events, we also need to detect the transition. 64 logic trigger_event; 65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge 66 // This flop is always active, no matter the enable state. 67 logic trigger_active_q; 68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg 69 1/1 if (!rst_ni) begin Tests: T1 T2 T4  70 1/1 trigger_active_q <= 1'b0; Tests: T1 T2 T4  71 end else begin 72 1/1 trigger_active_q <= trigger_active; Tests: T1 T2 T4  73 end 74 end 75 76 1/1 assign trigger_event = trigger_active & ~trigger_active_q; Tests: T1 T2 T4  77 // In case of level events, the event is equal to the level being active. 78 end else begin : gen_trigger_event_level 79 assign trigger_event = trigger_active; 80 end 81 82 ///////////////// 83 // Timer Logic // 84 ///////////////// 85 86 // Take the maximum width of both timer values. 87 localparam int unsigned TimerWidth = 88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth; 89 90 logic cnt_en, cnt_clr; 91 logic [TimerWidth-1:0] cnt_d, cnt_q; 92 1/1 assign cnt_d = (cnt_clr) ? '0 : Tests: T5 T9 T21  93 (cnt_en) ? cnt_q + 1'b1 : 94 cnt_q; 95 96 97 logic cnt_done, thresh_sel; 98 logic [TimerWidth-1:0] thresh; 99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : Tests: T12 T5 T9  100 TimerWidth'(cfg_debounce_timer_i); 101 1/1 assign cnt_done = (cnt_q >= thresh); Tests: T12 T5 T9  102 103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg 104 1/1 if (!rst_ni) begin Tests: T1 T2 T4  105 1/1 cnt_q <= '0; Tests: T1 T2 T4  106 end else begin 107 1/1 cnt_q <= cnt_d; Tests: T1 T2 T4  108 end 109 end 110 111 ///////// 112 // FSM // 113 ///////// 114 115 typedef enum logic [1:0] { 116 IdleSt, 117 DebounceSt, 118 DetectSt, 119 StableSt 120 } state_t; 121 122 state_t state_d, state_q; 123 124 always_comb begin : p_fsm 125 1/1 state_d = state_q; Tests: T1 T2 T4  126 127 // Counter controls (clear has priority). 128 1/1 cnt_clr = 1'b0; Tests: T1 T2 T4  129 1/1 cnt_en = 1'b0; Tests: T1 T2 T4  130 131 // Detected outputs 132 1/1 event_detected_o = 1'b0; Tests: T1 T2 T4  133 1/1 event_detected_pulse_o = 1'b0; Tests: T1 T2 T4  134 135 // Threshold select 136 // 0: debounce 137 // 1: detect 138 1/1 thresh_sel = 1'b0; Tests: T1 T2 T4  139 140 1/1 unique case (state_q) Tests: T1 T2 T4  141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 1/1 if (trigger_event && cfg_enable_i) begin Tests: T1 T2 T4  148 1/1 state_d = DebounceSt; Tests: T5 T9 T21  149 1/1 cnt_en = 1'b1; Tests: T5 T9 T21  150 end MISSING_ELSE 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 1/1 cnt_en = 1'b1; Tests: T5 T9 T21  161 // Unconditionally go back to idle if the detector is disabled. 162 1/1 if (!cfg_enable_i) begin Tests: T5 T9 T21  163 1/1 state_d = IdleSt; Tests: T21 T56  164 1/1 cnt_clr = 1'b1; Tests: T21 T56  165 1/1 end else if (cnt_done) begin Tests: T5 T9 T21  166 1/1 cnt_clr = 1'b1; Tests: T5 T9 T39  167 1/1 if (trigger_active) begin Tests: T5 T9 T39  168 1/1 state_d = DetectSt; Tests: T5 T9 T39  169 end else begin 170 1/1 state_d = IdleSt; Tests: T70 T54 T96  171 end 172 end MISSING_ELSE 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 1/1 thresh_sel = 1'b1; Tests: T5 T9 T39  182 1/1 cnt_en = 1'b1; Tests: T5 T9 T39  183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 1/1 if (!cfg_enable_i || !trigger_active) begin Tests: T5 T9 T39  186 1/1 state_d = IdleSt; Tests: T39 T129 T130  187 1/1 cnt_clr = 1'b1; Tests: T39 T129 T130  188 // If the trigger is active, count up. 189 end else begin 190 1/1 if (cnt_done) begin Tests: T5 T9 T54  191 1/1 state_d = StableSt; Tests: T5 T9 T54  192 1/1 cnt_clr = 1'b1; Tests: T5 T9 T54  193 1/1 event_detected_o = 1'b1; Tests: T5 T9 T54  194 1/1 event_detected_pulse_o = 1'b1; Tests: T5 T9 T54  195 end ==> MISSING_ELSE 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin Tests: T5 T9 T54  206 1/1 state_d = IdleSt; Tests: T5 T9 T54  207 // Otherwise keep the event detected output signal high. 208 end else begin 209 1/1 event_detected_o = 1'b1; Tests: T5 T9 T54  210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; Exclude Annotation: VC_COV_UNR 215 endcase // state_q 216 end 217 218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg 219 1/1 if (!rst_ni) begin Tests: T1 T2 T4  220 1/1 state_q <= IdleSt; Tests: T1 T2 T4  221 end else begin 222 1/1 state_q <= state_d; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
TotalCoveredPercent
Conditions181794.44
Logical181794.44
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT4,T12,T13
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT4,T12,T13
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT5,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T9,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT5,T9,T21
10CoveredT4,T12,T13
11CoveredT5,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT5,T9,T54
01CoveredT39,T129,T130
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT5,T9,T54
01Unreachable
10CoveredT5,T9,T54

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T5,T9,T21
DetectSt 168 Covered T5,T9,T39
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T5,T9,T54


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T5,T9,T39
DebounceSt->IdleSt 163 Covered T21,T70,T56
DetectSt->IdleSt 186 Covered T39,T129,T130
DetectSt->StableSt 191 Covered T5,T9,T54
IdleSt->DebounceSt 148 Covered T5,T9,T21
StableSt->IdleSt 206 Covered T5,T9,T54



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00


92 assign cnt_d = (cnt_clr) ? '0 : -1- ==> 93 (cnt_en) ? cnt_q + 1'b1 : -2- ==> ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T5,T9,T21
0 1 Covered T5,T9,T21
0 0 Excluded T1,T2,T4 VC_COV_UNR


99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T5,T9,T39
0 Covered T1,T2,T4


104 if (!rst_ni) begin -1- 105 cnt_q <= '0; ==> 106 end else begin 107 cnt_q <= cnt_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


140 unique case (state_q) -1- 141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 if (trigger_event && cfg_enable_i) begin -2- 148 state_d = DebounceSt; ==> 149 cnt_en = 1'b1; 150 end MISSING_ELSE ==> 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 cnt_en = 1'b1; 161 // Unconditionally go back to idle if the detector is disabled. 162 if (!cfg_enable_i) begin -3- 163 state_d = IdleSt; ==> 164 cnt_clr = 1'b1; 165 end else if (cnt_done) begin -4- 166 cnt_clr = 1'b1; 167 if (trigger_active) begin -5- 168 state_d = DetectSt; ==> 169 end else begin 170 state_d = IdleSt; ==> 171 end 172 end MISSING_ELSE ==> 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 thresh_sel = 1'b1; 182 cnt_en = 1'b1; 183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 if (!cfg_enable_i || !trigger_active) begin -6- 186 state_d = IdleSt; ==> 187 cnt_clr = 1'b1; 188 // If the trigger is active, count up. 189 end else begin 190 if (cnt_done) begin -7- 191 state_d = StableSt; ==> 192 cnt_clr = 1'b1; 193 event_detected_o = 1'b1; 194 event_detected_pulse_o = 1'b1; 195 end MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin -8- 206 state_d = IdleSt; ==> 207 // Otherwise keep the event detected output signal high. 208 end else begin 209 event_detected_o = 1'b1; ==> 210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; ==> (Excluded) Exclude Annotation: VC_COV_UNR

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T5,T9,T21
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T21,T56
DebounceSt - 0 1 1 - - - Covered T5,T9,T39
DebounceSt - 0 1 0 - - - Covered T70,T54,T96
DebounceSt - 0 0 - - - - Covered T5,T9,T21
DetectSt - - - - 1 - - Covered T39,T129,T130
DetectSt - - - - 0 1 - Covered T5,T9,T54
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T5,T9,T54
StableSt - - - - - - 0 Covered T5,T9,T54
default - - - - - - - Excluded VC_COV_UNR


219 if (!rst_ni) begin -1- 220 state_q <= IdleSt; ==> 221 end else begin 222 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


69 if (!rst_ni) begin -1- 70 trigger_active_q <= 1'b0; ==> 71 end else begin 72 trigger_active_q <= trigger_active; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7014086 171 0 0
CntIncr_A 7014086 177386 0 0
CntNoWrap_A 7014086 6364679 0 0
DetectStDropOut_A 7014086 10 0 0
DetectedOut_A 7014086 527300 0 0
DetectedPulseOut_A 7014086 48 0 0
DisabledIdleSt_A 7014086 4996405 0 0
DisabledNoDetection_A 7014086 4998801 0 0
EnterDebounceSt_A 7014086 114 0 0
EnterDetectSt_A 7014086 58 0 0
EnterStableSt_A 7014086 48 0 0
PulseIsPulse_A 7014086 48 0 0
StayInStableSt 7014086 527252 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7014086 7110 0 0
gen_low_level_sva.LowLevelEvent_A 7014086 6367248 0 0
gen_sticky_sva.StableStDropOut_A 7014086 401135 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 171 0 0
T5 689 2 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 2 0 0
T21 0 2 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 2 0 0
T54 0 5 0 0
T55 0 2 0 0
T56 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 177386 0 0
T5 689 52 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 79 0 0
T21 0 51 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 78 0 0
T54 0 302 0 0
T55 0 80 0 0
T56 0 50 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 44 0 0
T96 0 24 0 0
T97 0 29 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6364679 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 10 0 0
T39 1128 1 0 0
T40 29410 0 0 0
T53 806 0 0 0
T62 707 0 0 0
T78 499 0 0 0
T99 4402 0 0 0
T129 0 2 0 0
T130 0 5 0 0
T166 0 2 0 0
T167 408 0 0 0
T168 422 0 0 0
T169 439 0 0 0
T170 503 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 527300 0 0
T5 689 145 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 379 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 604 0 0
T55 0 396 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T97 0 81 0 0
T100 0 22 0 0
T129 0 68 0 0
T162 0 162 0 0
T164 0 107 0 0
T165 0 114 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 48 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 1 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T97 0 1 0 0
T100 0 1 0 0
T129 0 2 0 0
T162 0 2 0 0
T164 0 1 0 0
T165 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 4996405 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 4998801 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 114 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T21 0 2 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 4 0 0
T55 0 1 0 0
T56 0 2 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 58 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 1 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T97 0 1 0 0
T100 0 1 0 0
T129 0 4 0 0
T162 0 2 0 0
T164 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 48 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 1 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T97 0 1 0 0
T100 0 1 0 0
T129 0 2 0 0
T162 0 2 0 0
T164 0 1 0 0
T165 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 48 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 1 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T97 0 1 0 0
T100 0 1 0 0
T129 0 2 0 0
T162 0 2 0 0
T164 0 1 0 0
T165 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 527252 0 0
T5 689 144 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 378 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 603 0 0
T55 0 395 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T97 0 80 0 0
T100 0 21 0 0
T129 0 66 0 0
T162 0 160 0 0
T164 0 106 0 0
T165 0 112 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 7110 0 0
T3 481 0 0 0
T4 666 3 0 0
T5 0 2 0 0
T12 747 5 0 0
T13 523 5 0 0
T14 412 2 0 0
T15 423 3 0 0
T16 1038 0 0 0
T17 426 1 0 0
T22 491 6 0 0
T23 0 7 0 0
T25 0 4 0 0
T31 448 0 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6367248 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 401135 0 0
T5 689 39 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 128 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 257 0 0
T55 0 61 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T97 0 179 0 0
T100 0 247 0 0
T129 0 436 0 0
T162 0 452 0 0
T164 0 92 0 0
T165 0 205 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00

59 end else begin : gen_trigger_active_high 60 1/1 assign trigger_active = (trigger_i == 1'b1); Tests: T12 T13 T14  61 end 62 63 // In case of edge events, we also need to detect the transition. 64 logic trigger_event; 65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge 66 // This flop is always active, no matter the enable state. 67 logic trigger_active_q; 68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg 69 1/1 if (!rst_ni) begin Tests: T1 T2 T4  70 1/1 trigger_active_q <= 1'b0; Tests: T1 T2 T4  71 end else begin 72 1/1 trigger_active_q <= trigger_active; Tests: T1 T2 T4  73 end 74 end 75 76 1/1 assign trigger_event = trigger_active & ~trigger_active_q; Tests: T12 T13 T14  77 // In case of level events, the event is equal to the level being active. 78 end else begin : gen_trigger_event_level 79 assign trigger_event = trigger_active; 80 end 81 82 ///////////////// 83 // Timer Logic // 84 ///////////////// 85 86 // Take the maximum width of both timer values. 87 localparam int unsigned TimerWidth = 88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth; 89 90 logic cnt_en, cnt_clr; 91 logic [TimerWidth-1:0] cnt_d, cnt_q; 92 1/1 assign cnt_d = (cnt_clr) ? '0 : Tests: T5 T9 T21  93 (cnt_en) ? cnt_q + 1'b1 : 94 cnt_q; 95 96 97 logic cnt_done, thresh_sel; 98 logic [TimerWidth-1:0] thresh; 99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : Tests: T12 T5 T9  100 TimerWidth'(cfg_debounce_timer_i); 101 1/1 assign cnt_done = (cnt_q >= thresh); Tests: T12 T5 T9  102 103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg 104 1/1 if (!rst_ni) begin Tests: T1 T2 T4  105 1/1 cnt_q <= '0; Tests: T1 T2 T4  106 end else begin 107 1/1 cnt_q <= cnt_d; Tests: T1 T2 T4  108 end 109 end 110 111 ///////// 112 // FSM // 113 ///////// 114 115 typedef enum logic [1:0] { 116 IdleSt, 117 DebounceSt, 118 DetectSt, 119 StableSt 120 } state_t; 121 122 state_t state_d, state_q; 123 124 always_comb begin : p_fsm 125 1/1 state_d = state_q; Tests: T12 T13 T14  126 127 // Counter controls (clear has priority). 128 1/1 cnt_clr = 1'b0; Tests: T12 T13 T14  129 1/1 cnt_en = 1'b0; Tests: T12 T13 T14  130 131 // Detected outputs 132 1/1 event_detected_o = 1'b0; Tests: T12 T13 T14  133 1/1 event_detected_pulse_o = 1'b0; Tests: T12 T13 T14  134 135 // Threshold select 136 // 0: debounce 137 // 1: detect 138 1/1 thresh_sel = 1'b0; Tests: T12 T13 T14  139 140 1/1 unique case (state_q) Tests: T12 T13 T14  141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 1/1 if (trigger_event && cfg_enable_i) begin Tests: T12 T13 T14  148 1/1 state_d = DebounceSt; Tests: T5 T9 T21  149 1/1 cnt_en = 1'b1; Tests: T5 T9 T21  150 end MISSING_ELSE 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 1/1 cnt_en = 1'b1; Tests: T5 T9 T21  161 // Unconditionally go back to idle if the detector is disabled. 162 1/1 if (!cfg_enable_i) begin Tests: T5 T9 T21  163 1/1 state_d = IdleSt; Tests: T21 T56  164 1/1 cnt_clr = 1'b1; Tests: T21 T56  165 1/1 end else if (cnt_done) begin Tests: T5 T9 T21  166 1/1 cnt_clr = 1'b1; Tests: T5 T9 T39  167 1/1 if (trigger_active) begin Tests: T5 T9 T39  168 1/1 state_d = DetectSt; Tests: T5 T9 T39  169 end else begin 170 1/1 state_d = IdleSt; Tests: T97 T127 T171  171 end 172 end MISSING_ELSE 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 1/1 thresh_sel = 1'b1; Tests: T5 T9 T39  182 1/1 cnt_en = 1'b1; Tests: T5 T9 T39  183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 1/1 if (!cfg_enable_i || !trigger_active) begin Tests: T5 T9 T39  186 1/1 state_d = IdleSt; Tests: T97 T127 T128  187 1/1 cnt_clr = 1'b1; Tests: T97 T127 T128  188 // If the trigger is active, count up. 189 end else begin 190 1/1 if (cnt_done) begin Tests: T5 T9 T39  191 1/1 state_d = StableSt; Tests: T5 T9 T39  192 1/1 cnt_clr = 1'b1; Tests: T5 T9 T39  193 1/1 event_detected_o = 1'b1; Tests: T5 T9 T39  194 1/1 event_detected_pulse_o = 1'b1; Tests: T5 T9 T39  195 end ==> MISSING_ELSE 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin Tests: T5 T9 T39  206 1/1 state_d = IdleSt; Tests: T5 T9 T39  207 // Otherwise keep the event detected output signal high. 208 end else begin 209 1/1 event_detected_o = 1'b1; Tests: T5 T9 T39  210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; Exclude Annotation: VC_COV_UNR 215 endcase // state_q 216 end 217 218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg 219 1/1 if (!rst_ni) begin Tests: T1 T2 T4  220 1/1 state_q <= IdleSt; Tests: T1 T2 T4  221 end else begin 222 1/1 state_q <= state_d; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
TotalCoveredPercent
Conditions181794.44
Logical181794.44
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT12,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT12,T13,T14
11CoveredT12,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT5,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T9,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT5,T9,T21
10CoveredT12,T13,T14
11CoveredT5,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT5,T9,T39
01CoveredT97,T127,T128
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT5,T9,T39
01Unreachable
10CoveredT5,T9,T39

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T5,T9,T21
DetectSt 168 Covered T5,T9,T39
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T5,T9,T39


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T5,T9,T39
DebounceSt->IdleSt 163 Covered T21,T56,T97
DetectSt->IdleSt 186 Covered T97,T127,T128
DetectSt->StableSt 191 Covered T5,T9,T39
IdleSt->DebounceSt 148 Covered T5,T9,T21
StableSt->IdleSt 206 Covered T5,T9,T39



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00


92 assign cnt_d = (cnt_clr) ? '0 : -1- ==> 93 (cnt_en) ? cnt_q + 1'b1 : -2- ==> ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T5,T9,T21
0 1 Covered T5,T9,T21
0 0 Excluded T1,T2,T4 VC_COV_UNR


99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T5,T9,T39
0 Covered T1,T2,T4


104 if (!rst_ni) begin -1- 105 cnt_q <= '0; ==> 106 end else begin 107 cnt_q <= cnt_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


140 unique case (state_q) -1- 141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 if (trigger_event && cfg_enable_i) begin -2- 148 state_d = DebounceSt; ==> 149 cnt_en = 1'b1; 150 end MISSING_ELSE ==> 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 cnt_en = 1'b1; 161 // Unconditionally go back to idle if the detector is disabled. 162 if (!cfg_enable_i) begin -3- 163 state_d = IdleSt; ==> 164 cnt_clr = 1'b1; 165 end else if (cnt_done) begin -4- 166 cnt_clr = 1'b1; 167 if (trigger_active) begin -5- 168 state_d = DetectSt; ==> 169 end else begin 170 state_d = IdleSt; ==> 171 end 172 end MISSING_ELSE ==> 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 thresh_sel = 1'b1; 182 cnt_en = 1'b1; 183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 if (!cfg_enable_i || !trigger_active) begin -6- 186 state_d = IdleSt; ==> 187 cnt_clr = 1'b1; 188 // If the trigger is active, count up. 189 end else begin 190 if (cnt_done) begin -7- 191 state_d = StableSt; ==> 192 cnt_clr = 1'b1; 193 event_detected_o = 1'b1; 194 event_detected_pulse_o = 1'b1; 195 end MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin -8- 206 state_d = IdleSt; ==> 207 // Otherwise keep the event detected output signal high. 208 end else begin 209 event_detected_o = 1'b1; ==> 210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; ==> (Excluded) Exclude Annotation: VC_COV_UNR

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T5,T9,T21
IdleSt 0 - - - - - - Covered T12,T13,T14
DebounceSt - 1 - - - - - Covered T21,T56
DebounceSt - 0 1 1 - - - Covered T5,T9,T39
DebounceSt - 0 1 0 - - - Covered T97,T127,T171
DebounceSt - 0 0 - - - - Covered T5,T9,T21
DetectSt - - - - 1 - - Covered T97,T127,T128
DetectSt - - - - 0 1 - Covered T5,T9,T39
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T5,T9,T39
StableSt - - - - - - 0 Covered T5,T9,T39
default - - - - - - - Excluded VC_COV_UNR


219 if (!rst_ni) begin -1- 220 state_q <= IdleSt; ==> 221 end else begin 222 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


69 if (!rst_ni) begin -1- 70 trigger_active_q <= 1'b0; ==> 71 end else begin 72 trigger_active_q <= trigger_active; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7014086 150 0 0
CntIncr_A 7014086 73605 0 0
CntNoWrap_A 7014086 6364700 0 0
DetectStDropOut_A 7014086 5 0 0
DetectedOut_A 7014086 34596 0 0
DetectedPulseOut_A 7014086 58 0 0
DisabledIdleSt_A 7014086 4996405 0 0
DisabledNoDetection_A 7014086 4998801 0 0
EnterDebounceSt_A 7014086 88 0 0
EnterDetectSt_A 7014086 63 0 0
EnterStableSt_A 7014086 58 0 0
PulseIsPulse_A 7014086 58 0 0
StayInStableSt 7014086 34538 0 0
gen_high_level_sva.HighLevelEvent_A 7014086 6367248 0 0
gen_sticky_sva.StableStDropOut_A 7014086 547304 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 150 0 0
T5 689 2 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 2 0 0
T21 0 2 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 2 0 0
T54 0 4 0 0
T55 0 2 0 0
T56 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 2 0 0
T96 0 2 0 0
T97 0 3 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 73605 0 0
T5 689 29 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 39 0 0
T21 0 51 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 50 0 0
T54 0 164 0 0
T55 0 78 0 0
T56 0 49 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 42 0 0
T96 0 40 0 0
T97 0 146 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6364700 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 5 0 0
T97 735 1 0 0
T125 648 0 0 0
T127 0 2 0 0
T128 0 1 0 0
T162 1182 0 0 0
T172 0 1 0 0
T173 502 0 0 0
T174 45552 0 0 0
T175 3027 0 0 0
T176 450 0 0 0
T177 427 0 0 0
T178 38567 0 0 0
T179 497 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 34596 0 0
T5 689 58 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 240 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 43 0 0
T54 0 1013 0 0
T55 0 277 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 3 0 0
T96 0 22 0 0
T100 0 164 0 0
T162 0 401 0 0
T163 0 246 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 58 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 4996405 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 4998801 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 88 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T21 0 2 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 2 0 0
T55 0 1 0 0
T56 0 2 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 63 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 58 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 58 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 1 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 34538 0 0
T5 689 57 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 239 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 42 0 0
T54 0 1011 0 0
T55 0 276 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 2 0 0
T96 0 21 0 0
T100 0 163 0 0
T162 0 399 0 0
T163 0 245 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6367248 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 547304 0 0
T5 689 152 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 304 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 47 0 0
T54 0 308 0 0
T55 0 188 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 144 0 0
T96 0 68 0 0
T100 0 54 0 0
T162 0 114 0 0
T163 0 214 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00

59 end else begin : gen_trigger_active_high 60 1/1 assign trigger_active = (trigger_i == 1'b1); Tests: T12 T13 T14  61 end 62 63 // In case of edge events, we also need to detect the transition. 64 logic trigger_event; 65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge 66 // This flop is always active, no matter the enable state. 67 logic trigger_active_q; 68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg 69 if (!rst_ni) begin 70 trigger_active_q <= 1'b0; 71 end else begin 72 trigger_active_q <= trigger_active; 73 end 74 end 75 76 assign trigger_event = trigger_active & ~trigger_active_q; 77 // In case of level events, the event is equal to the level being active. 78 end else begin : gen_trigger_event_level 79 1/1 assign trigger_event = trigger_active; Tests: T12 T13 T14  80 end 81 82 ///////////////// 83 // Timer Logic // 84 ///////////////// 85 86 // Take the maximum width of both timer values. 87 localparam int unsigned TimerWidth = 88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth; 89 90 logic cnt_en, cnt_clr; 91 logic [TimerWidth-1:0] cnt_d, cnt_q; 92 1/1 assign cnt_d = (cnt_clr) ? '0 : Tests: T5 T9 T21  93 (cnt_en) ? cnt_q + 1'b1 : 94 cnt_q; 95 96 97 logic cnt_done, thresh_sel; 98 logic [TimerWidth-1:0] thresh; 99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : Tests: T12 T5 T9  100 TimerWidth'(cfg_debounce_timer_i); 101 1/1 assign cnt_done = (cnt_q >= thresh); Tests: T12 T5 T9  102 103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg 104 1/1 if (!rst_ni) begin Tests: T1 T2 T4  105 1/1 cnt_q <= '0; Tests: T1 T2 T4  106 end else begin 107 1/1 cnt_q <= cnt_d; Tests: T1 T2 T4  108 end 109 end 110 111 ///////// 112 // FSM // 113 ///////// 114 115 typedef enum logic [1:0] { 116 IdleSt, 117 DebounceSt, 118 DetectSt, 119 StableSt 120 } state_t; 121 122 state_t state_d, state_q; 123 124 always_comb begin : p_fsm 125 1/1 state_d = state_q; Tests: T12 T13 T14  126 127 // Counter controls (clear has priority). 128 1/1 cnt_clr = 1'b0; Tests: T12 T13 T14  129 1/1 cnt_en = 1'b0; Tests: T12 T13 T14  130 131 // Detected outputs 132 1/1 event_detected_o = 1'b0; Tests: T12 T13 T14  133 1/1 event_detected_pulse_o = 1'b0; Tests: T12 T13 T14  134 135 // Threshold select 136 // 0: debounce 137 // 1: detect 138 1/1 thresh_sel = 1'b0; Tests: T12 T13 T14  139 140 1/1 unique case (state_q) Tests: T12 T13 T14  141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 1/1 if (trigger_event && cfg_enable_i) begin Tests: T12 T13 T14  148 1/1 state_d = DebounceSt; Tests: T5 T9 T21  149 1/1 cnt_en = 1'b1; Tests: T5 T9 T21  150 end MISSING_ELSE 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 1/1 cnt_en = 1'b1; Tests: T5 T9 T21  161 // Unconditionally go back to idle if the detector is disabled. 162 1/1 if (!cfg_enable_i) begin Tests: T5 T9 T21  163 1/1 state_d = IdleSt; Tests: T21 T56  164 1/1 cnt_clr = 1'b1; Tests: T21 T56  165 1/1 end else if (cnt_done) begin Tests: T5 T9 T21  166 1/1 cnt_clr = 1'b1; Tests: T5 T9 T39  167 1/1 if (trigger_active) begin Tests: T5 T9 T39  168 1/1 state_d = DetectSt; Tests: T5 T70 T54  169 end else begin 170 1/1 state_d = IdleSt; Tests: T9 T39 T116  171 end 172 end MISSING_ELSE 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 1/1 thresh_sel = 1'b1; Tests: T5 T70 T54  182 1/1 cnt_en = 1'b1; Tests: T5 T70 T54  183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 1/1 if (!cfg_enable_i || !trigger_active) begin Tests: T5 T70 T54  186 1/1 state_d = IdleSt; Tests: T117 T118 T119  187 1/1 cnt_clr = 1'b1; Tests: T117 T118 T119  188 // If the trigger is active, count up. 189 end else begin 190 1/1 if (cnt_done) begin Tests: T5 T70 T54  191 1/1 state_d = StableSt; Tests: T5 T70 T54  192 1/1 cnt_clr = 1'b1; Tests: T5 T70 T54  193 1/1 event_detected_o = 1'b1; Tests: T5 T70 T54  194 1/1 event_detected_pulse_o = 1'b1; Tests: T5 T70 T54  195 end ==> MISSING_ELSE 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin Tests: T5 T70 T54  206 1/1 state_d = IdleSt; Tests: T5 T70 T54  207 // Otherwise keep the event detected output signal high. 208 end else begin 209 1/1 event_detected_o = 1'b1; Tests: T5 T70 T54  210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; Exclude Annotation: VC_COV_UNR 215 endcase // state_q 216 end 217 218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg 219 1/1 if (!rst_ni) begin Tests: T1 T2 T4  220 1/1 state_q <= IdleSt; Tests: T1 T2 T4  221 end else begin 222 1/1 state_q <= state_d; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
TotalCoveredPercent
Conditions151493.33
Logical151493.33
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT12,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T9,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT5,T9,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT5,T70,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT5,T9,T21
10CoveredT12,T13,T14
11CoveredT5,T9,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT5,T70,T54
01CoveredT117,T118,T119
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT5,T70,T54
01Unreachable
10CoveredT5,T70,T54

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T5,T9,T21
DetectSt 168 Covered T5,T70,T54
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T5,T70,T54


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T5,T70,T54
DebounceSt->IdleSt 163 Covered T9,T21,T39
DetectSt->IdleSt 186 Covered T117,T118,T119
DetectSt->StableSt 191 Covered T5,T70,T54
IdleSt->DebounceSt 148 Covered T5,T9,T21
StableSt->IdleSt 206 Covered T5,T70,T54



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
Branches 18 18 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00


92 assign cnt_d = (cnt_clr) ? '0 : -1- ==> 93 (cnt_en) ? cnt_q + 1'b1 : -2- ==> ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T5,T9,T21
0 1 Covered T5,T9,T21
0 0 Excluded T1,T2,T4 VC_COV_UNR


99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T5,T70,T54
0 Covered T1,T2,T4


104 if (!rst_ni) begin -1- 105 cnt_q <= '0; ==> 106 end else begin 107 cnt_q <= cnt_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


140 unique case (state_q) -1- 141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 if (trigger_event && cfg_enable_i) begin -2- 148 state_d = DebounceSt; ==> 149 cnt_en = 1'b1; 150 end MISSING_ELSE ==> 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 cnt_en = 1'b1; 161 // Unconditionally go back to idle if the detector is disabled. 162 if (!cfg_enable_i) begin -3- 163 state_d = IdleSt; ==> 164 cnt_clr = 1'b1; 165 end else if (cnt_done) begin -4- 166 cnt_clr = 1'b1; 167 if (trigger_active) begin -5- 168 state_d = DetectSt; ==> 169 end else begin 170 state_d = IdleSt; ==> 171 end 172 end MISSING_ELSE ==> 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 thresh_sel = 1'b1; 182 cnt_en = 1'b1; 183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 if (!cfg_enable_i || !trigger_active) begin -6- 186 state_d = IdleSt; ==> 187 cnt_clr = 1'b1; 188 // If the trigger is active, count up. 189 end else begin 190 if (cnt_done) begin -7- 191 state_d = StableSt; ==> 192 cnt_clr = 1'b1; 193 event_detected_o = 1'b1; 194 event_detected_pulse_o = 1'b1; 195 end MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin -8- 206 state_d = IdleSt; ==> 207 // Otherwise keep the event detected output signal high. 208 end else begin 209 event_detected_o = 1'b1; ==> 210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; ==> (Excluded) Exclude Annotation: VC_COV_UNR

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T5,T9,T21
IdleSt 0 - - - - - - Covered T12,T13,T14
DebounceSt - 1 - - - - - Covered T21,T56
DebounceSt - 0 1 1 - - - Covered T5,T70,T54
DebounceSt - 0 1 0 - - - Covered T9,T39,T116
DebounceSt - 0 0 - - - - Covered T5,T9,T21
DetectSt - - - - 1 - - Covered T117,T118,T119
DetectSt - - - - 0 1 - Covered T5,T70,T54
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T5,T70,T54
StableSt - - - - - - 0 Covered T5,T70,T54
default - - - - - - - Excluded VC_COV_UNR


219 if (!rst_ni) begin -1- 220 state_q <= IdleSt; ==> 221 end else begin 222 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7014086 158 0 0
CntIncr_A 7014086 127939 0 0
CntNoWrap_A 7014086 6364692 0 0
DetectStDropOut_A 7014086 8 0 0
DetectedOut_A 7014086 352297 0 0
DetectedPulseOut_A 7014086 51 0 0
DisabledIdleSt_A 7014086 4996405 0 0
DisabledNoDetection_A 7014086 4998801 0 0
EnterDebounceSt_A 7014086 100 0 0
EnterDetectSt_A 7014086 59 0 0
EnterStableSt_A 7014086 51 0 0
PulseIsPulse_A 7014086 51 0 0
StayInStableSt 7014086 352246 0 0
gen_high_event_sva.HighLevelEvent_A 7014086 6367248 0 0
gen_high_level_sva.HighLevelEvent_A 7014086 6367248 0 0
gen_sticky_sva.StableStDropOut_A 7014086 790793 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 158 0 0
T5 689 2 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 4 0 0
T21 0 2 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 4 0 0
T55 0 2 0 0
T56 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 2 0 0
T96 0 2 0 0
T97 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 127939 0 0
T5 689 29 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 192 0 0
T21 0 52 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 34 0 0
T54 0 123 0 0
T55 0 23 0 0
T56 0 53 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 98 0 0
T96 0 63 0 0
T97 0 94 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6364692 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 8 0 0
T117 3366 1 0 0
T118 0 1 0 0
T119 0 2 0 0
T172 0 3 0 0
T180 0 1 0 0
T181 2408 0 0 0
T182 800 0 0 0
T183 522 0 0 0
T184 403 0 0 0
T185 9082 0 0 0
T186 425 0 0 0
T187 432 0 0 0
T188 493 0 0 0
T189 795 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 352297 0 0
T5 689 88 0 0
T6 7579 0 0 0
T8 627 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 789 0 0
T55 0 158 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 53 0 0
T96 0 41 0 0
T97 0 165 0 0
T100 0 161 0 0
T162 0 257 0 0
T163 0 199 0 0
T164 0 177 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 51 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0
T164 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 4996405 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 4998801 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 100 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T9 0 4 0 0
T21 0 2 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T39 0 1 0 0
T54 0 2 0 0
T55 0 1 0 0
T56 0 2 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 59 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0
T164 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 51 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0
T164 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 51 0 0
T5 689 1 0 0
T6 7579 0 0 0
T8 627 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 2 0 0
T55 0 1 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 1 0 0
T96 0 1 0 0
T97 0 1 0 0
T100 0 1 0 0
T162 0 2 0 0
T163 0 1 0 0
T164 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 352246 0 0
T5 689 87 0 0
T6 7579 0 0 0
T8 627 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 787 0 0
T55 0 157 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 52 0 0
T96 0 40 0 0
T97 0 164 0 0
T100 0 160 0 0
T162 0 255 0 0
T163 0 198 0 0
T164 0 176 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6367248 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6367248 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 790793 0 0
T5 689 137 0 0
T6 7579 0 0 0
T8 627 0 0 0
T26 501 0 0 0
T27 645 0 0 0
T29 456 0 0 0
T54 0 603 0 0
T55 0 370 0 0
T65 522 0 0 0
T66 406 0 0 0
T67 424 0 0 0
T68 818 0 0 0
T70 0 49 0 0
T96 0 43 0 0
T97 0 35 0 0
T100 0 60 0 0
T162 0 408 0 0
T163 0 232 0 0
T164 0 33 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00

59 end else begin : gen_trigger_active_high 60 1/1 assign trigger_active = (trigger_i == 1'b1); Tests: T1 T2 T4  61 end 62 63 // In case of edge events, we also need to detect the transition. 64 logic trigger_event; 65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge 66 // This flop is always active, no matter the enable state. 67 logic trigger_active_q; 68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg 69 1/1 if (!rst_ni) begin Tests: T1 T2 T4  70 1/1 trigger_active_q <= 1'b0; Tests: T1 T2 T4  71 end else begin 72 1/1 trigger_active_q <= trigger_active; Tests: T1 T2 T4  73 end 74 end 75 76 1/1 assign trigger_event = trigger_active & ~trigger_active_q; Tests: T1 T2 T4  77 // In case of level events, the event is equal to the level being active. 78 end else begin : gen_trigger_event_level 79 assign trigger_event = trigger_active; 80 end 81 82 ///////////////// 83 // Timer Logic // 84 ///////////////// 85 86 // Take the maximum width of both timer values. 87 localparam int unsigned TimerWidth = 88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth; 89 90 logic cnt_en, cnt_clr; 91 logic [TimerWidth-1:0] cnt_d, cnt_q; 92 1/1 assign cnt_d = (cnt_clr) ? '0 : Tests: T10 T51 T49  93 (cnt_en) ? cnt_q + 1'b1 : 94 cnt_q; 95 96 97 logic cnt_done, thresh_sel; 98 logic [TimerWidth-1:0] thresh; 99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : Tests: T1 T2 T3  100 TimerWidth'(cfg_debounce_timer_i); 101 1/1 assign cnt_done = (cnt_q >= thresh); Tests: T1 T2 T3  102 103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg 104 1/1 if (!rst_ni) begin Tests: T1 T2 T4  105 1/1 cnt_q <= '0; Tests: T1 T2 T4  106 end else begin 107 1/1 cnt_q <= cnt_d; Tests: T1 T2 T4  108 end 109 end 110 111 ///////// 112 // FSM // 113 ///////// 114 115 typedef enum logic [1:0] { 116 IdleSt, 117 DebounceSt, 118 DetectSt, 119 StableSt 120 } state_t; 121 122 state_t state_d, state_q; 123 124 always_comb begin : p_fsm 125 1/1 state_d = state_q; Tests: T1 T2 T4  126 127 // Counter controls (clear has priority). 128 1/1 cnt_clr = 1'b0; Tests: T1 T2 T4  129 1/1 cnt_en = 1'b0; Tests: T1 T2 T4  130 131 // Detected outputs 132 1/1 event_detected_o = 1'b0; Tests: T1 T2 T4  133 1/1 event_detected_pulse_o = 1'b0; Tests: T1 T2 T4  134 135 // Threshold select 136 // 0: debounce 137 // 1: detect 138 1/1 thresh_sel = 1'b0; Tests: T1 T2 T4  139 140 1/1 unique case (state_q) Tests: T1 T2 T4  141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 1/1 if (trigger_event && cfg_enable_i) begin Tests: T1 T2 T4  148 1/1 state_d = DebounceSt; Tests: T10 T51 T49  149 1/1 cnt_en = 1'b1; Tests: T10 T51 T49  150 end MISSING_ELSE 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 1/1 cnt_en = 1'b1; Tests: T10 T51 T49  161 // Unconditionally go back to idle if the detector is disabled. 162 1/1 if (!cfg_enable_i) begin Tests: T10 T51 T49  163 0/1 ==> state_d = IdleSt; 164 0/1 ==> cnt_clr = 1'b1; 165 1/1 end else if (cnt_done) begin Tests: T10 T51 T49  166 1/1 cnt_clr = 1'b1; Tests: T10 T51 T49  167 1/1 if (trigger_active) begin Tests: T10 T51 T49  168 1/1 state_d = DetectSt; Tests: T10 T51 T49  169 end else begin 170 1/1 state_d = IdleSt; Tests: T190  171 end 172 end MISSING_ELSE 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 1/1 thresh_sel = 1'b1; Tests: T10 T51 T49  182 1/1 cnt_en = 1'b1; Tests: T10 T51 T49  183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 1/1 if (!cfg_enable_i || !trigger_active) begin Tests: T10 T51 T49  186 1/1 state_d = IdleSt; Tests: T56 T191 T137  187 1/1 cnt_clr = 1'b1; Tests: T56 T191 T137  188 // If the trigger is active, count up. 189 end else begin 190 1/1 if (cnt_done) begin Tests: T10 T51 T49  191 1/1 state_d = StableSt; Tests: T10 T51 T49  192 1/1 cnt_clr = 1'b1; Tests: T10 T51 T49  193 1/1 event_detected_o = 1'b1; Tests: T10 T51 T49  194 1/1 event_detected_pulse_o = 1'b1; Tests: T10 T51 T49  195 end ==> MISSING_ELSE 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin Tests: T10 T51 T49  206 1/1 state_d = IdleSt; Tests: T21 T192 T193  207 // Otherwise keep the event detected output signal high. 208 end else begin 209 1/1 event_detected_o = 1'b1; Tests: T10 T51 T49  210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; Exclude Annotation: VC_COV_UNR 215 endcase // state_q 216 end 217 218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg 219 1/1 if (!rst_ni) begin Tests: T1 T2 T4  220 1/1 state_q <= IdleSt; Tests: T1 T2 T4  221 end else begin 222 1/1 state_q <= state_d; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions2121100.00
Logical2121100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT10,T51,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT10,T51,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT10,T51,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T10,T51
10CoveredT1,T2,T4
11CoveredT10,T51,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT10,T51,T49
01CoveredT191,T137
10CoveredT56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT10,T51,T49
01CoveredT192,T193,T189
10CoveredT21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT10,T51,T49
1-CoveredT192,T193,T189

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T10,T51,T49
DetectSt 168 Covered T10,T51,T49
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T10,T51,T49


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T10,T51,T49
DebounceSt->IdleSt 163 Covered T131,T128,T190
DetectSt->IdleSt 186 Covered T56,T191,T137
DetectSt->StableSt 191 Covered T10,T51,T49
IdleSt->DebounceSt 148 Covered T10,T51,T49
StableSt->IdleSt 206 Covered T21,T100,T192



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00


92 assign cnt_d = (cnt_clr) ? '0 : -1- ==> 93 (cnt_en) ? cnt_q + 1'b1 : -2- ==> ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T10,T51,T49
0 1 Covered T10,T51,T49
0 0 Excluded T1,T2,T4 VC_COV_UNR


99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T51,T49
0 Covered T1,T2,T4


104 if (!rst_ni) begin -1- 105 cnt_q <= '0; ==> 106 end else begin 107 cnt_q <= cnt_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


140 unique case (state_q) -1- 141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 if (trigger_event && cfg_enable_i) begin -2- 148 state_d = DebounceSt; ==> 149 cnt_en = 1'b1; 150 end MISSING_ELSE ==> 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 cnt_en = 1'b1; 161 // Unconditionally go back to idle if the detector is disabled. 162 if (!cfg_enable_i) begin -3- 163 state_d = IdleSt; ==> 164 cnt_clr = 1'b1; 165 end else if (cnt_done) begin -4- 166 cnt_clr = 1'b1; 167 if (trigger_active) begin -5- 168 state_d = DetectSt; ==> 169 end else begin 170 state_d = IdleSt; ==> 171 end 172 end MISSING_ELSE ==> 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 thresh_sel = 1'b1; 182 cnt_en = 1'b1; 183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 if (!cfg_enable_i || !trigger_active) begin -6- 186 state_d = IdleSt; ==> 187 cnt_clr = 1'b1; 188 // If the trigger is active, count up. 189 end else begin 190 if (cnt_done) begin -7- 191 state_d = StableSt; ==> 192 cnt_clr = 1'b1; 193 event_detected_o = 1'b1; 194 event_detected_pulse_o = 1'b1; 195 end MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin -8- 206 state_d = IdleSt; ==> 207 // Otherwise keep the event detected output signal high. 208 end else begin 209 event_detected_o = 1'b1; ==> 210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; ==> (Excluded) Exclude Annotation: VC_COV_UNR

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T10,T51,T49
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T10,T51,T49
DebounceSt - 0 1 0 - - - Covered T190
DebounceSt - 0 0 - - - - Covered T10,T51,T49
DetectSt - - - - 1 - - Covered T56,T191,T137
DetectSt - - - - 0 1 - Covered T10,T51,T49
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T21,T192,T193
StableSt - - - - - - 0 Covered T10,T51,T49
default - - - - - - - Excluded VC_COV_UNR


219 if (!rst_ni) begin -1- 220 state_q <= IdleSt; ==> 221 end else begin 222 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


69 if (!rst_ni) begin -1- 70 trigger_active_q <= 1'b0; ==> 71 end else begin 72 trigger_active_q <= trigger_active; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7014086 89 0 0
CntIncr_A 7014086 57641 0 0
CntNoWrap_A 7014086 6364761 0 0
DetectStDropOut_A 7014086 2 0 0
DetectedOut_A 7014086 14284 0 0
DetectedPulseOut_A 7014086 41 0 0
DisabledIdleSt_A 7014086 6173131 0 0
DisabledNoDetection_A 7014086 6175467 0 0
EnterDebounceSt_A 7014086 47 0 0
EnterDetectSt_A 7014086 44 0 0
EnterStableSt_A 7014086 41 0 0
PulseIsPulse_A 7014086 41 0 0
StayInStableSt 7014086 14224 0 0
gen_high_level_sva.HighLevelEvent_A 7014086 6367248 0 0
gen_not_sticky_sva.StableStDropOut_A 7014086 21 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 89 0 0
T10 558 2 0 0
T11 30017 0 0 0
T21 0 2 0 0
T49 0 2 0 0
T51 1595 2 0 0
T56 0 2 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 2 0 0
T101 409 0 0 0
T189 0 4 0 0
T192 0 2 0 0
T193 0 2 0 0
T194 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 57641 0 0
T10 558 21 0 0
T11 30017 0 0 0
T21 0 32 0 0
T49 0 39 0 0
T51 1595 88 0 0
T56 0 39 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 54 0 0
T101 409 0 0 0
T131 0 37 0 0
T192 0 89 0 0
T193 0 68 0 0
T194 0 16 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6364761 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 2 0 0
T127 13755 0 0 0
T137 0 1 0 0
T191 9711 1 0 0
T195 403 0 0 0
T196 493 0 0 0
T197 422 0 0 0
T198 447 0 0 0
T199 15095 0 0 0
T200 525 0 0 0
T201 741 0 0 0
T202 431 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 14284 0 0
T10 558 40 0 0
T11 30017 0 0 0
T21 0 7 0 0
T49 0 43 0 0
T51 1595 60 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 37 0 0
T101 409 0 0 0
T189 0 8 0 0
T192 0 43 0 0
T193 0 53 0 0
T194 0 38 0 0
T203 0 41 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 41 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 1 0 0
T101 409 0 0 0
T189 0 2 0 0
T192 0 1 0 0
T193 0 1 0 0
T194 0 1 0 0
T203 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6173131 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 4 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6175467 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 4 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 47 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T49 0 1 0 0
T51 1595 1 0 0
T56 0 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 1 0 0
T101 409 0 0 0
T131 0 1 0 0
T192 0 1 0 0
T193 0 1 0 0
T194 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 44 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T49 0 1 0 0
T51 1595 1 0 0
T56 0 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 1 0 0
T101 409 0 0 0
T189 0 2 0 0
T192 0 1 0 0
T193 0 1 0 0
T194 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 41 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 1 0 0
T101 409 0 0 0
T189 0 2 0 0
T192 0 1 0 0
T193 0 1 0 0
T194 0 1 0 0
T203 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 41 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 1 0 0
T101 409 0 0 0
T189 0 2 0 0
T192 0 1 0 0
T193 0 1 0 0
T194 0 1 0 0
T203 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 14224 0 0
T10 558 38 0 0
T11 30017 0 0 0
T21 0 6 0 0
T49 0 41 0 0
T51 1595 58 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 35 0 0
T101 409 0 0 0
T189 0 6 0 0
T192 0 42 0 0
T193 0 52 0 0
T194 0 36 0 0
T203 0 39 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6367248 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 21 0 0
T44 6528 0 0 0
T124 17655 0 0 0
T171 0 2 0 0
T189 0 2 0 0
T192 1122 1 0 0
T193 0 1 0 0
T204 0 1 0 0
T205 0 1 0 0
T206 0 1 0 0
T207 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T210 527 0 0 0
T211 686 0 0 0
T212 421 0 0 0
T213 421 0 0 0
T214 724 0 0 0
T215 901 0 0 0
T216 407 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00

57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low 58 1/1 assign trigger_active = (trigger_i == 1'b0); Tests: T1 T2 T4  59 end else begin : gen_trigger_active_high 60 assign trigger_active = (trigger_i == 1'b1); 61 end 62 63 // In case of edge events, we also need to detect the transition. 64 logic trigger_event; 65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge 66 // This flop is always active, no matter the enable state. 67 logic trigger_active_q; 68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg 69 1/1 if (!rst_ni) begin Tests: T1 T2 T4  70 1/1 trigger_active_q <= 1'b0; Tests: T1 T2 T4  71 end else begin 72 1/1 trigger_active_q <= trigger_active; Tests: T1 T2 T4  73 end 74 end 75 76 1/1 assign trigger_event = trigger_active & ~trigger_active_q; Tests: T1 T2 T4  77 // In case of level events, the event is equal to the level being active. 78 end else begin : gen_trigger_event_level 79 assign trigger_event = trigger_active; 80 end 81 82 ///////////////// 83 // Timer Logic // 84 ///////////////// 85 86 // Take the maximum width of both timer values. 87 localparam int unsigned TimerWidth = 88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth; 89 90 logic cnt_en, cnt_clr; 91 logic [TimerWidth-1:0] cnt_d, cnt_q; 92 1/1 assign cnt_d = (cnt_clr) ? '0 : Tests: T10 T51 T49  93 (cnt_en) ? cnt_q + 1'b1 : 94 cnt_q; 95 96 97 logic cnt_done, thresh_sel; 98 logic [TimerWidth-1:0] thresh; 99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : Tests: T1 T2 T3  100 TimerWidth'(cfg_debounce_timer_i); 101 1/1 assign cnt_done = (cnt_q >= thresh); Tests: T1 T2 T3  102 103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg 104 1/1 if (!rst_ni) begin Tests: T1 T2 T4  105 1/1 cnt_q <= '0; Tests: T1 T2 T4  106 end else begin 107 1/1 cnt_q <= cnt_d; Tests: T1 T2 T4  108 end 109 end 110 111 ///////// 112 // FSM // 113 ///////// 114 115 typedef enum logic [1:0] { 116 IdleSt, 117 DebounceSt, 118 DetectSt, 119 StableSt 120 } state_t; 121 122 state_t state_d, state_q; 123 124 always_comb begin : p_fsm 125 1/1 state_d = state_q; Tests: T1 T2 T4  126 127 // Counter controls (clear has priority). 128 1/1 cnt_clr = 1'b0; Tests: T1 T2 T4  129 1/1 cnt_en = 1'b0; Tests: T1 T2 T4  130 131 // Detected outputs 132 1/1 event_detected_o = 1'b0; Tests: T1 T2 T4  133 1/1 event_detected_pulse_o = 1'b0; Tests: T1 T2 T4  134 135 // Threshold select 136 // 0: debounce 137 // 1: detect 138 1/1 thresh_sel = 1'b0; Tests: T1 T2 T4  139 140 1/1 unique case (state_q) Tests: T1 T2 T4  141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 1/1 if (trigger_event && cfg_enable_i) begin Tests: T1 T2 T4  148 1/1 state_d = DebounceSt; Tests: T10 T51 T49  149 1/1 cnt_en = 1'b1; Tests: T10 T51 T49  150 end MISSING_ELSE 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 1/1 cnt_en = 1'b1; Tests: T10 T51 T49  161 // Unconditionally go back to idle if the detector is disabled. 162 1/1 if (!cfg_enable_i) begin Tests: T10 T51 T49  163 1/1 state_d = IdleSt; Tests: T56  164 1/1 cnt_clr = 1'b1; Tests: T56  165 1/1 end else if (cnt_done) begin Tests: T10 T51 T49  166 1/1 cnt_clr = 1'b1; Tests: T10 T51 T49  167 1/1 if (trigger_active) begin Tests: T10 T51 T49  168 1/1 state_d = DetectSt; Tests: T10 T51 T49  169 end else begin 170 1/1 state_d = IdleSt; Tests: T125 T100 T127  171 end 172 end MISSING_ELSE 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 1/1 thresh_sel = 1'b1; Tests: T10 T51 T49  182 1/1 cnt_en = 1'b1; Tests: T10 T51 T49  183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 1/1 if (!cfg_enable_i || !trigger_active) begin Tests: T10 T51 T49  186 1/1 state_d = IdleSt; Tests: T117 T171  187 1/1 cnt_clr = 1'b1; Tests: T117 T171  188 // If the trigger is active, count up. 189 end else begin 190 1/1 if (cnt_done) begin Tests: T10 T51 T49  191 1/1 state_d = StableSt; Tests: T10 T51 T49  192 1/1 cnt_clr = 1'b1; Tests: T10 T51 T49  193 1/1 event_detected_o = 1'b1; Tests: T10 T51 T49  194 1/1 event_detected_pulse_o = 1'b1; Tests: T10 T51 T49  195 end ==> MISSING_ELSE 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin Tests: T10 T51 T49  206 1/1 state_d = IdleSt; Tests: T10 T51 T49  207 // Otherwise keep the event detected output signal high. 208 end else begin 209 1/1 event_detected_o = 1'b1; Tests: T10 T51 T49  210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; Exclude Annotation: VC_COV_UNR 215 endcase // state_q 216 end 217 218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg 219 1/1 if (!rst_ni) begin Tests: T1 T2 T4  220 1/1 state_q <= IdleSt; Tests: T1 T2 T4  221 end else begin 222 1/1 state_q <= state_d; Tests: T1 T2 T4 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT10,T51,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT10,T51,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT10,T51,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT10,T51,T49
10CoveredT13,T14,T15
11CoveredT10,T51,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT10,T51,T49
01CoveredT117,T171
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT10,T51,T49
01CoveredT10,T51,T49
10CoveredT21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT10,T51,T49
1-CoveredT10,T51,T49

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
DebounceSt 148 Covered T10,T51,T49
DetectSt 168 Covered T10,T51,T49
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T10,T51,T49


transitions   Line No.   Covered   Tests   
DebounceSt->DetectSt 168 Covered T10,T51,T49
DebounceSt->IdleSt 163 Covered T56,T125,T100
DetectSt->IdleSt 186 Covered T117,T171
DetectSt->StableSt 191 Covered T10,T51,T49
IdleSt->DebounceSt 148 Covered T10,T51,T49
StableSt->IdleSt 206 Covered T10,T51,T49



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00


92 assign cnt_d = (cnt_clr) ? '0 : -1- ==> 93 (cnt_en) ? cnt_q + 1'b1 : -2- ==> ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T10,T51,T49
0 1 Covered T10,T51,T49
0 0 Excluded T1,T2,T4 VC_COV_UNR


99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T10,T51,T49
0 Covered T1,T2,T4


104 if (!rst_ni) begin -1- 105 cnt_q <= '0; ==> 106 end else begin 107 cnt_q <= cnt_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


140 unique case (state_q) -1- 141 //////////////////////////////////////////// 142 // We are waiting for the event to occur. 143 // This can be either a specific level or edge, 144 // depending on the configuration. 145 IdleSt: begin 146 // Stay here if the detector is disabled. 147 if (trigger_event && cfg_enable_i) begin -2- 148 state_d = DebounceSt; ==> 149 cnt_en = 1'b1; 150 end MISSING_ELSE ==> 151 end 152 //////////////////////////////////////////// 153 // If an event has occurred, we back off for 154 // the amount of debounce cycles configured. 155 // Once the timer has expired, we sample the 156 // signal again and check whether it has the 157 // correct level. If so, we move on to the 158 // detection stage, otherwise we fall back. 159 DebounceSt: begin 160 cnt_en = 1'b1; 161 // Unconditionally go back to idle if the detector is disabled. 162 if (!cfg_enable_i) begin -3- 163 state_d = IdleSt; ==> 164 cnt_clr = 1'b1; 165 end else if (cnt_done) begin -4- 166 cnt_clr = 1'b1; 167 if (trigger_active) begin -5- 168 state_d = DetectSt; ==> 169 end else begin 170 state_d = IdleSt; ==> 171 end 172 end MISSING_ELSE ==> 173 end 174 //////////////////////////////////////////// 175 // Once the debounce period has passed, we 176 // check whether the signal remains stable 177 // throughout the entire detection period. 178 // If it is not stable at any cycle, we fall 179 // back to idle. 180 DetectSt: begin 181 thresh_sel = 1'b1; 182 cnt_en = 1'b1; 183 // Go back to idle if either the trigger level is not active anymore, or if the 184 // detector is disabled. 185 if (!cfg_enable_i || !trigger_active) begin -6- 186 state_d = IdleSt; ==> 187 cnt_clr = 1'b1; 188 // If the trigger is active, count up. 189 end else begin 190 if (cnt_done) begin -7- 191 state_d = StableSt; ==> 192 cnt_clr = 1'b1; 193 event_detected_o = 1'b1; 194 event_detected_pulse_o = 1'b1; 195 end MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 196 end 197 end 198 //////////////////////////////////////////// 199 // At this point we have detected the event 200 // and monitor whether the signal remains stable. 201 StableSt: begin 202 // Go back to idle if either the trigger level is not active anymore, or if the detector is 203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order 204 // to go back to the idle state. 205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin -8- 206 state_d = IdleSt; ==> 207 // Otherwise keep the event detected output signal high. 208 end else begin 209 event_detected_o = 1'b1; ==> 210 end 211 end 212 //////////////////////////////////////////// 213 // This is a full case statement 214 default: ; ==> (Excluded) Exclude Annotation: VC_COV_UNR

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T10,T51,T49
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T56
DebounceSt - 0 1 1 - - - Covered T10,T51,T49
DebounceSt - 0 1 0 - - - Covered T125,T100,T127
DebounceSt - 0 0 - - - - Covered T10,T51,T49
DetectSt - - - - 1 - - Covered T117,T171
DetectSt - - - - 0 1 - Covered T10,T51,T49
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T10,T51,T49
StableSt - - - - - - 0 Covered T10,T51,T49
default - - - - - - - Excluded VC_COV_UNR


219 if (!rst_ni) begin -1- 220 state_q <= IdleSt; ==> 221 end else begin 222 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


69 if (!rst_ni) begin -1- 70 trigger_active_q <= 1'b0; ==> 71 end else begin 72 trigger_active_q <= trigger_active; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntClr_A 7014086 139 0 0
CntIncr_A 7014086 33259 0 0
CntNoWrap_A 7014086 6364711 0 0
DetectStDropOut_A 7014086 2 0 0
DetectedOut_A 7014086 24230 0 0
DetectedPulseOut_A 7014086 64 0 0
DisabledIdleSt_A 7014086 6277861 0 0
DisabledNoDetection_A 7014086 6280199 0 0
EnterDebounceSt_A 7014086 75 0 0
EnterDetectSt_A 7014086 66 0 0
EnterStableSt_A 7014086 64 0 0
PulseIsPulse_A 7014086 64 0 0
StayInStableSt 7014086 24141 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7014086 2658 0 0
gen_low_level_sva.LowLevelEvent_A 7014086 6367248 0 0
gen_not_sticky_sva.StableStDropOut_A 7014086 38 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 139 0 0
T10 558 2 0 0
T11 30017 0 0 0
T21 0 2 0 0
T46 0 4 0 0
T49 0 2 0 0
T51 1595 2 0 0
T56 0 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 1 0 0
T101 409 0 0 0
T125 0 5 0 0
T131 0 2 0 0
T217 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 33259 0 0
T10 558 21 0 0
T11 30017 0 0 0
T21 0 32 0 0
T46 0 168 0 0
T49 0 39 0 0
T51 1595 88 0 0
T56 0 39 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 54 0 0
T101 409 0 0 0
T125 0 54 0 0
T131 0 44 0 0
T217 0 49 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6364711 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 2 0 0
T117 3366 1 0 0
T171 0 1 0 0
T181 2408 0 0 0
T182 800 0 0 0
T183 522 0 0 0
T184 403 0 0 0
T185 9082 0 0 0
T186 425 0 0 0
T187 432 0 0 0
T188 493 0 0 0
T189 795 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 24230 0 0
T10 558 66 0 0
T11 30017 0 0 0
T21 0 7 0 0
T46 0 163 0 0
T49 0 102 0 0
T51 1595 38 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T101 409 0 0 0
T125 0 88 0 0
T129 0 12 0 0
T131 0 7 0 0
T217 0 214 0 0
T218 0 64 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 64 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T46 0 2 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T101 409 0 0 0
T125 0 2 0 0
T129 0 1 0 0
T131 0 1 0 0
T217 0 1 0 0
T218 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6277861 0 0
T1 509 108 0 0
T2 486 85 0 0
T3 481 80 0 0
T4 666 265 0 0
T12 747 346 0 0
T13 523 122 0 0
T14 412 11 0 0
T15 423 22 0 0
T16 1038 637 0 0
T17 426 25 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6280199 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 75 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T46 0 2 0 0
T49 0 1 0 0
T51 1595 1 0 0
T56 0 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T100 0 1 0 0
T101 409 0 0 0
T125 0 3 0 0
T131 0 1 0 0
T217 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 66 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T46 0 2 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T101 409 0 0 0
T125 0 2 0 0
T129 0 1 0 0
T131 0 1 0 0
T217 0 1 0 0
T218 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 64 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T46 0 2 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T101 409 0 0 0
T125 0 2 0 0
T129 0 1 0 0
T131 0 1 0 0
T217 0 1 0 0
T218 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 64 0 0
T10 558 1 0 0
T11 30017 0 0 0
T21 0 1 0 0
T46 0 2 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T101 409 0 0 0
T125 0 2 0 0
T129 0 1 0 0
T131 0 1 0 0
T217 0 1 0 0
T218 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 24141 0 0
T10 558 65 0 0
T11 30017 0 0 0
T21 0 6 0 0
T46 0 160 0 0
T49 0 101 0 0
T51 1595 37 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T101 409 0 0 0
T125 0 85 0 0
T129 0 11 0 0
T131 0 6 0 0
T217 0 212 0 0
T218 0 62 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 2658 0 0
T3 481 1 0 0
T13 523 5 0 0
T14 412 1 0 0
T15 423 3 0 0
T16 1038 0 0 0
T17 426 3 0 0
T22 491 3 0 0
T23 497 4 0 0
T25 0 6 0 0
T26 0 5 0 0
T31 448 0 0 0
T65 0 6 0 0
T74 403 0 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 6367248 0 0
T1 509 109 0 0
T2 486 86 0 0
T3 481 81 0 0
T4 666 266 0 0
T12 747 347 0 0
T13 523 123 0 0
T14 412 12 0 0
T15 423 23 0 0
T16 1038 638 0 0
T17 426 26 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7014086 38 0 0
T10 558 1 0 0
T11 30017 0 0 0
T46 0 1 0 0
T49 0 1 0 0
T51 1595 1 0 0
T58 692 0 0 0
T59 509 0 0 0
T84 507 0 0 0
T93 425 0 0 0
T94 8443 0 0 0
T95 448 0 0 0
T101 409 0 0 0
T125 0 1 0 0
T129 0 1 0 0
T131 0 1 0 0
T189 0 2 0 0
T192 0 1 0 0
T193 0 1 0 0