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Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.67 95.83 87.50 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.67 95.83 87.50 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sysrst_ctrl_autoblock


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.63 95.83 92.31 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.63 95.83 92.31 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.42 95.83 84.62 83.33 95.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.42 95.83 84.62 83.33 95.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.46 95.56 92.31 100.00 94.44 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.46 95.56 92.31 100.00 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL484695.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT23,T27,T28
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT23,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT23,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT23,T27,T28
10CoveredT6,T21,T34
11CoveredT23,T27,T28

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT23,T27,T28
01CoveredT37
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT23,T27,T28
01CoveredT23,T27,T28
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT23,T27,T28
1-CoveredT23,T27,T28

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Covered T10
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T23,T27,T28
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T23,T27,T28
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T23,T27,T28
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T23,T27,T28
DebounceSt - 0 1 0 - - - Covered T56,T84,T85
DebounceSt - 0 0 - - - - Covered T23,T27,T28
DetectSt - - - - 1 - - Covered T37
DetectSt - - - - 0 1 - Covered T23,T27,T28
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T23,T27,T28
StableSt - - - - - - 0 Covered T23,T27,T28
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3328765 0 0
CntIncr_A 3964510 149052 0 0
CntNoWrap_A 3964510 149052 0 0
DetectStDropOut_A 3964510 1 0 0
DetectedOut_A 3964510 642 0 0
DetectedPulseOut_A 3964510 91 0 0
DisabledIdleSt_A 3964510 3324151 0 0
DisabledNoDetection_A 3964510 3325382 0 0
EnterDebounceSt_A 3964510 108 0 0
EnterDetectSt_A 3964510 92 0 0
EnterStableSt_A 3964510 91 0 0
PulseIsPulse_A 3964510 91 0 0
StayInStableSt 3964510 551 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 3818 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 91 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3328765 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 149052 0 0
T17 10031 690 0 0
T23 737 85 0 0
T27 709 162 0 0
T28 299733 139 0 0
T55 1995 52 0 0
T56 659 119 0 0
T57 3273 108 0 0
T58 729 61 0 0
T59 797 96 0 0
T60 609 90 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 149052 0 0
T17 10031 690 0 0
T23 737 85 0 0
T27 709 162 0 0
T28 299733 139 0 0
T55 1995 52 0 0
T56 659 119 0 0
T57 3273 108 0 0
T58 729 61 0 0
T59 797 96 0 0
T60 609 90 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1 0 0
T37 36716 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 642 0 0
T23 737 12 0 0
T27 709 22 0 0
T28 299733 22 0 0
T55 1995 6 0 0
T56 659 8 0 0
T57 3273 14 0 0
T58 729 6 0 0
T59 797 12 0 0
T60 609 9 0 0
T69 23429 2 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 91 0 0
T23 737 1 0 0
T27 709 2 0 0
T28 299733 2 0 0
T55 1995 1 0 0
T56 659 1 0 0
T57 3273 2 0 0
T58 729 1 0 0
T59 797 1 0 0
T60 609 2 0 0
T69 23429 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3324151 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3325382 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 108 0 0
T17 10031 1 0 0
T23 737 1 0 0
T27 709 2 0 0
T28 299733 2 0 0
T55 1995 1 0 0
T56 659 2 0 0
T57 3273 2 0 0
T58 729 1 0 0
T59 797 1 0 0
T60 609 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 92 0 0
T23 737 1 0 0
T27 709 2 0 0
T28 299733 2 0 0
T55 1995 1 0 0
T56 659 1 0 0
T57 3273 2 0 0
T58 729 1 0 0
T59 797 1 0 0
T60 609 2 0 0
T69 23429 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 91 0 0
T23 737 1 0 0
T27 709 2 0 0
T28 299733 2 0 0
T55 1995 1 0 0
T56 659 1 0 0
T57 3273 2 0 0
T58 729 1 0 0
T59 797 1 0 0
T60 609 2 0 0
T69 23429 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 91 0 0
T23 737 1 0 0
T27 709 2 0 0
T28 299733 2 0 0
T55 1995 1 0 0
T56 659 1 0 0
T57 3273 2 0 0
T58 729 1 0 0
T59 797 1 0 0
T60 609 2 0 0
T69 23429 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 551 0 0
T23 737 11 0 0
T27 709 20 0 0
T28 299733 20 0 0
T55 1995 5 0 0
T56 659 7 0 0
T57 3273 12 0 0
T58 729 5 0 0
T59 797 11 0 0
T60 609 7 0 0
T69 23429 1 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3818 0 0
T6 64351 12 0 0
T7 2247 12 0 0
T8 25853 1 0 0
T19 963 1 0 0
T21 482 10 0 0
T34 524 6 0 0
T35 524 6 0 0
T36 502 5 0 0
T49 446 11 0 0
T75 422 3 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 91 0 0
T23 737 1 0 0
T27 709 2 0 0
T28 299733 2 0 0
T55 1995 1 0 0
T56 659 1 0 0
T57 3273 2 0 0
T58 729 1 0 0
T59 797 1 0 0
T60 609 2 0 0
T69 23429 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
TOTAL484695.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT7,T8,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT6,T21,T34
11CoveredT7,T8,T9

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT7,T8,T28
01CoveredT39,T40
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT7,T8,T28
01Unreachable
10CoveredT7,T8,T28

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Covered T10
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T7,T8,T9
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T28
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T7,T8,T9
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T7,T8,T28
DebounceSt - 0 1 0 - - - Covered T9,T54,T78
DebounceSt - 0 0 - - - - Covered T7,T8,T9
DetectSt - - - - 1 - - Covered T39,T40
DetectSt - - - - 0 1 - Covered T7,T8,T28
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T7,T8,T28
StableSt - - - - - - 0 Covered T7,T8,T28
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3351756 0 0
CntIncr_A 3964510 126061 0 0
CntNoWrap_A 3964510 126061 0 0
DetectStDropOut_A 3964510 4 0 0
DetectedOut_A 3964510 411034 0 0
DetectedPulseOut_A 3964510 56 0 0
DisabledIdleSt_A 3964510 2265531 0 0
DisabledNoDetection_A 3964510 2266796 0 0
EnterDebounceSt_A 3964510 117 0 0
EnterDetectSt_A 3964510 60 0 0
EnterStableSt_A 3964510 56 0 0
PulseIsPulse_A 3964510 56 0 0
StayInStableSt 3964510 410978 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 3818 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_sticky_sva.StableStDropOut_A 3964510 525029 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3351756 0 0
T6 64351 61945 0 0
T7 2247 1750 0 0
T8 25853 25394 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 126061 0 0
T7 2247 96 0 0
T8 25853 58 0 0
T9 1106 435 0 0
T17 10031 91 0 0
T28 299733 28850 0 0
T31 53863 28938 0 0
T54 2751 348 0 0
T78 1352 37 0 0
T79 1453 36 0 0
T80 1811 582 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 126061 0 0
T7 2247 96 0 0
T8 25853 58 0 0
T9 1106 435 0 0
T17 10031 91 0 0
T28 299733 28850 0 0
T31 53863 28938 0 0
T54 2751 348 0 0
T78 1352 37 0 0
T79 1453 36 0 0
T80 1811 582 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4 0 0
T39 3033 1 0 0
T40 1066 3 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 411034 0 0
T7 2247 302 0 0
T8 25853 46 0 0
T17 10031 254 0 0
T28 299733 104349 0 0
T31 53863 24257 0 0
T46 809 32 0 0
T79 1453 142 0 0
T81 1411 463 0 0
T82 1145 146 0 0
T83 1501 197 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 56 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T46 809 1 0 0
T79 1453 2 0 0
T81 1411 3 0 0
T82 1145 1 0 0
T83 1501 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2265531 0 0
T6 64351 61945 0 0
T7 2247 1396 0 0
T8 25853 33 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2266796 0 0
T6 64351 61951 0 0
T7 2247 1397 0 0
T8 25853 34 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 117 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 5 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T54 2751 4 0 0
T78 1352 1 0 0
T79 1453 2 0 0
T80 1811 6 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 60 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T46 809 1 0 0
T79 1453 2 0 0
T81 1411 3 0 0
T82 1145 1 0 0
T83 1501 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 56 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T46 809 1 0 0
T79 1453 2 0 0
T81 1411 3 0 0
T82 1145 1 0 0
T83 1501 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 56 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T46 809 1 0 0
T79 1453 2 0 0
T81 1411 3 0 0
T82 1145 1 0 0
T83 1501 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 410978 0 0
T7 2247 301 0 0
T8 25853 45 0 0
T17 10031 253 0 0
T28 299733 104348 0 0
T31 53863 24254 0 0
T46 809 31 0 0
T79 1453 140 0 0
T81 1411 460 0 0
T82 1145 145 0 0
T83 1501 196 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3818 0 0
T6 64351 12 0 0
T7 2247 12 0 0
T8 25853 1 0 0
T19 963 1 0 0
T21 482 10 0 0
T34 524 6 0 0
T35 524 6 0 0
T36 502 5 0 0
T49 446 11 0 0
T75 422 3 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 525029 0 0
T7 2247 41 0 0
T8 25853 25306 0 0
T17 10031 49 0 0
T28 299733 156304 0 0
T31 53863 130 0 0
T46 809 22 0 0
T79 1453 417 0 0
T81 1411 107 0 0
T82 1145 128 0 0
T83 1501 43 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
TOTAL484695.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
TotalCoveredPercent
Conditions131184.62
Logical131184.62
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT6,T21,T34
11CoveredT7,T8,T9

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT7,T8,T9
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT7,T8,T9
01Unreachable
10CoveredT7,T8,T9

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T7,T8,T9
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T7,T8,T9
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Covered T44
DebounceSt - 0 1 1 - - - Covered T7,T8,T9
DebounceSt - 0 1 0 - - - Covered T31,T78,T86
DebounceSt - 0 0 - - - - Covered T7,T8,T9
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T7,T8,T9
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T7,T8,T9
StableSt - - - - - - 0 Covered T7,T8,T9
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3325558 0 0
CntIncr_A 3964510 152259 0 0
CntNoWrap_A 3964510 152259 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 320388 0 0
DetectedPulseOut_A 3964510 69 0 0
DisabledIdleSt_A 3964510 2265531 0 0
DisabledNoDetection_A 3964510 2266796 0 0
EnterDebounceSt_A 3964510 99 0 0
EnterDetectSt_A 3964510 69 0 0
EnterStableSt_A 3964510 69 0 0
PulseIsPulse_A 3964510 69 0 0
StayInStableSt 3964510 320319 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_sticky_sva.StableStDropOut_A 3964510 458503 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3325558 0 0
T6 64351 61945 0 0
T7 2247 1788 0 0
T8 25853 752 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 152259 0 0
T7 2247 58 0 0
T8 25853 24700 0 0
T9 1106 106 0 0
T17 10031 21 0 0
T28 299733 43 0 0
T31 53863 869 0 0
T54 2751 41 0 0
T78 1352 32 0 0
T79 1453 122 0 0
T80 1811 126 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 152259 0 0
T7 2247 58 0 0
T8 25853 24700 0 0
T9 1106 106 0 0
T17 10031 21 0 0
T28 299733 43 0 0
T31 53863 869 0 0
T54 2751 41 0 0
T78 1352 32 0 0
T79 1453 122 0 0
T80 1811 126 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 320388 0 0
T7 2247 286 0 0
T8 25853 684 0 0
T9 1106 197 0 0
T17 10031 134 0 0
T28 299733 176 0 0
T46 809 13 0 0
T54 2751 158 0 0
T79 1453 391 0 0
T80 1811 496 0 0
T81 1411 325 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 69 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T46 809 1 0 0
T54 2751 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0
T81 1411 3 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2265531 0 0
T6 64351 61945 0 0
T7 2247 1396 0 0
T8 25853 33 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2266796 0 0
T6 64351 61951 0 0
T7 2247 1397 0 0
T8 25853 34 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 99 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 11 0 0
T54 2751 1 0 0
T78 1352 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 69 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T46 809 1 0 0
T54 2751 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0
T81 1411 3 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 69 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T46 809 1 0 0
T54 2751 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0
T81 1411 3 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 69 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T46 809 1 0 0
T54 2751 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0
T81 1411 3 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 320319 0 0
T7 2247 285 0 0
T8 25853 683 0 0
T9 1106 195 0 0
T17 10031 133 0 0
T28 299733 175 0 0
T46 809 12 0 0
T54 2751 157 0 0
T79 1453 389 0 0
T80 1811 494 0 0
T81 1411 322 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 458503 0 0
T7 2247 97 0 0
T8 25853 22 0 0
T9 1106 326 0 0
T17 10031 250 0 0
T28 299733 289273 0 0
T46 809 53 0 0
T54 2751 343 0 0
T79 1453 89 0 0
T80 1811 98 0 0
T81 1411 379 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
TOTAL454395.56
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT7,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT6,T21,T34
11CoveredT7,T8,T9

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT38
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT7,T8,T9
01Unreachable
10CoveredT7,T8,T9

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Covered T10
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
Branches 18 17 94.44
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 222 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T7,T8,T9
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T7,T8,T9
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T7,T8,T9
DebounceSt - 0 1 0 - - - Covered T46,T47,T48
DebounceSt - 0 0 - - - - Covered T7,T8,T9
DetectSt - - - - 1 - - Covered T38
DetectSt - - - - 0 1 - Covered T7,T8,T9
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T7,T8,T9
StableSt - - - - - - 0 Covered T7,T8,T9
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3319547 0 0
CntIncr_A 3964510 158270 0 0
CntNoWrap_A 3964510 158270 0 0
DetectStDropOut_A 3964510 2 0 0
DetectedOut_A 3964510 244733 0 0
DetectedPulseOut_A 3964510 66 0 0
DisabledIdleSt_A 3964510 2265531 0 0
DisabledNoDetection_A 3964510 2266796 0 0
EnterDebounceSt_A 3964510 96 0 0
EnterDetectSt_A 3964510 68 0 0
EnterStableSt_A 3964510 66 0 0
PulseIsPulse_A 3964510 66 0 0
StayInStableSt 3964510 244667 0 0
gen_high_event_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_sticky_sva.StableStDropOut_A 3964510 480798 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3319547 0 0
T6 64351 61945 0 0
T7 2247 1766 0 0
T8 25853 25391 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 158270 0 0
T7 2247 80 0 0
T8 25853 61 0 0
T9 1106 142 0 0
T17 10031 13 0 0
T28 299733 63113 0 0
T31 53863 192 0 0
T54 2751 90 0 0
T78 1352 93 0 0
T79 1453 138 0 0
T80 1811 68 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 158270 0 0
T7 2247 80 0 0
T8 25853 61 0 0
T9 1106 142 0 0
T17 10031 13 0 0
T28 299733 63113 0 0
T31 53863 192 0 0
T54 2751 90 0 0
T78 1352 93 0 0
T79 1453 138 0 0
T80 1811 68 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2 0 0
T38 10871 2 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 244733 0 0
T7 2247 207 0 0
T8 25853 44 0 0
T9 1106 446 0 0
T17 10031 78 0 0
T28 299733 226374 0 0
T31 53863 718 0 0
T54 2751 445 0 0
T78 1352 14 0 0
T79 1453 275 0 0
T80 1811 218 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 66 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T54 2751 1 0 0
T78 1352 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2265531 0 0
T6 64351 61945 0 0
T7 2247 1396 0 0
T8 25853 33 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2266796 0 0
T6 64351 61951 0 0
T7 2247 1397 0 0
T8 25853 34 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 96 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T54 2751 1 0 0
T78 1352 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 68 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T54 2751 1 0 0
T78 1352 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 66 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T54 2751 1 0 0
T78 1352 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 66 0 0
T7 2247 1 0 0
T8 25853 1 0 0
T9 1106 2 0 0
T17 10031 1 0 0
T28 299733 1 0 0
T31 53863 3 0 0
T54 2751 1 0 0
T78 1352 1 0 0
T79 1453 2 0 0
T80 1811 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 244667 0 0
T7 2247 206 0 0
T8 25853 43 0 0
T9 1106 444 0 0
T17 10031 77 0 0
T28 299733 226373 0 0
T31 53863 715 0 0
T54 2751 444 0 0
T78 1352 13 0 0
T79 1453 273 0 0
T80 1811 216 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 480798 0 0
T7 2247 160 0 0
T8 25853 25311 0 0
T9 1106 47 0 0
T17 10031 320 0 0
T28 299733 25 0 0
T31 53863 52449 0 0
T54 2751 25 0 0
T78 1352 22 0 0
T79 1453 208 0 0
T80 1811 466 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT20,T87,T88
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT20,T87,T88

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT20,T87,T88

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT20,T45,T57
10CoveredT6,T21,T34
11CoveredT20,T87,T88

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT20,T87,T88
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT20,T87,T88
01CoveredT87,T89,T90
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT20,T87,T88
1-CoveredT87,T89,T90

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T20,T87,T88
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T20,T87,T88
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T20,T87,T88
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T20,T87,T88
DebounceSt - 0 1 0 - - - Covered T91,T92
DebounceSt - 0 0 - - - - Covered T20,T87,T88
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T20,T87,T88
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T87,T89,T90
StableSt - - - - - - 0 Covered T20,T87,T88
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3264929 0 0
CntIncr_A 3964510 212888 0 0
CntNoWrap_A 3964510 212888 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 824 0 0
DetectedPulseOut_A 3964510 12 0 0
DisabledIdleSt_A 3964510 2961825 0 0
DisabledNoDetection_A 3964510 2963072 0 0
EnterDebounceSt_A 3964510 14 0 0
EnterDetectSt_A 3964510 12 0 0
EnterStableSt_A 3964510 12 0 0
PulseIsPulse_A 3964510 12 0 0
StayInStableSt 3964510 805 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 5 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3264929 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 212888 0 0
T20 3758 50 0 0
T87 321439 126070 0 0
T88 5876 83 0 0
T89 6770 70 0 0
T90 623 39 0 0
T91 745 89 0 0
T92 566 22 0 0
T93 539 18 0 0
T94 850 90 0 0
T95 907 94 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 212888 0 0
T20 3758 50 0 0
T87 321439 126070 0 0
T88 5876 83 0 0
T89 6770 70 0 0
T90 623 39 0 0
T91 745 89 0 0
T92 566 22 0 0
T93 539 18 0 0
T94 850 90 0 0
T95 907 94 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 824 0 0
T20 3758 74 0 0
T87 321439 73 0 0
T88 5876 34 0 0
T89 6770 65 0 0
T90 623 90 0 0
T93 539 47 0 0
T94 850 202 0 0
T95 907 125 0 0
T96 190658 68 0 0
T97 2538 46 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T20 3758 1 0 0
T87 321439 2 0 0
T88 5876 1 0 0
T89 6770 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T96 190658 2 0 0
T97 2538 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2961825 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2963072 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 14 0 0
T20 3758 1 0 0
T87 321439 2 0 0
T88 5876 1 0 0
T89 6770 1 0 0
T90 623 1 0 0
T91 745 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T95 907 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T20 3758 1 0 0
T87 321439 2 0 0
T88 5876 1 0 0
T89 6770 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T96 190658 2 0 0
T97 2538 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T20 3758 1 0 0
T87 321439 2 0 0
T88 5876 1 0 0
T89 6770 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T96 190658 2 0 0
T97 2538 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T20 3758 1 0 0
T87 321439 2 0 0
T88 5876 1 0 0
T89 6770 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T96 190658 2 0 0
T97 2538 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 805 0 0
T20 3758 72 0 0
T87 321439 70 0 0
T88 5876 32 0 0
T89 6770 64 0 0
T90 623 89 0 0
T93 539 45 0 0
T94 850 200 0 0
T95 907 124 0 0
T96 190658 65 0 0
T97 2538 44 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 5 0 0
T87 321439 1 0 0
T89 6770 1 0 0
T90 623 1 0 0
T95 907 1 0 0
T96 190658 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T20,T45
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T20,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T20,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T20,T45
10CoveredT6,T21,T34
11CoveredT6,T20,T45

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T20,T45
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T20,T45
01CoveredT20,T98,T99
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T20,T45
1-CoveredT20,T98,T99

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T20,T45
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T20,T45
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T20,T45
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T20,T45
DebounceSt - 0 1 0 - - - Covered T6,T89,T100
DebounceSt - 0 0 - - - - Covered T6,T20,T45
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T20,T45
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T20,T98,T99
StableSt - - - - - - 0 Covered T6,T20,T45
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3390364 0 0
CntIncr_A 3964510 87453 0 0
CntNoWrap_A 3964510 87453 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 18903 0 0
DetectedPulseOut_A 3964510 22 0 0
DisabledIdleSt_A 3964510 3282227 0 0
DisabledNoDetection_A 3964510 3283471 0 0
EnterDebounceSt_A 3964510 25 0 0
EnterDetectSt_A 3964510 22 0 0
EnterStableSt_A 3964510 22 0 0
PulseIsPulse_A 3964510 22 0 0
StayInStableSt 3964510 18869 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 2652 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 10 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3390364 0 0
T6 64351 61793 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 87453 0 0
T6 64351 152 0 0
T18 711 55 0 0
T20 3758 50 0 0
T38 10871 72 0 0
T45 852 92 0 0
T85 14254 41 0 0
T91 745 178 0 0
T98 559 15 0 0
T99 537 38 0 0
T101 231264 21 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 87453 0 0
T6 64351 152 0 0
T18 711 55 0 0
T20 3758 50 0 0
T38 10871 72 0 0
T45 852 92 0 0
T85 14254 41 0 0
T91 745 178 0 0
T98 559 15 0 0
T99 537 38 0 0
T101 231264 21 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 18903 0 0
T6 64351 73 0 0
T18 711 37 0 0
T20 3758 54 0 0
T38 10871 150 0 0
T45 852 34 0 0
T85 14254 92 0 0
T91 745 70 0 0
T98 559 62 0 0
T99 537 81 0 0
T101 231264 100 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 22 0 0
T6 64351 1 0 0
T18 711 1 0 0
T20 3758 1 0 0
T38 10871 1 0 0
T45 852 1 0 0
T85 14254 1 0 0
T91 745 2 0 0
T98 559 1 0 0
T99 537 2 0 0
T101 231264 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3282227 0 0
T6 64351 61634 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3283471 0 0
T6 64351 61639 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 25 0 0
T6 64351 2 0 0
T18 711 1 0 0
T20 3758 1 0 0
T38 10871 1 0 0
T45 852 1 0 0
T85 14254 1 0 0
T91 745 2 0 0
T98 559 1 0 0
T99 537 2 0 0
T101 231264 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 22 0 0
T6 64351 1 0 0
T18 711 1 0 0
T20 3758 1 0 0
T38 10871 1 0 0
T45 852 1 0 0
T85 14254 1 0 0
T91 745 2 0 0
T98 559 1 0 0
T99 537 2 0 0
T101 231264 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 22 0 0
T6 64351 1 0 0
T18 711 1 0 0
T20 3758 1 0 0
T38 10871 1 0 0
T45 852 1 0 0
T85 14254 1 0 0
T91 745 2 0 0
T98 559 1 0 0
T99 537 2 0 0
T101 231264 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 22 0 0
T6 64351 1 0 0
T18 711 1 0 0
T20 3758 1 0 0
T38 10871 1 0 0
T45 852 1 0 0
T85 14254 1 0 0
T91 745 2 0 0
T98 559 1 0 0
T99 537 2 0 0
T101 231264 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 18869 0 0
T6 64351 71 0 0
T18 711 35 0 0
T20 3758 53 0 0
T38 10871 148 0 0
T45 852 32 0 0
T85 14254 90 0 0
T91 745 67 0 0
T98 559 61 0 0
T99 537 78 0 0
T101 231264 98 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2652 0 0
T6 64351 9 0 0
T19 963 2 0 0
T21 482 5 0 0
T30 1872 13 0 0
T34 524 5 0 0
T35 524 5 0 0
T36 502 6 0 0
T49 446 12 0 0
T75 422 5 0 0
T76 423 3 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T20 3758 1 0 0
T91 745 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T96 190658 2 0 0
T97 2538 1 0 0
T98 559 1 0 0
T99 537 1 0 0
T102 748 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T19,T20
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T19,T20
10CoveredT6,T21,T34
11CoveredT6,T19,T20

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T19,T20
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T19,T20
01CoveredT20,T28,T45
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T19,T20
1-CoveredT20,T28,T45

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T19,T20
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T19,T20
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T19,T20
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T19,T20
DebounceSt - 0 1 0 - - - Covered T6,T92
DebounceSt - 0 0 - - - - Covered T6,T19,T20
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T19,T20
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T20,T28,T45
StableSt - - - - - - 0 Covered T6,T19,T20
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3399062 0 0
CntIncr_A 3964510 78755 0 0
CntNoWrap_A 3964510 78755 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 1202 0 0
DetectedPulseOut_A 3964510 17 0 0
DisabledIdleSt_A 3964510 3314412 0 0
DisabledNoDetection_A 3964510 3315652 0 0
EnterDebounceSt_A 3964510 19 0 0
EnterDetectSt_A 3964510 17 0 0
EnterStableSt_A 3964510 17 0 0
PulseIsPulse_A 3964510 17 0 0
StayInStableSt 3964510 1176 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 8 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3399062 0 0
T6 64351 61842 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 468 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78755 0 0
T6 64351 103 0 0
T19 963 94 0 0
T20 3758 50 0 0
T28 299733 36 0 0
T38 10871 72 0 0
T43 6768 61 0 0
T45 852 92 0 0
T57 3273 86 0 0
T85 14254 36 0 0
T99 537 19 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78755 0 0
T6 64351 103 0 0
T19 963 94 0 0
T20 3758 50 0 0
T28 299733 36 0 0
T38 10871 72 0 0
T43 6768 61 0 0
T45 852 92 0 0
T57 3273 86 0 0
T85 14254 36 0 0
T99 537 19 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1202 0 0
T6 64351 38 0 0
T19 963 219 0 0
T20 3758 35 0 0
T28 299733 35 0 0
T38 10871 42 0 0
T43 6768 130 0 0
T45 852 215 0 0
T57 3273 58 0 0
T85 14254 81 0 0
T99 537 44 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T28 299733 1 0 0
T38 10871 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T99 537 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3314412 0 0
T6 64351 61451 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 3 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3315652 0 0
T6 64351 61455 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 3 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T6 64351 2 0 0
T19 963 1 0 0
T20 3758 1 0 0
T28 299733 1 0 0
T38 10871 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T99 537 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T28 299733 1 0 0
T38 10871 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T99 537 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T28 299733 1 0 0
T38 10871 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T99 537 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T28 299733 1 0 0
T38 10871 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T99 537 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1176 0 0
T6 64351 36 0 0
T19 963 217 0 0
T20 3758 34 0 0
T28 299733 34 0 0
T38 10871 40 0 0
T43 6768 129 0 0
T45 852 214 0 0
T57 3273 57 0 0
T85 14254 80 0 0
T99 537 42 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 8 0 0
T20 3758 1 0 0
T28 299733 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T103 951 1 0 0
T104 157503 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T20,T28
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T20,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T20,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T20,T28
10CoveredT6,T21,T34
11CoveredT6,T20,T28

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T20,T28
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T20,T28
01CoveredT6,T28,T99
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T20,T28
1-CoveredT6,T28,T99

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T20,T28
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T20,T28
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T20,T28
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T20,T28
DebounceSt - 0 1 0 - - - Covered T20,T45,T88
DebounceSt - 0 0 - - - - Covered T6,T20,T28
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T20,T28
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T6,T28,T99
StableSt - - - - - - 0 Covered T6,T20,T28
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3398998 0 0
CntIncr_A 3964510 78819 0 0
CntNoWrap_A 3964510 78819 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 13709 0 0
DetectedPulseOut_A 3964510 17 0 0
DisabledIdleSt_A 3964510 3316515 0 0
DisabledNoDetection_A 3964510 3317761 0 0
EnterDebounceSt_A 3964510 23 0 0
EnterDetectSt_A 3964510 17 0 0
EnterStableSt_A 3964510 17 0 0
PulseIsPulse_A 3964510 17 0 0
StayInStableSt 3964510 13684 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 2994 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 9 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3398998 0 0
T6 64351 61918 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78819 0 0
T6 64351 27 0 0
T20 3758 100 0 0
T28 299733 72 0 0
T43 6768 122 0 0
T45 852 184 0 0
T85 14254 41 0 0
T88 5876 83 0 0
T99 537 19 0 0
T105 592 26 0 0
T106 1935 12 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78819 0 0
T6 64351 27 0 0
T20 3758 100 0 0
T28 299733 72 0 0
T43 6768 122 0 0
T45 852 184 0 0
T85 14254 41 0 0
T88 5876 83 0 0
T99 537 19 0 0
T105 592 26 0 0
T106 1935 12 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13709 0 0
T6 64351 35 0 0
T20 3758 74 0 0
T28 299733 65 0 0
T43 6768 54 0 0
T45 852 34 0 0
T85 14254 35 0 0
T99 537 35 0 0
T105 592 117 0 0
T106 1935 41 0 0
T107 670 81 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 2 0 0
T45 852 1 0 0
T85 14254 1 0 0
T99 537 1 0 0
T105 592 1 0 0
T106 1935 1 0 0
T107 670 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3316515 0 0
T6 64351 61762 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3317761 0 0
T6 64351 61767 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 23 0 0
T6 64351 1 0 0
T20 3758 2 0 0
T28 299733 2 0 0
T43 6768 2 0 0
T45 852 2 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T99 537 1 0 0
T105 592 1 0 0
T106 1935 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 2 0 0
T45 852 1 0 0
T85 14254 1 0 0
T99 537 1 0 0
T105 592 1 0 0
T106 1935 1 0 0
T107 670 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 2 0 0
T45 852 1 0 0
T85 14254 1 0 0
T99 537 1 0 0
T105 592 1 0 0
T106 1935 1 0 0
T107 670 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 17 0 0
T6 64351 1 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 2 0 0
T45 852 1 0 0
T85 14254 1 0 0
T99 537 1 0 0
T105 592 1 0 0
T106 1935 1 0 0
T107 670 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13684 0 0
T6 64351 34 0 0
T20 3758 72 0 0
T28 299733 62 0 0
T43 6768 51 0 0
T45 852 32 0 0
T85 14254 33 0 0
T99 537 34 0 0
T105 592 115 0 0
T106 1935 39 0 0
T107 670 79 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2994 0 0
T6 64351 9 0 0
T19 963 1 0 0
T21 482 4 0 0
T22 717 2 0 0
T30 1872 11 0 0
T34 524 6 0 0
T35 524 6 0 0
T36 502 7 0 0
T49 446 11 0 0
T75 422 5 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 9 0 0
T6 64351 1 0 0
T28 299733 1 0 0
T43 6768 1 0 0
T90 623 1 0 0
T97 2538 1 0 0
T99 537 1 0 0
T100 668 1 0 0
T104 157503 1 0 0
T108 762 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T57,T85
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T57,T85

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T57,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T98,T57
10CoveredT6,T21,T34
11CoveredT6,T57,T85

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T57,T85
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T57,T85
01CoveredT6,T57,T104
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T57,T85
1-CoveredT6,T57,T104

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T57,T85
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T57,T85
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T57,T85
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T57,T85
DebounceSt - 0 1 0 - - - Covered T38,T93,T97
DebounceSt - 0 0 - - - - Covered T6,T57,T85
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T57,T85
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T6,T57,T104
StableSt - - - - - - 0 Covered T6,T57,T85
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3399310 0 0
CntIncr_A 3964510 78507 0 0
CntNoWrap_A 3964510 78507 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 910 0 0
DetectedPulseOut_A 3964510 12 0 0
DisabledIdleSt_A 3964510 3317947 0 0
DisabledNoDetection_A 3964510 3319199 0 0
EnterDebounceSt_A 3964510 16 0 0
EnterDetectSt_A 3964510 12 0 0
EnterStableSt_A 3964510 12 0 0
PulseIsPulse_A 3964510 12 0 0
StayInStableSt 3964510 891 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 5 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3399310 0 0
T6 64351 61815 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78507 0 0
T6 64351 130 0 0
T38 10871 144 0 0
T57 3273 86 0 0
T85 14254 41 0 0
T89 6770 70 0 0
T93 539 36 0 0
T97 2538 34 0 0
T100 668 43 0 0
T104 157503 77870 0 0
T107 670 53 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78507 0 0
T6 64351 130 0 0
T38 10871 144 0 0
T57 3273 86 0 0
T85 14254 41 0 0
T89 6770 70 0 0
T93 539 36 0 0
T97 2538 34 0 0
T100 668 43 0 0
T104 157503 77870 0 0
T107 670 53 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 910 0 0
T6 64351 194 0 0
T38 10871 42 0 0
T57 3273 35 0 0
T85 14254 201 0 0
T89 6770 203 0 0
T93 539 47 0 0
T100 668 37 0 0
T104 157503 70 0 0
T107 670 81 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T6 64351 3 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T89 6770 1 0 0
T93 539 1 0 0
T100 668 1 0 0
T104 157503 2 0 0
T107 670 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3317947 0 0
T6 64351 61451 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3319199 0 0
T6 64351 61455 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 16 0 0
T6 64351 3 0 0
T38 10871 2 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T89 6770 1 0 0
T93 539 2 0 0
T97 2538 2 0 0
T100 668 1 0 0
T104 157503 2 0 0
T107 670 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T6 64351 3 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T89 6770 1 0 0
T93 539 1 0 0
T100 668 1 0 0
T104 157503 2 0 0
T107 670 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T6 64351 3 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T89 6770 1 0 0
T93 539 1 0 0
T100 668 1 0 0
T104 157503 2 0 0
T107 670 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T6 64351 3 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T89 6770 1 0 0
T93 539 1 0 0
T100 668 1 0 0
T104 157503 2 0 0
T107 670 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 891 0 0
T6 64351 190 0 0
T38 10871 40 0 0
T57 3273 34 0 0
T85 14254 199 0 0
T89 6770 201 0 0
T93 539 45 0 0
T100 668 36 0 0
T104 157503 67 0 0
T107 670 79 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 5 0 0
T6 64351 2 0 0
T57 3273 1 0 0
T100 668 1 0 0
T104 157503 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T19,T109
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T19,T109

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT19,T109,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T19,T110
10CoveredT6,T21,T34
11CoveredT6,T19,T109

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT19,T109,T85
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT19,T109,T85
01CoveredT19,T85,T38
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT19,T109,T85
1-CoveredT19,T85,T38

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T19,T109
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T19,T109,T85
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T19,T109
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T19,T109,T85
DebounceSt - 0 1 0 - - - Covered T6,T104
DebounceSt - 0 0 - - - - Covered T6,T19,T109
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T19,T109,T85
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T19,T85,T38
StableSt - - - - - - 0 Covered T19,T109,T85
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3395273 0 0
CntIncr_A 3964510 82544 0 0
CntNoWrap_A 3964510 82544 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 103786 0 0
DetectedPulseOut_A 3964510 10 0 0
DisabledIdleSt_A 3964510 3125744 0 0
DisabledNoDetection_A 3964510 3126991 0 0
EnterDebounceSt_A 3964510 12 0 0
EnterDetectSt_A 3964510 10 0 0
EnterStableSt_A 3964510 10 0 0
PulseIsPulse_A 3964510 10 0 0
StayInStableSt 3964510 103771 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 3584 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 5 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3395273 0 0
T6 64351 61918 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 468 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 82544 0 0
T6 64351 27 0 0
T19 963 94 0 0
T38 10871 72 0 0
T85 14254 36 0 0
T90 623 39 0 0
T93 539 18 0 0
T94 850 90 0 0
T104 157503 38935 0 0
T108 762 57 0 0
T109 507 10 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 82544 0 0
T6 64351 27 0 0
T19 963 94 0 0
T38 10871 72 0 0
T85 14254 36 0 0
T90 623 39 0 0
T93 539 18 0 0
T94 850 90 0 0
T104 157503 38935 0 0
T108 762 57 0 0
T109 507 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 103786 0 0
T19 963 88 0 0
T38 10871 35 0 0
T85 14254 9 0 0
T90 623 35 0 0
T93 539 35 0 0
T94 850 35 0 0
T96 190658 103329 0 0
T100 668 35 0 0
T108 762 101 0 0
T109 507 84 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T96 190658 1 0 0
T100 668 1 0 0
T108 762 1 0 0
T109 507 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3125744 0 0
T6 64351 61762 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 3 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3126991 0 0
T6 64351 61767 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 3 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 12 0 0
T6 64351 1 0 0
T19 963 1 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T104 157503 1 0 0
T108 762 1 0 0
T109 507 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T96 190658 1 0 0
T100 668 1 0 0
T108 762 1 0 0
T109 507 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T96 190658 1 0 0
T100 668 1 0 0
T108 762 1 0 0
T109 507 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T90 623 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T96 190658 1 0 0
T100 668 1 0 0
T108 762 1 0 0
T109 507 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 103771 0 0
T19 963 87 0 0
T38 10871 34 0 0
T85 14254 8 0 0
T90 623 34 0 0
T93 539 34 0 0
T94 850 33 0 0
T96 190658 103327 0 0
T100 668 33 0 0
T108 762 99 0 0
T109 507 82 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3584 0 0
T6 64351 13 0 0
T7 2247 12 0 0
T8 25853 1 0 0
T19 963 1 0 0
T21 482 9 0 0
T34 524 4 0 0
T35 524 4 0 0
T36 502 5 0 0
T49 446 12 0 0
T75 422 3 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 5 0 0
T19 963 1 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T90 623 1 0 0
T93 539 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T19,T109
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T19,T109

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T19,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T19,T109
10CoveredT6,T21,T34
11CoveredT6,T19,T109

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T19,T85
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T19,T85
01CoveredT6,T19,T102
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T19,T85
1-CoveredT6,T19,T102

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T19,T109
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T19,T85
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T19,T109
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T19,T85
DebounceSt - 0 1 0 - - - Covered T109,T91,T111
DebounceSt - 0 0 - - - - Covered T6,T19,T109
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T19,T85
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T6,T19,T102
StableSt - - - - - - 0 Covered T6,T19,T85
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3433928 0 0
CntIncr_A 3964510 43889 0 0
CntNoWrap_A 3964510 43889 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 1516 0 0
DetectedPulseOut_A 3964510 9 0 0
DisabledIdleSt_A 3964510 3284633 0 0
DisabledNoDetection_A 3964510 3285887 0 0
EnterDebounceSt_A 3964510 13 0 0
EnterDetectSt_A 3964510 9 0 0
EnterStableSt_A 3964510 9 0 0
PulseIsPulse_A 3964510 9 0 0
StayInStableSt 3964510 1502 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 4 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3433928 0 0
T6 64351 61869 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 468 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 43889 0 0
T6 64351 76 0 0
T19 963 94 0 0
T85 14254 77 0 0
T90 623 39 0 0
T91 745 178 0 0
T96 190658 43123 0 0
T102 748 184 0 0
T109 507 10 0 0
T111 2584 108 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 43889 0 0
T6 64351 76 0 0
T19 963 94 0 0
T85 14254 77 0 0
T90 623 39 0 0
T91 745 178 0 0
T96 190658 43123 0 0
T102 748 184 0 0
T109 507 10 0 0
T111 2584 108 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1516 0 0
T6 64351 73 0 0
T19 963 218 0 0
T85 14254 324 0 0
T90 623 39 0 0
T96 190658 675 0 0
T102 748 70 0 0
T111 2584 117 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 9 0 0
T6 64351 1 0 0
T19 963 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T96 190658 1 0 0
T102 748 2 0 0
T111 2584 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3284633 0 0
T6 64351 61634 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 3 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3285887 0 0
T6 64351 61639 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 3 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13 0 0
T6 64351 1 0 0
T19 963 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T91 745 2 0 0
T96 190658 1 0 0
T102 748 2 0 0
T109 507 1 0 0
T111 2584 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 9 0 0
T6 64351 1 0 0
T19 963 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T96 190658 1 0 0
T102 748 2 0 0
T111 2584 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 9 0 0
T6 64351 1 0 0
T19 963 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T96 190658 1 0 0
T102 748 2 0 0
T111 2584 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 9 0 0
T6 64351 1 0 0
T19 963 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T96 190658 1 0 0
T102 748 2 0 0
T111 2584 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1502 0 0
T6 64351 72 0 0
T19 963 217 0 0
T85 14254 320 0 0
T90 623 37 0 0
T96 190658 674 0 0
T102 748 67 0 0
T111 2584 115 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4 0 0
T6 64351 1 0 0
T19 963 1 0 0
T96 190658 1 0 0
T102 748 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T19,T28
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T19,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT19,T28,T109

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T19,T28
10CoveredT6,T21,T34
11CoveredT6,T19,T28

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT19,T28,T109
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT19,T28,T109
01CoveredT28,T105,T111
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT19,T28,T109
1-CoveredT28,T105,T111

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T19,T28
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T19,T28,T109
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T19,T28
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T19,T28,T109
DebounceSt - 0 1 0 - - - Covered T6,T38,T89
DebounceSt - 0 0 - - - - Covered T6,T19,T28
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T19,T28,T109
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T28,T105,T111
StableSt - - - - - - 0 Covered T19,T28,T109
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3476987 0 0
CntIncr_A 3964510 830 0 0
CntNoWrap_A 3964510 830 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 973 0 0
DetectedPulseOut_A 3964510 15 0 0
DisabledIdleSt_A 3964510 3471998 0 0
DisabledNoDetection_A 3964510 3473242 0 0
EnterDebounceSt_A 3964510 18 0 0
EnterDetectSt_A 3964510 15 0 0
EnterStableSt_A 3964510 15 0 0
PulseIsPulse_A 3964510 15 0 0
StayInStableSt 3964510 948 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 3196 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 5 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3476987 0 0
T6 64351 61918 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 468 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 830 0 0
T6 64351 27 0 0
T19 963 94 0 0
T28 299733 72 0 0
T38 10871 72 0 0
T43 6768 61 0 0
T89 6770 70 0 0
T92 566 22 0 0
T101 231264 21 0 0
T105 592 26 0 0
T109 507 10 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 830 0 0
T6 64351 27 0 0
T19 963 94 0 0
T28 299733 72 0 0
T38 10871 72 0 0
T43 6768 61 0 0
T89 6770 70 0 0
T92 566 22 0 0
T101 231264 21 0 0
T105 592 26 0 0
T109 507 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 973 0 0
T19 963 36 0 0
T28 299733 68 0 0
T43 6768 45 0 0
T92 566 34 0 0
T93 539 35 0 0
T94 850 76 0 0
T101 231264 100 0 0
T105 592 35 0 0
T109 507 84 0 0
T111 2584 35 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 15 0 0
T19 963 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T101 231264 1 0 0
T105 592 1 0 0
T109 507 1 0 0
T111 2584 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3471998 0 0
T6 64351 61762 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 3 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3473242 0 0
T6 64351 61767 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 3 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 18 0 0
T6 64351 1 0 0
T19 963 1 0 0
T28 299733 2 0 0
T38 10871 1 0 0
T43 6768 1 0 0
T89 6770 1 0 0
T92 566 1 0 0
T101 231264 1 0 0
T105 592 1 0 0
T109 507 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 15 0 0
T19 963 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T101 231264 1 0 0
T105 592 1 0 0
T109 507 1 0 0
T111 2584 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 15 0 0
T19 963 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T101 231264 1 0 0
T105 592 1 0 0
T109 507 1 0 0
T111 2584 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 15 0 0
T19 963 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T101 231264 1 0 0
T105 592 1 0 0
T109 507 1 0 0
T111 2584 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 948 0 0
T19 963 34 0 0
T28 299733 65 0 0
T43 6768 43 0 0
T92 566 32 0 0
T93 539 33 0 0
T94 850 75 0 0
T101 231264 98 0 0
T105 592 34 0 0
T109 507 82 0 0
T111 2584 34 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3196 0 0
T6 64351 8 0 0
T19 963 1 0 0
T21 482 11 0 0
T30 1872 12 0 0
T34 524 4 0 0
T35 524 6 0 0
T36 502 4 0 0
T49 446 9 0 0
T75 422 3 0 0
T76 423 6 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 5 0 0
T28 299733 1 0 0
T94 850 1 0 0
T105 592 1 0 0
T111 2584 1 0 0
T112 624 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%