Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T1 T2 T4
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T2 T4
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T2 T4
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T2 T4
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T4 T5 T27
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T4
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T4
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
105 1/1 cnt_q <= '0;
Tests: T1 T2 T4
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T4
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T2 T4
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T4
129 1/1 cnt_en = 1'b0;
Tests: T1 T2 T4
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T2 T4
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T2 T4
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T2 T4
139
140 1/1 unique case (state_q)
Tests: T1 T2 T4
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T2 T4
148 1/1 state_d = DebounceSt;
Tests: T4 T5 T27
149 1/1 cnt_en = 1'b1;
Tests: T4 T5 T27
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T4 T5 T27
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T4 T5 T27
163 1/1 state_d = IdleSt;
Tests: T21 T56
164 1/1 cnt_clr = 1'b1;
Tests: T21 T56
165 1/1 end else if (cnt_done) begin
Tests: T4 T5 T27
166 1/1 cnt_clr = 1'b1;
Tests: T4 T5 T27
167 1/1 if (trigger_active) begin
Tests: T4 T5 T27
168 1/1 state_d = DetectSt;
Tests: T4 T5 T27
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T61 T70 T54
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T4 T5 T27
182 1/1 cnt_en = 1'b1;
Tests: T4 T5 T27
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T4 T5 T27
186 1/1 state_d = IdleSt;
Tests: T45 T39 T63
187 1/1 cnt_clr = 1'b1;
Tests: T45 T39 T63
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T4 T5 T27
191 1/1 state_d = StableSt;
Tests: T4 T5 T27
192 1/1 cnt_clr = 1'b1;
Tests: T4 T5 T27
193 1/1 event_detected_o = 1'b1;
Tests: T4 T5 T27
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T4 T5 T27
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T4 T5 T27
206 1/1 state_d = IdleSt;
Tests: T4 T5 T27
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T4 T5 T27
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
220 1/1 state_q <= IdleSt;
Tests: T1 T2 T4
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T2 T4
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T2 T4
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T2 T4
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T2 T4
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T2 T4
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T5 T8 T9
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T12
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T12
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
105 1/1 cnt_q <= '0;
Tests: T1 T2 T4
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T4
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T2 T4
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T4
129 1/1 cnt_en = 1'b0;
Tests: T1 T2 T4
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T2 T4
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T2 T4
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T2 T4
139
140 1/1 unique case (state_q)
Tests: T1 T2 T4
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T2 T4
148 1/1 state_d = DebounceSt;
Tests: T5 T8 T9
149 1/1 cnt_en = 1'b1;
Tests: T5 T8 T9
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T5 T8 T9
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T5 T8 T9
163 1/1 state_d = IdleSt;
Tests: T21 T56
164 1/1 cnt_clr = 1'b1;
Tests: T21 T56
165 1/1 end else if (cnt_done) begin
Tests: T5 T8 T9
166 1/1 cnt_clr = 1'b1;
Tests: T5 T8 T9
167 1/1 if (trigger_active) begin
Tests: T5 T8 T9
168 1/1 state_d = DetectSt;
Tests: T5 T8 T9
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T53 T115 T97
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T5 T8 T9
182 1/1 cnt_en = 1'b1;
Tests: T5 T8 T9
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T5 T8 T9
186 1/1 state_d = IdleSt;
Tests: T56 T115 T97
187 1/1 cnt_clr = 1'b1;
Tests: T56 T115 T97
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T5 T8 T9
191 1/1 state_d = StableSt;
Tests: T5 T8 T9
192 1/1 cnt_clr = 1'b1;
Tests: T5 T8 T9
193 1/1 event_detected_o = 1'b1;
Tests: T5 T8 T9
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T5 T8 T9
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T5 T8 T9
206 1/1 state_d = IdleSt;
Tests: T5 T9 T21
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T5 T8 T9
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
220 1/1 state_q <= IdleSt;
Tests: T1 T2 T4
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T2 T4
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T12 T13 T14
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T12 T13 T14
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T5 T9 T21
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T12 T5 T9
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T12 T5 T9
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
105 1/1 cnt_q <= '0;
Tests: T1 T2 T4
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T4
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T12 T13 T14
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T12 T13 T14
129 1/1 cnt_en = 1'b0;
Tests: T12 T13 T14
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T12 T13 T14
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T12 T13 T14
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T12 T13 T14
139
140 1/1 unique case (state_q)
Tests: T12 T13 T14
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T12 T13 T14
148 1/1 state_d = DebounceSt;
Tests: T5 T9 T21
149 1/1 cnt_en = 1'b1;
Tests: T5 T9 T21
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T5 T9 T21
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T5 T9 T21
163 1/1 state_d = IdleSt;
Tests: T21 T56
164 1/1 cnt_clr = 1'b1;
Tests: T21 T56
165 1/1 end else if (cnt_done) begin
Tests: T5 T9 T21
166 1/1 cnt_clr = 1'b1;
Tests: T5 T9 T39
167 1/1 if (trigger_active) begin
Tests: T5 T9 T39
168 1/1 state_d = DetectSt;
Tests: T5 T70 T54
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T9 T39 T116
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T5 T70 T54
182 1/1 cnt_en = 1'b1;
Tests: T5 T70 T54
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T5 T70 T54
186 1/1 state_d = IdleSt;
Tests: T117 T118 T119
187 1/1 cnt_clr = 1'b1;
Tests: T117 T118 T119
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T5 T70 T54
191 1/1 state_d = StableSt;
Tests: T5 T70 T54
192 1/1 cnt_clr = 1'b1;
Tests: T5 T70 T54
193 1/1 event_detected_o = 1'b1;
Tests: T5 T70 T54
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T5 T70 T54
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T5 T70 T54
206 1/1 state_d = IdleSt;
Tests: T5 T70 T54
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T5 T70 T54
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
220 1/1 state_q <= IdleSt;
Tests: T1 T2 T4
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T2 T4
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T11 T21 T30
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T11 T21 T30
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T7 T29
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
105 1/1 cnt_q <= '0;
Tests: T1 T2 T4
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T4
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T7 T29
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T7 T29
129 1/1 cnt_en = 1'b0;
Tests: T1 T7 T29
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T7 T29
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T7 T29
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T7 T29
139
140 1/1 unique case (state_q)
Tests: T1 T7 T29
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T7 T29
148 1/1 state_d = DebounceSt;
Tests: T1 T7 T29
149 1/1 cnt_en = 1'b1;
Tests: T1 T7 T29
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T7 T29
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T7 T29
163 1/1 state_d = IdleSt;
Tests: T21 T56
164 1/1 cnt_clr = 1'b1;
Tests: T21 T56
165 1/1 end else if (cnt_done) begin
Tests: T1 T7 T29
166 1/1 cnt_clr = 1'b1;
Tests: T1 T7 T29
167 1/1 if (trigger_active) begin
Tests: T1 T7 T29
168 1/1 state_d = DetectSt;
Tests: T1 T7 T29
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T21 T56 T120
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T7 T29
182 1/1 cnt_en = 1'b1;
Tests: T1 T7 T29
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T7 T29
186 1/1 state_d = IdleSt;
Tests: T11 T21 T30
187 1/1 cnt_clr = 1'b1;
Tests: T11 T21 T30
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T7 T29
191 1/1 state_d = StableSt;
Tests: T1 T7 T29
192 1/1 cnt_clr = 1'b1;
Tests: T1 T7 T29
193 1/1 event_detected_o = 1'b1;
Tests: T1 T7 T29
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T7 T29
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T7 T29
206 1/1 state_d = IdleSt;
Tests: T11 T21 T30
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T7 T29
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
220 1/1 state_q <= IdleSt;
Tests: T1 T2 T4
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T2 T4
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T2 T31
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T2 T4
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T2 T4
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T2 T4
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T31
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
105 1/1 cnt_q <= '0;
Tests: T1 T2 T4
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T4
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T2 T4
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T4
129 1/1 cnt_en = 1'b0;
Tests: T1 T2 T4
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T2 T4
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T2 T4
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T2 T4
139
140 1/1 unique case (state_q)
Tests: T1 T2 T4
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T2 T4
148 1/1 state_d = DebounceSt;
Tests: T1 T2 T31
149 1/1 cnt_en = 1'b1;
Tests: T1 T2 T31
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T2 T31
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T2 T31
163 1/1 state_d = IdleSt;
Tests: T21 T56
164 1/1 cnt_clr = 1'b1;
Tests: T21 T56
165 1/1 end else if (cnt_done) begin
Tests: T1 T2 T31
166 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T31
167 1/1 if (trigger_active) begin
Tests: T1 T2 T31
168 1/1 state_d = DetectSt;
Tests: T1 T2 T7
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T31 T6 T29
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T2 T7
182 1/1 cnt_en = 1'b1;
Tests: T1 T2 T7
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T2 T7
186 1/1 state_d = IdleSt;
Tests: T21 T42 T56
187 1/1 cnt_clr = 1'b1;
Tests: T21 T42 T56
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T2 T7
191 1/1 state_d = StableSt;
Tests: T1 T2 T7
192 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T7
193 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T7
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T2 T7
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T2 T7
206 1/1 state_d = IdleSt;
Tests: T1 T2 T7
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T7
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
220 1/1 state_q <= IdleSt;
Tests: T1 T2 T4
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T2 T4
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T31 |
| 1 | Covered | T1,T2,T4 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T31 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T31 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T31 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T7 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T31 |
| 1 | 0 | Covered | T28,T11,T51 |
| 1 | 1 | Covered | T1,T2,T31 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T7 |
| 0 | 1 | Covered | T42,T56,T121 |
| 1 | 0 | Covered | T21,T56 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T7 |
| 0 | 1 | Covered | T1,T2,T7 |
| 1 | 0 | Covered | T21,T56,T122 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T2,T7 |
| 1 | - | Covered | T1,T2,T7 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T4 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T4,T27,T8 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T4,T27,T8 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T4,T27,T8 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T27,T8 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T4,T27,T8 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T27,T8 |
| 0 | 1 | Covered | T45,T63,T123 |
| 1 | 0 | Covered | T56 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T27,T8 |
| 0 | 1 | Covered | T4,T27,T8 |
| 1 | 0 | Covered | T21,T56 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T4,T27,T8 |
| 1 | - | Covered | T4,T27,T8 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T11,T21,T30 |
| 1 | Covered | T1,T2,T4 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T7,T29 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T7,T29 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T7,T29 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T21,T30 |
| 1 | 0 | Covered | T11,T21,T30 |
| 1 | 1 | Covered | T1,T7,T29 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T7,T29 |
| 0 | 1 | Covered | T11,T21,T56 |
| 1 | 0 | Covered | T11,T21,T30 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T7,T29 |
| 0 | 1 | Covered | T11,T21,T30 |
| 1 | 0 | Covered | T11,T21,T124 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T7,T29 |
| 1 | - | Covered | T11,T21,T30 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T12,T13,T14 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T21 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T21 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T70,T54 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T9,T21 |
| 1 | 0 | Covered | T12,T13,T14 |
| 1 | 1 | Covered | T5,T9,T21 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T70,T54 |
| 0 | 1 | Covered | T117,T118,T119 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T70,T54 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T70,T54 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T4 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T8,T10,T51 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T8,T10,T51 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T8,T10,T51 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T8,T10 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T8,T10,T51 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T10,T51 |
| 0 | 1 | Covered | T115,T125,T126 |
| 1 | 0 | Covered | T56 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T10,T51 |
| 0 | 1 | Covered | T8,T10,T52 |
| 1 | 0 | Covered | T21,T56 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T8,T10,T51 |
| 1 | - | Covered | T8,T10,T52 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T12,T13,T14 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T12,T13,T14 |
| 1 | 1 | Covered | T12,T13,T14 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T21 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T21 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T39 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T9,T21 |
| 1 | 0 | Covered | T12,T13,T14 |
| 1 | 1 | Covered | T5,T9,T21 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T9,T39 |
| 0 | 1 | Covered | T97,T127,T128 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T9,T39 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T9,T39 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T12,T13 |
| 1 | Covered | T1,T2,T4 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T12,T13 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T21 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T21 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T5,T9,T39 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T9,T21 |
| 1 | 0 | Covered | T4,T12,T13 |
| 1 | 1 | Covered | T5,T9,T21 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T9,T54 |
| 0 | 1 | Covered | T39,T129,T130 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T9,T54 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T9,T54 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| | | |
| DebounceSt |
148 |
Covered |
T4,T27,T8 |
| DetectSt |
168 |
Covered |
T4,T27,T8 |
| IdleSt |
163 |
Covered |
T1,T2,T4 |
| StableSt |
191 |
Covered |
T4,T27,T8 |
| | | |
| DebounceSt->DetectSt |
168 |
Covered |
T4,T27,T8 |
| DebounceSt->IdleSt |
163 |
Covered |
T61,T56,T131 |
| DetectSt->IdleSt |
186 |
Covered |
T45,T39,T63 |
| DetectSt->StableSt |
191 |
Covered |
T4,T27,T8 |
| IdleSt->DebounceSt |
148 |
Covered |
T4,T27,T8 |
| StableSt->IdleSt |
206 |
Covered |
T4,T27,T8 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T27,T8 |
| 0 |
1 |
Covered |
T4,T27,T8 |
| 0 |
0 |
Covered |
T1,T2,T4 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T27,T8 |
| 0 |
Covered |
T1,T2,T4 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T4 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T27,T8 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T21,T56 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T4,T27,T8 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T61,T115,T125 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T4,T27,T8 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T45,T39,T63 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T4,T27,T8 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T2,T7 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T4,T27,T8 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T4,T27,T8 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T4 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T7,T5 |
| 0 |
1 |
Covered |
T1,T7,T5 |
| 0 |
0 |
Covered |
T1,T2,T4 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T7,T5 |
| 0 |
Covered |
T1,T2,T4 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T4 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T7,T5 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T12,T13,T14 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T21,T56 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T7,T5 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T9,T21,T39 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T7,T5 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T11,T21,T30 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T7,T5 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T7,T29 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T5,T21,T30 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T7,T5 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T4 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
19565 |
0 |
0 |
| T1 |
1018 |
4 |
0 |
0 |
| T2 |
972 |
2 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
2 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
4 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T11 |
0 |
10 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
18 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
4 |
0 |
0 |
| T28 |
0 |
1 |
0 |
0 |
| T29 |
456 |
3 |
0 |
0 |
| T31 |
448 |
1 |
0 |
0 |
| T56 |
0 |
17 |
0 |
0 |
| T57 |
443 |
1 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T59 |
0 |
4 |
0 |
0 |
| T61 |
0 |
3 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
0 |
4 |
0 |
0 |
| T64 |
0 |
4 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
4 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
2 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
1902383 |
0 |
0 |
| T1 |
1018 |
46 |
0 |
0 |
| T2 |
972 |
25 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
56 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
46 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T11 |
0 |
210 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
500 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
86 |
0 |
0 |
| T28 |
0 |
20 |
0 |
0 |
| T29 |
456 |
41 |
0 |
0 |
| T31 |
448 |
20 |
0 |
0 |
| T56 |
0 |
680 |
0 |
0 |
| T57 |
443 |
20 |
0 |
0 |
| T58 |
0 |
55 |
0 |
0 |
| T59 |
0 |
46 |
0 |
0 |
| T61 |
0 |
74 |
0 |
0 |
| T62 |
0 |
73 |
0 |
0 |
| T63 |
0 |
174 |
0 |
0 |
| T64 |
0 |
144 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
46 |
0 |
0 |
| T131 |
0 |
42 |
0 |
0 |
| T132 |
0 |
25 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
165466535 |
0 |
0 |
| T1 |
13234 |
2804 |
0 |
0 |
| T2 |
12636 |
2208 |
0 |
0 |
| T3 |
12506 |
2074 |
0 |
0 |
| T4 |
17316 |
6888 |
0 |
0 |
| T12 |
19422 |
8996 |
0 |
0 |
| T13 |
13598 |
3172 |
0 |
0 |
| T14 |
10712 |
286 |
0 |
0 |
| T15 |
10998 |
572 |
0 |
0 |
| T16 |
26988 |
16562 |
0 |
0 |
| T17 |
11076 |
650 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
2164 |
0 |
0 |
| T11 |
30017 |
3 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T41 |
33129 |
0 |
0 |
0 |
| T42 |
10965 |
8 |
0 |
0 |
| T52 |
494 |
0 |
0 |
0 |
| T54 |
8961 |
0 |
0 |
0 |
| T56 |
7997 |
1 |
0 |
0 |
| T63 |
765 |
1 |
0 |
0 |
| T73 |
148631 |
0 |
0 |
0 |
| T79 |
493 |
0 |
0 |
0 |
| T80 |
497 |
0 |
0 |
0 |
| T89 |
0 |
12 |
0 |
0 |
| T90 |
0 |
28 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T121 |
0 |
4 |
0 |
0 |
| T123 |
0 |
1 |
0 |
0 |
| T134 |
0 |
14 |
0 |
0 |
| T135 |
0 |
1 |
0 |
0 |
| T136 |
0 |
4 |
0 |
0 |
| T137 |
0 |
1 |
0 |
0 |
| T138 |
0 |
6 |
0 |
0 |
| T139 |
0 |
4 |
0 |
0 |
| T140 |
0 |
3 |
0 |
0 |
| T141 |
0 |
1 |
0 |
0 |
| T142 |
0 |
1 |
0 |
0 |
| T143 |
0 |
6 |
0 |
0 |
| T144 |
0 |
8 |
0 |
0 |
| T145 |
522 |
0 |
0 |
0 |
| T146 |
401 |
0 |
0 |
0 |
| T147 |
1460 |
0 |
0 |
0 |
| T148 |
422 |
0 |
0 |
0 |
| T149 |
419 |
0 |
0 |
0 |
| T150 |
507 |
0 |
0 |
0 |
| T151 |
710 |
0 |
0 |
0 |
| T152 |
4402 |
0 |
0 |
0 |
| T153 |
403 |
0 |
0 |
0 |
| T154 |
424 |
0 |
0 |
0 |
| T155 |
525 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
1900160 |
0 |
0 |
| T1 |
1018 |
86 |
0 |
0 |
| T2 |
972 |
3 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
5 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
84 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
464 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
18 |
0 |
0 |
| T29 |
456 |
31 |
0 |
0 |
| T30 |
0 |
154 |
0 |
0 |
| T31 |
448 |
0 |
0 |
0 |
| T32 |
0 |
36 |
0 |
0 |
| T40 |
0 |
3260 |
0 |
0 |
| T56 |
0 |
575 |
0 |
0 |
| T57 |
443 |
0 |
0 |
0 |
| T58 |
0 |
13 |
0 |
0 |
| T59 |
0 |
86 |
0 |
0 |
| T61 |
0 |
6 |
0 |
0 |
| T62 |
0 |
8 |
0 |
0 |
| T63 |
0 |
7 |
0 |
0 |
| T64 |
0 |
14 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
82 |
0 |
0 |
| T132 |
0 |
3 |
0 |
0 |
| T133 |
0 |
7 |
0 |
0 |
| T156 |
0 |
10 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
6322 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
972 |
1 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
1 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
7 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
2 |
0 |
0 |
| T29 |
456 |
1 |
0 |
0 |
| T30 |
0 |
21 |
0 |
0 |
| T31 |
448 |
0 |
0 |
0 |
| T32 |
0 |
5 |
0 |
0 |
| T40 |
0 |
32 |
0 |
0 |
| T56 |
0 |
6 |
0 |
0 |
| T57 |
443 |
0 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T132 |
0 |
1 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T156 |
0 |
2 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
155033848 |
0 |
0 |
| T1 |
13234 |
2622 |
0 |
0 |
| T2 |
12636 |
2129 |
0 |
0 |
| T3 |
12506 |
1548 |
0 |
0 |
| T4 |
17316 |
6786 |
0 |
0 |
| T12 |
19422 |
8996 |
0 |
0 |
| T13 |
13598 |
3172 |
0 |
0 |
| T14 |
10712 |
286 |
0 |
0 |
| T15 |
10998 |
572 |
0 |
0 |
| T16 |
26988 |
16562 |
0 |
0 |
| T17 |
11076 |
650 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
155091534 |
0 |
0 |
| T1 |
13234 |
2646 |
0 |
0 |
| T2 |
12636 |
2154 |
0 |
0 |
| T3 |
12506 |
1567 |
0 |
0 |
| T4 |
17316 |
6812 |
0 |
0 |
| T12 |
19422 |
9022 |
0 |
0 |
| T13 |
13598 |
3198 |
0 |
0 |
| T14 |
10712 |
312 |
0 |
0 |
| T15 |
10998 |
598 |
0 |
0 |
| T16 |
26988 |
16588 |
0 |
0 |
| T17 |
11076 |
676 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
10059 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
972 |
1 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
1 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T11 |
0 |
5 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
10 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
2 |
0 |
0 |
| T28 |
0 |
1 |
0 |
0 |
| T29 |
456 |
2 |
0 |
0 |
| T31 |
448 |
1 |
0 |
0 |
| T56 |
0 |
10 |
0 |
0 |
| T57 |
443 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
9535 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
972 |
1 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
1 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T11 |
0 |
5 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
10 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
2 |
0 |
0 |
| T29 |
456 |
1 |
0 |
0 |
| T31 |
448 |
0 |
0 |
0 |
| T32 |
0 |
5 |
0 |
0 |
| T40 |
0 |
32 |
0 |
0 |
| T42 |
0 |
8 |
0 |
0 |
| T57 |
443 |
0 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T132 |
0 |
1 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T156 |
0 |
2 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
6322 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
972 |
1 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
1 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
7 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
2 |
0 |
0 |
| T29 |
456 |
1 |
0 |
0 |
| T30 |
0 |
21 |
0 |
0 |
| T31 |
448 |
0 |
0 |
0 |
| T32 |
0 |
5 |
0 |
0 |
| T40 |
0 |
32 |
0 |
0 |
| T56 |
0 |
6 |
0 |
0 |
| T57 |
443 |
0 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T132 |
0 |
1 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T156 |
0 |
2 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
6322 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
972 |
1 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
1 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
7 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
2 |
0 |
0 |
| T29 |
456 |
1 |
0 |
0 |
| T30 |
0 |
21 |
0 |
0 |
| T31 |
448 |
0 |
0 |
0 |
| T32 |
0 |
5 |
0 |
0 |
| T40 |
0 |
32 |
0 |
0 |
| T56 |
0 |
6 |
0 |
0 |
| T57 |
443 |
0 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T132 |
0 |
1 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T156 |
0 |
2 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
182366236 |
1892750 |
0 |
0 |
| T1 |
1018 |
83 |
0 |
0 |
| T2 |
972 |
2 |
0 |
0 |
| T3 |
1443 |
0 |
0 |
0 |
| T4 |
1998 |
4 |
0 |
0 |
| T6 |
7579 |
0 |
0 |
0 |
| T7 |
0 |
81 |
0 |
0 |
| T8 |
627 |
0 |
0 |
0 |
| T12 |
2241 |
0 |
0 |
0 |
| T13 |
1569 |
0 |
0 |
0 |
| T14 |
1236 |
0 |
0 |
0 |
| T15 |
1269 |
0 |
0 |
0 |
| T16 |
3114 |
0 |
0 |
0 |
| T17 |
1278 |
0 |
0 |
0 |
| T21 |
0 |
457 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
16 |
0 |
0 |
| T29 |
456 |
29 |
0 |
0 |
| T30 |
0 |
133 |
0 |
0 |
| T31 |
448 |
0 |
0 |
0 |
| T32 |
0 |
31 |
0 |
0 |
| T40 |
0 |
3222 |
0 |
0 |
| T56 |
0 |
569 |
0 |
0 |
| T57 |
443 |
0 |
0 |
0 |
| T58 |
0 |
11 |
0 |
0 |
| T59 |
0 |
83 |
0 |
0 |
| T61 |
0 |
5 |
0 |
0 |
| T62 |
0 |
7 |
0 |
0 |
| T63 |
0 |
6 |
0 |
0 |
| T64 |
0 |
12 |
0 |
0 |
| T65 |
522 |
0 |
0 |
0 |
| T66 |
406 |
0 |
0 |
0 |
| T67 |
424 |
0 |
0 |
0 |
| T68 |
818 |
0 |
0 |
0 |
| T69 |
615 |
0 |
0 |
0 |
| T87 |
0 |
79 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
6 |
0 |
0 |
| T156 |
0 |
8 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
63126774 |
52743 |
0 |
0 |
| T1 |
1527 |
3 |
0 |
0 |
| T2 |
1458 |
3 |
0 |
0 |
| T3 |
4329 |
2 |
0 |
0 |
| T4 |
3996 |
9 |
0 |
0 |
| T5 |
0 |
8 |
0 |
0 |
| T7 |
0 |
3 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T12 |
5229 |
20 |
0 |
0 |
| T13 |
4707 |
48 |
0 |
0 |
| T14 |
3708 |
12 |
0 |
0 |
| T15 |
3807 |
23 |
0 |
0 |
| T16 |
9342 |
5 |
0 |
0 |
| T17 |
3834 |
17 |
0 |
0 |
| T22 |
2946 |
58 |
0 |
0 |
| T23 |
994 |
57 |
0 |
0 |
| T25 |
0 |
29 |
0 |
0 |
| T26 |
0 |
12 |
0 |
0 |
| T31 |
2688 |
3 |
0 |
0 |
| T65 |
0 |
11 |
0 |
0 |
| T74 |
1209 |
0 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
35070430 |
31836240 |
0 |
0 |
| T1 |
2545 |
545 |
0 |
0 |
| T2 |
2430 |
430 |
0 |
0 |
| T3 |
2405 |
405 |
0 |
0 |
| T4 |
3330 |
1330 |
0 |
0 |
| T12 |
3735 |
1735 |
0 |
0 |
| T13 |
2615 |
615 |
0 |
0 |
| T14 |
2060 |
60 |
0 |
0 |
| T15 |
2115 |
115 |
0 |
0 |
| T16 |
5190 |
3190 |
0 |
0 |
| T17 |
2130 |
130 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
119239462 |
108243216 |
0 |
0 |
| T1 |
8653 |
1853 |
0 |
0 |
| T2 |
8262 |
1462 |
0 |
0 |
| T3 |
8177 |
1377 |
0 |
0 |
| T4 |
11322 |
4522 |
0 |
0 |
| T12 |
12699 |
5899 |
0 |
0 |
| T13 |
8891 |
2091 |
0 |
0 |
| T14 |
7004 |
204 |
0 |
0 |
| T15 |
7191 |
391 |
0 |
0 |
| T16 |
17646 |
10846 |
0 |
0 |
| T17 |
7242 |
442 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
63126774 |
57305232 |
0 |
0 |
| T1 |
4581 |
981 |
0 |
0 |
| T2 |
4374 |
774 |
0 |
0 |
| T3 |
4329 |
729 |
0 |
0 |
| T4 |
5994 |
2394 |
0 |
0 |
| T12 |
6723 |
3123 |
0 |
0 |
| T13 |
4707 |
1107 |
0 |
0 |
| T14 |
3708 |
108 |
0 |
0 |
| T15 |
3807 |
207 |
0 |
0 |
| T16 |
9342 |
5742 |
0 |
0 |
| T17 |
3834 |
234 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
161323978 |
5006 |
0 |
0 |
| T1 |
509 |
1 |
0 |
0 |
| T2 |
486 |
1 |
0 |
0 |
| T3 |
962 |
0 |
0 |
0 |
| T4 |
1332 |
1 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T12 |
1494 |
0 |
0 |
0 |
| T13 |
1046 |
0 |
0 |
0 |
| T14 |
824 |
0 |
0 |
0 |
| T15 |
846 |
0 |
0 |
0 |
| T16 |
2076 |
0 |
0 |
0 |
| T17 |
852 |
0 |
0 |
0 |
| T21 |
7856 |
5 |
0 |
0 |
| T22 |
491 |
0 |
0 |
0 |
| T27 |
0 |
2 |
0 |
0 |
| T30 |
0 |
21 |
0 |
0 |
| T31 |
448 |
0 |
0 |
0 |
| T32 |
20109 |
5 |
0 |
0 |
| T40 |
0 |
26 |
0 |
0 |
| T55 |
0 |
3 |
0 |
0 |
| T56 |
0 |
6 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T72 |
1746 |
0 |
0 |
0 |
| T77 |
524 |
0 |
0 |
0 |
| T87 |
0 |
1 |
0 |
0 |
| T132 |
0 |
1 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T156 |
0 |
2 |
0 |
0 |
| T157 |
427 |
0 |
0 |
0 |
| T158 |
403 |
0 |
0 |
0 |
| T159 |
507 |
0 |
0 |
0 |
| T160 |
524 |
0 |
0 |
0 |
| T161 |
422 |
0 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
21042258 |
1739232 |
0 |
0 |
| T5 |
2067 |
328 |
0 |
0 |
| T6 |
22737 |
0 |
0 |
0 |
| T8 |
1881 |
0 |
0 |
0 |
| T9 |
0 |
432 |
0 |
0 |
| T26 |
1503 |
0 |
0 |
0 |
| T27 |
1935 |
0 |
0 |
0 |
| T29 |
1368 |
0 |
0 |
0 |
| T39 |
0 |
47 |
0 |
0 |
| T54 |
0 |
1168 |
0 |
0 |
| T55 |
0 |
619 |
0 |
0 |
| T65 |
1566 |
0 |
0 |
0 |
| T66 |
1218 |
0 |
0 |
0 |
| T67 |
1272 |
0 |
0 |
0 |
| T68 |
2454 |
0 |
0 |
0 |
| T70 |
0 |
193 |
0 |
0 |
| T96 |
0 |
111 |
0 |
0 |
| T97 |
0 |
214 |
0 |
0 |
| T100 |
0 |
361 |
0 |
0 |
| T129 |
0 |
436 |
0 |
0 |
| T162 |
0 |
974 |
0 |
0 |
| T163 |
0 |
446 |
0 |
0 |
| T164 |
0 |
125 |
0 |
0 |
| T165 |
0 |
205 |
0 |
0 |
