Module Definition
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Module : sysrst_ctrl_detect
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.35 100.00 96.30 100.00 95.45 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 90.31 93.48 90.91 83.33 90.48 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 90.39 93.48 90.91 83.33 90.48 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 90.39 93.48 90.91 83.33 90.48 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 90.39 93.48 90.91 83.33 90.48 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 91.69 95.65 90.91 83.33 95.24 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 91.69 95.65 90.91 83.33 95.24 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 91.69 95.65 90.91 83.33 95.24 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 91.69 95.65 90.91 83.33 95.24 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 91.78 95.65 90.91 83.33 95.24 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 91.78 95.65 90.91 83.33 95.24 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 91.78 95.65 90.91 83.33 95.24 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 91.78 95.65 90.91 83.33 95.24 93.75
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present 98.75 100.00 93.75 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb 98.95 100.00 94.74 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open 98.95 100.00 94.74 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect 99.09 100.00 95.45 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 99.09 100.00 95.45 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 99.09 100.00 95.45 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
SCORELINE
99.09 100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORELINE
98.95 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORELINE
91.78 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORELINE
91.78 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORELINE
91.78 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORELINE
90.39 93.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORELINE
90.39 93.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORELINE
90.39 93.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORELINE
91.78 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00


57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T5 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T16 T3 T6 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T16 T3 T6 
149        1/1                    cnt_en = 1'b1;
           Tests:       T16 T3 T6 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T16 T3 T6 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T16 T3 T6 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T16 T3 T6 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T3 T6 
167        1/1                    if (trigger_active) begin
           Tests:       T16 T3 T6 
168        1/1                      state_d = DetectSt;
           Tests:       T16 T3 T6 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T19 T71 T72 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T16 T3 T6 
182        1/1                  cnt_en = 1'b1;
           Tests:       T16 T3 T6 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T16 T3 T6 
186        1/1                    state_d = IdleSt;
           Tests:       T6 T96 T97 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T96 T97 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T16 T3 T27 
191        1/1                      state_d = StableSt;
           Tests:       T16 T3 T27 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T16 T3 T27 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T16 T3 T27 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T16 T3 T27 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T16 T3 T27 
206        1/1                    state_d = IdleSt;
           Tests:       T16 T11 T27 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T16 T3 T27 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 
Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
SCORELINE
98.95 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORELINE
91.69 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORELINE
90.31 93.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORELINE
99.09 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORELINE
91.69 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORELINE
91.69 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORELINE
99.09 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORELINE
91.69 95.65
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00


59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T5 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T11 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T11 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T11 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T11 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T11 T12 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T11 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T11 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T11 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T11 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T38 T69 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T11 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T11 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T11 T12 
186        1/1                    state_d = IdleSt;
           Tests:       T38 T69 T71 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T38 T69 T71 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T11 T12 
191        1/1                      state_d = StableSt;
           Tests:       T6 T11 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T11 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T11 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T11 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T11 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T6 T11 T12 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T11 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 
Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
SCORELINE
98.75 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00


59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T5 T13 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T12 T19 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T12 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T12 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T12 T19 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T12 T19 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T12 T19 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T12 T19 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T12 T19 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T19 T38 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T19 T38 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T19 T38 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T73 T97 T98 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T19 T38 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T19 T38 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T19 T38 
186        1/1                    state_d = IdleSt;
           Tests:       T99 T100 T101 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T99 T100 T101 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T19 T38 
191        1/1                      state_d = StableSt;
           Tests:       T6 T19 T38 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T19 T38 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T19 T38 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T19 T38 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T19 T38 
206        1/1                    state_d = IdleSt;
           Tests:       T6 T19 T38 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T19 T38 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 
Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00


59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T12 T20 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T12 T20 T30 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T8 T29 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T8 T29 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T8 T29 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T8 T29 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T8 T29 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T8 T29 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T8 T29 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T8 T29 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T8 T29 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T8 T29 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T8 T29 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T29 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T8 T29 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T8 T29 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T8 T29 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T8 T29 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T8 T29 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T12 T55 T102 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T8 T29 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T29 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T8 T29 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T20 T30 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T20 T30 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T8 T29 
191        1/1                      state_d = StableSt;
           Tests:       T1 T8 T29 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T8 T29 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T8 T29 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T8 T29 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T8 T29 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T20 T42 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T8 T29 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 
Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORELINE
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00


59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T2 T8 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T2 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T2 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T2 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T2 T8 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T2 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T8 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T2 T8 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T2 T8 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T29 T56 T57 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T2 T8 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T8 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T2 T8 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T55 T40 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 T40 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T2 T8 
191        1/1                      state_d = StableSt;
           Tests:       T1 T2 T8 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T2 T8 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T2 T8 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T2 T8 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T2 T8 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T8 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T2 T8 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 
Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

TotalCoveredPercent
Conditions2222100.00
Logical2222100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T8
1CoveredT1,T4,T5 

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T8
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T8 

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T8 

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T8 

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T8
10CoveredT17,T87,T103
11CoveredT1,T2,T8 

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T8
01CoveredT40,T43,T104
10CoveredT12,T55 

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T8
01CoveredT1,T2,T8
10CoveredT12,T20,T55 

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT1,T2,T8
1-CoveredT1,T2,T8
Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
99.09 95.45
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORECOND
91.78 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORECOND
91.78 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORECOND
91.78 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORECOND
90.39 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORECOND
90.39 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORECOND
90.39 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORECOND
91.78 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

TotalCoveredPercent
Conditions222195.45
Logical222195.45
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T5 

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT16,T3,T7 

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT16,T3,T7 

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT16,T3,T7 

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T3,T7
10CoveredT1,T4,T5
11CoveredT16,T3,T7 

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T3,T7
01CoveredT96,T105,T106
10Not Covered 

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT16,T3,T7
01CoveredT16,T11,T27
10CoveredT12 

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT16,T3,T7
1-CoveredT16,T11,T27
Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORECOND
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT12,T20,T30
1CoveredT1,T4,T5 

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T8,T29 

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T8,T29 

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T8,T29 

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT12,T20,T30
10CoveredT12,T20,T42
11CoveredT1,T8,T29 

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT1,T8,T29
01CoveredT12,T20,T30
10CoveredT12,T20,T55 

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T8,T29
01CoveredT12,T20,T42
10CoveredT12,T55,T107 

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT1,T8,T29
1-CoveredT12,T20,T42
Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
98.75 93.75
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT4,T5,T13 

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T19,T38 

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T12,T19
10CoveredT4,T5,T13
11CoveredT6,T12,T19 

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T19,T38
01CoveredT99,T100,T101
10Not Covered 

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT6,T19,T38
01Unreachable
10CoveredT6,T19,T38
Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
91.69 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORECOND
90.31 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORECOND
99.09 95.45
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORECOND
91.69 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORECOND
91.69 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORECOND
99.09 95.45
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORECOND
91.69 90.91
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

TotalCoveredPercent
Conditions222195.45
Logical222195.45
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T4,T5 

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT3,T7,T11 

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT3,T7,T11 

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT3,T11,T12 

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T7,T11
10CoveredT1,T4,T5
11CoveredT3,T7,T11 

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT3,T11,T12
01CoveredT54,T50
10Not Covered 

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T11,T12
01CoveredT11,T45,T49
10CoveredT12 

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T11,T12
1-CoveredT11,T45,T49
Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
98.95 94.74
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT4,T5,T13 

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT4,T5,T13
11CoveredT4,T5,T13 

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T19,T38 

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T12,T19
10CoveredT4,T5,T13
11CoveredT6,T12,T19 

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T19,T38
01CoveredT38,T69,T71
10Not Covered 

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT6,T19,T38
01Unreachable
10CoveredT6,T19,T38
Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
98.95 94.74
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT4,T5,T13
1CoveredT1,T4,T5 

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT4,T5,T13
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T12,T19 

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT6,T19,T38 

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T12,T19
10CoveredT4,T5,T13
11CoveredT6,T12,T19 

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT19,T38,T69
01CoveredT6,T97,T108
10Not Covered 

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT19,T38,T69
01Unreachable
10CoveredT19,T38,T69
FSM Coverage for Module : sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T16,T3,T7
DetectSt 168 Covered T16,T3,T7
IdleSt 163 Covered T1,T4,T5
StableSt 191 Covered T16,T3,T7


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T16,T3,T7
DebounceSt->IdleSt 163 Covered T11,T12,T19
DetectSt->IdleSt 186 Covered T6,T12,T20
DetectSt->StableSt 191 Covered T16,T3,T7
IdleSt->DebounceSt 148 Covered T16,T3,T7
StableSt->IdleSt 206 Covered T16,T11,T27


Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
SCOREBRANCH
99.09 100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCOREBRANCH
91.78 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
91.78 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
91.78 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
90.39 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
90.39 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
90.39 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
91.78 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
98.95 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCOREBRANCH
98.95 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCOREBRANCH
91.69 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
90.31 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
99.09 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
91.69 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
91.69 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
99.09 100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
91.69 95.24
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Line No.TotalCoveredPercent
Branches 23 22 95.65
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00
IF 69 2 2 100.00 



92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>

Branches:
-1--2-StatusTests
1 - Covered T16,T3,T7
0 1 Covered T16,T3,T7
0 0 Covered T1,T4,T5 



99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>

Branches:
-1-StatusTests
1 Covered T16,T3,T7
0 Covered T1,T4,T5 



104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5 



140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T16,T3,T7
IdleSt 0 - - - - - - Covered T1,T4,T5
DebounceSt - 1 - - - - - Covered T12,T55
DebounceSt - 0 1 1 - - - Covered T16,T3,T7
DebounceSt - 0 1 0 - - - Covered T11,T19,T71
DebounceSt - 0 0 - - - - Covered T16,T3,T7
DetectSt - - - - 1 - - Covered T6,T12,T38
DetectSt - - - - 0 1 - Covered T16,T3,T7
DetectSt - - - - 0 0 - Covered T1,T2,T8
StableSt - - - - - - 1 Covered T16,T11,T27
StableSt - - - - - - 0 Covered T16,T3,T7
default - - - - - - - Not Covered 



219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5 



69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
SCOREBRANCH
98.75 100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCOREBRANCH
100.00 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00 



92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T6,T8
0 1 Covered T1,T6,T8
0 0 Covered T1,T4,T5 



99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>

Branches:
-1-StatusTests
1 Covered T1,T6,T8
0 Covered T1,T4,T5 



104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5 



140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T1,T6,T8
IdleSt 0 - - - - - - Covered T4,T5,T13
DebounceSt - 1 - - - - - Covered T12,T55
DebounceSt - 0 1 1 - - - Covered T1,T6,T8
DebounceSt - 0 1 0 - - - Covered T12,T73,T55
DebounceSt - 0 0 - - - - Covered T1,T6,T8
DetectSt - - - - 1 - - Covered T12,T20,T30
DetectSt - - - - 0 1 - Covered T1,T6,T8
DetectSt - - - - 0 0 - Covered T1,T8,T29
StableSt - - - - - - 1 Covered T6,T12,T20
StableSt - - - - - - 0 Covered T1,T6,T8
default - - - - - - - Not Covered 



219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5

Assert Coverage for Module : sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 19 19 100.00 19 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 19 19 100.00 19 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 191490572 16973 0 0
CntIncr_A 191490572 1623168 0 0
CntNoWrap_A 191490572 179217771 0 0
DetectStDropOut_A 191490572 1708 0 0
DetectedOut_A 191490572 1585145 0 0
DetectedPulseOut_A 191490572 5497 0 0
DisabledIdleSt_A 191490572 170006383 0 0
DisabledNoDetection_A 191490572 170050908 0 0
EnterDebounceSt_A 191490572 8723 0 0
EnterDetectSt_A 191490572 8255 0 0
EnterStableSt_A 191490572 5497 0 0
PulseIsPulse_A 191490572 5497 0 0
StayInStableSt 191490572 1579018 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 66285198 40364 0 0
gen_high_event_sva.HighLevelEvent_A 36825110 34477515 0 0
gen_high_level_sva.HighLevelEvent_A 125205374 117223551 0 0
gen_low_level_sva.LowLevelEvent_A 66285198 62059527 0 0
gen_not_sticky_sva.StableStDropOut_A 169395506 4691 0 0
gen_sticky_sva.StableStDropOut_A 22095066 2383756 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 16973 0 0
T1 1010 4 0 0
T2 966 2 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 4 0 0
T9 484 2 0 0
T10 0 2 0 0
T12 7268 26 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 4 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T20 0 52 0 0
T26 502 0 0 0
T27 0 2 0 0
T28 0 2 0 0
T29 0 3 0 0
T56 0 3 0 0
T57 0 1 0 0
T58 0 2 0 0
T59 0 2 0 0
T60 0 2 0 0
T61 0 6 0 0
T62 0 3 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T91 0 2 0 0
T109 0 2 0 0
T110 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 1623168 0 0
T1 1010 46 0 0
T2 966 25 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 46 0 0
T9 484 25 0 0
T10 0 25 0 0
T12 7268 683 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 99 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T20 0 1234 0 0
T26 502 0 0 0
T27 0 24 0 0
T28 0 50 0 0
T29 0 41 0 0
T56 0 41 0 0
T57 0 20 0 0
T58 0 28 0 0
T59 0 19 0 0
T60 0 78 0 0
T61 0 143 0 0
T62 0 173 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T91 0 21 0 0
T109 0 25 0 0
T110 0 82 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 179217771 0 0
T1 13130 2700 0 0
T2 12558 2130 0 0
T4 11622 1196 0 0
T5 12896 2470 0 0
T13 10972 546 0 0
T14 13598 3172 0 0
T15 18408 7982 0 0
T16 17524 7094 0 0
T17 39572 1066 0 0
T18 12922 2496 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 1708 0 0
T12 7268 1 0 0
T20 0 4 0 0
T30 0 12 0 0
T31 0 8 0 0
T55 0 1 0 0
T93 5318 12 0 0
T94 0 9 0 0
T96 622 1 0 0
T102 0 20 0 0
T105 0 1 0 0
T106 0 1 0 0
T111 14718 3 0 0
T112 0 4 0 0
T113 0 3 0 0
T114 0 5 0 0
T115 0 7 0 0
T116 0 2 0 0
T117 0 5 0 0
T118 0 4 0 0
T119 0 3 0 0
T120 0 10 0 0
T121 1467 0 0 0
T122 493 0 0 0
T123 522 0 0 0
T124 628 0 0 0
T125 8402 0 0 0
T126 412 0 0 0
T127 500 0 0 0
T128 403 0 0 0
T129 13390 0 0 0
T130 425 0 0 0
T131 507 0 0 0
T132 3178 0 0 0
T133 31189 0 0 0
T134 490 0 0 0
T135 39063 0 0 0
T136 1871 0 0 0
T137 413 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 1585145 0 0
T1 1010 83 0 0
T2 966 3 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 84 0 0
T9 484 3 0 0
T10 0 3 0 0
T12 7268 469 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 8 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T26 502 0 0 0
T27 0 4 0 0
T28 0 11 0 0
T29 0 45 0 0
T40 0 11 0 0
T55 0 463 0 0
T56 0 28 0 0
T58 0 3 0 0
T59 0 3 0 0
T60 0 7 0 0
T61 0 27 0 0
T62 0 7 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T92 0 1359 0 0
T109 0 4 0 0
T110 0 7 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 5497 0 0
T1 1010 2 0 0
T2 966 1 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 2 0 0
T9 484 1 0 0
T10 0 1 0 0
T12 7268 7 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 2 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T26 502 0 0 0
T27 0 1 0 0
T28 0 1 0 0
T29 0 1 0 0
T40 0 1 0 0
T55 0 6 0 0
T56 0 1 0 0
T58 0 1 0 0
T59 0 1 0 0
T60 0 1 0 0
T61 0 3 0 0
T62 0 1 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T92 0 20 0 0
T109 0 1 0 0
T110 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 170006383 0 0
T1 13130 2524 0 0
T2 12558 2054 0 0
T4 11622 1196 0 0
T5 12896 2470 0 0
T13 10972 546 0 0
T14 13598 3172 0 0
T15 18408 7982 0 0
T16 17524 6923 0 0
T17 39572 1066 0 0
T18 12922 2496 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 170050908 0 0
T1 13130 2548 0 0
T2 12558 2079 0 0
T4 11622 1222 0 0
T5 12896 2496 0 0
T13 10972 572 0 0
T14 13598 3198 0 0
T15 18408 8008 0 0
T16 17524 6948 0 0
T17 39572 1222 0 0
T18 12922 2522 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 8723 0 0
T1 1010 2 0 0
T2 966 1 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 2 0 0
T9 484 1 0 0
T10 0 1 0 0
T12 7268 15 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 2 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T20 0 26 0 0
T26 502 0 0 0
T27 0 1 0 0
T28 0 1 0 0
T29 0 2 0 0
T56 0 2 0 0
T57 0 1 0 0
T58 0 1 0 0
T59 0 1 0 0
T60 0 1 0 0
T61 0 3 0 0
T62 0 2 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T91 0 1 0 0
T109 0 1 0 0
T110 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 8255 0 0
T1 1010 2 0 0
T2 966 1 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 2 0 0
T9 484 1 0 0
T10 0 1 0 0
T12 7268 11 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 2 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T26 502 0 0 0
T27 0 1 0 0
T28 0 1 0 0
T29 0 1 0 0
T40 0 1 0 0
T55 0 3 0 0
T56 0 1 0 0
T58 0 1 0 0
T59 0 1 0 0
T60 0 1 0 0
T61 0 3 0 0
T62 0 1 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T92 0 2 0 0
T109 0 1 0 0
T110 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 5497 0 0
T1 1010 2 0 0
T2 966 1 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 2 0 0
T9 484 1 0 0
T10 0 1 0 0
T12 7268 7 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 2 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T26 502 0 0 0
T27 0 1 0 0
T28 0 1 0 0
T29 0 1 0 0
T40 0 1 0 0
T55 0 6 0 0
T56 0 1 0 0
T58 0 1 0 0
T59 0 1 0 0
T60 0 1 0 0
T61 0 3 0 0
T62 0 1 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T92 0 20 0 0
T109 0 1 0 0
T110 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 5497 0 0
T1 1010 2 0 0
T2 966 1 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 2 0 0
T9 484 1 0 0
T10 0 1 0 0
T12 7268 7 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 2 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T26 502 0 0 0
T27 0 1 0 0
T28 0 1 0 0
T29 0 1 0 0
T40 0 1 0 0
T55 0 6 0 0
T56 0 1 0 0
T58 0 1 0 0
T59 0 1 0 0
T60 0 1 0 0
T61 0 3 0 0
T62 0 1 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T92 0 20 0 0
T109 0 1 0 0
T110 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 191490572 1579018 0 0
T1 1010 80 0 0
T2 966 2 0 0
T3 709 0 0 0
T4 894 0 0 0
T5 992 0 0 0
T6 1143 0 0 0
T8 507 81 0 0
T9 484 2 0 0
T10 0 2 0 0
T12 7268 462 0 0
T13 844 0 0 0
T14 1046 0 0 0
T15 1416 0 0 0
T16 2022 6 0 0
T17 4566 0 0 0
T18 1491 0 0 0
T26 502 0 0 0
T27 0 3 0 0
T28 0 10 0 0
T29 0 43 0 0
T40 0 10 0 0
T55 0 457 0 0
T56 0 26 0 0
T58 0 2 0 0
T59 0 2 0 0
T60 0 6 0 0
T61 0 24 0 0
T62 0 6 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T92 0 1339 0 0
T109 0 3 0 0
T110 0 5 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 66285198 40364 0 0
T1 1515 3 0 0
T2 4347 3 0 0
T3 4254 8 0 0
T4 4023 49 0 0
T5 4464 58 0 0
T6 0 28 0 0
T8 0 1 0 0
T13 3798 18 0 0
T14 4707 42 0 0
T15 6372 4 0 0
T16 6066 9 0 0
T17 13698 8 0 0
T18 4473 60 0 0
T26 0 41 0 0
T65 0 9 0 0
T74 0 9 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36825110 34477515 0 0
T1 2525 525 0 0
T2 2415 415 0 0
T4 2235 235 0 0
T5 2480 480 0 0
T13 2110 110 0 0
T14 2615 615 0 0
T15 3540 1540 0 0
T16 3370 1370 0 0
T17 7610 235 0 0
T18 2485 485 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 125205374 117223551 0 0
T1 8585 1785 0 0
T2 8211 1411 0 0
T4 7599 799 0 0
T5 8432 1632 0 0
T13 7174 374 0 0
T14 8891 2091 0 0
T15 12036 5236 0 0
T16 11458 4658 0 0
T17 25874 799 0 0
T18 8449 1649 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 66285198 62059527 0 0
T1 4545 945 0 0
T2 4347 747 0 0
T4 4023 423 0 0
T5 4464 864 0 0
T13 3798 198 0 0
T14 4707 1107 0 0
T15 6372 2772 0 0
T16 6066 2466 0 0
T17 13698 423 0 0
T18 4473 873 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169395506 4691 0 0
T1 505 1 0 0
T2 483 1 0 0
T3 709 0 0 0
T4 447 0 0 0
T5 496 0 0 0
T6 1143 0 0 0
T8 507 1 0 0
T9 484 1 0 0
T10 0 1 0 0
T12 7268 5 0 0
T13 422 0 0 0
T14 523 0 0 0
T15 708 0 0 0
T16 1348 2 0 0
T17 3044 0 0 0
T18 994 0 0 0
T26 502 0 0 0
T27 0 1 0 0
T28 0 1 0 0
T40 0 1 0 0
T42 0 5 0 0
T43 0 10 0 0
T58 0 1 0 0
T59 0 1 0 0
T60 0 1 0 0
T61 0 3 0 0
T62 0 1 0 0
T64 402 0 0 0
T65 422 0 0 0
T66 448 0 0 0
T67 404 0 0 0
T68 2219 0 0 0
T92 0 20 0 0
T109 0 1 0 0
T110 0 2 0 0
T138 0 2 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22095066 2383756 0 0
T6 2286 287 0 0
T8 1014 0 0 0
T9 968 0 0 0
T19 1687 1295 0 0
T25 1012 0 0 0
T38 454044 658685 0 0
T57 438 0 0 0
T58 629 0 0 0
T64 804 0 0 0
T65 844 0 0 0
T69 2117 526 0 0
T70 0 432 0 0
T71 0 407 0 0
T72 0 184 0 0
T73 0 2098 0 0
T74 1004 0 0 0
T75 1046 0 0 0
T76 882 0 0 0
T77 812 0 0 0
T79 0 186940 0 0
T91 461 0 0 0
T99 0 31 0 0
T108 0 289 0 0
T139 0 220 0 0
T140 0 1115 0 0
T141 0 96111 0 0
T142 746 0 0 0
T143 422 0 0 0
T144 1100 0 0 0
T145 405 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%