Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	84.92	89.13	90.48		66.67	85.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	85.00	89.13	90.48		66.67	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
85.00	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
84.92	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T33,T17
1	Covered	T44,T45,T46

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T33,T17
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T16,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T16,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T16,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T19
1	0	Covered	T16,T33,T17
1	1	Covered	T16,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T19
0	1	Covered	T75,T76,T77
1	0	Covered	T47,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T19
0	1	Covered	T16,T17,T19
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T19
1	-	Covered	T16,T17,T19

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
85.00	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T44,T45,T46

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T14,T28,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T14,T28,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T14,T28,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T21
1	0	Covered	T44,T46,T71
1	1	Covered	T14,T28,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T28,T21
0	1	Covered	T79,T59,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T28,T21
0	1	Covered	T14,T28,T21
1	0	Covered	T47,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T28,T21
1	-	Covered	T14,T28,T21

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T33,T20,T22
1	Covered	T44,T45,T46

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T33,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T33,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T33,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T20,T22
1	0	Covered	T20,T22,T49
1	1	Covered	T33,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T20,T22
0	1	Covered	T33,T20,T49
1	0	Covered	T20,T49,T47

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T22,T49
0	1	Covered	T20,T22,T49
1	0	Covered	T81,T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T22,T49
1	-	Covered	T20,T22,T49

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T44,T46,T71

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T51
1	0	Covered	T44,T46,T71
1	1	Covered	T15,T50,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T50,T56
0	1	Covered	T64,T65,T68
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T50,T56
0	1	Unreachable
1	0	Covered	T15,T50,T56

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
84.92	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T44,T45,T46

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T14,T18,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T14,T18,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T14,T18,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T21
1	0	Covered	T44,T45,T46
1	1	Covered	T14,T18,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T21
0	1	Covered	T59,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T21
0	1	Covered	T18,T21,T23
1	0	Covered	T47,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T18,T21
1	-	Covered	T18,T21,T23

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T44,T46,T71

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T46,T71
1	1	Covered	T44,T46,T71

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T51,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T51
1	0	Covered	T44,T46,T71
1	1	Covered	T15,T50,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T51,T56
0	1	Covered	T86,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T51,T56
0	1	Unreachable
1	0	Covered	T15,T51,T56

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T44,T46,T71
1	Covered	T44,T45,T46

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T46,T71
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T44,T45,T46
1	Covered	T15,T50,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T51
1	0	Covered	T44,T46,T71
1	1	Covered	T15,T50,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T65,T66
0	1	Covered	T15,T51,T56
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T65,T66
0	1	Unreachable
1	0	Covered	T50,T65,T66

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
85.00	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
84.92	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T28,T21
0	1	Covered	T14,T28,T21
0	0	Covered	T44,T45,T46

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T21
0	Covered	T44,T45,T46

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T44,T45,T46
0	Covered	T44,T45,T46

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T28,T21
IdleSt	0	-	-	-	-	-	-	Covered	T44,T45,T46
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T28,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T90,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T28,T21
DetectSt	-	-	-	-	1	-	-	Covered	T15,T51,T79
DetectSt	-	-	-	-	0	1	-	Covered	T14,T28,T21
DetectSt	-	-	-	-	0	0	-	Covered	T16,T17,T19
StableSt	-	-	-	-	-	-	1	Covered	T14,T28,T21
StableSt	-	-	-	-	-	-	0	Covered	T14,T28,T21
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T44,T45,T46
0	Covered	T44,T45,T46

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T44,T45,T46
0	Covered	T44,T45,T46

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T33,T20
0	1	Covered	T15,T33,T20
0	0	Covered	T44,T45,T46

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T33,T20
0	Covered	T44,T45,T46

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T44,T45,T46
0	Covered	T44,T45,T46

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T33,T20
IdleSt	0	-	-	-	-	-	-	Covered	T44,T46,T71
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T33,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T47,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T33,T20
DetectSt	-	-	-	-	1	-	-	Covered	T33,T20,T49
DetectSt	-	-	-	-	0	1	-	Covered	T15,T22,T50
DetectSt	-	-	-	-	0	0	-	Covered	T33,T20,T22
StableSt	-	-	-	-	-	-	1	Covered	T15,T22,T50
StableSt	-	-	-	-	-	-	0	Covered	T15,T22,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T44,T45,T46
0	Covered	T44,T45,T46

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	159415022	19389	0	0
CntIncr_A	159415022	1597921	0	0
CntNoWrap_A	159415022	144848035	0	0
DetectStDropOut_A	159415022	2107	0	0
DetectedOut_A	159415022	1252315	0	0
DetectedPulseOut_A	159415022	6314	0	0
DisabledIdleSt_A	159415022	136526032	0	0
DisabledNoDetection_A	159415022	136576746	0	0
EnterDebounceSt_A	159415022	10077	0	0
EnterDetectSt_A	159415022	9324	0	0
EnterStableSt_A	159415022	6314	0	0
PulseIsPulse_A	159415022	6314	0	0
StayInStableSt	159415022	1245284	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	55182123	55761	0	0
gen_high_event_sva.HighLevelEvent_A	30656735	27869720	0	0
gen_high_level_sva.HighLevelEvent_A	104232899	94757048	0	0
gen_low_level_sva.LowLevelEvent_A	55182123	50165496	0	0
gen_not_sticky_sva.StableStDropOut_A	141020981	5431	0	0
gen_sticky_sva.StableStDropOut_A	18394041	1947460	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	19389	0	0
T16	120540	22	0	0
T17	82484	7	0	0
T18	9200	0	0	0
T19	205176	7	0	0
T20	26922	0	0	0
T21	9924	0	0	0
T22	32200	52	0	0
T28	3880	4	0	0
T29	2425	0	0	0
T30	3360	0	0	0
T31	2010	0	0	0
T32	2200	0	0	0
T33	49644	60	0	0
T34	3798	0	0	0
T47	0	25	0	0
T49	0	56	0	0
T50	0	8	0	0
T52	0	3	0	0
T53	0	23	0	0
T54	0	6	0	0
T57	0	4	0	0
T62	4041	0	0	0
T63	4707	0	0	0
T72	2410	0	0	0
T76	0	4	0	0
T79	0	4	0	0
T89	0	5	0	0
T92	0	1	0	0
T93	0	50	0	0
T94	0	5	0	0
T95	0	2	0	0
T96	0	2	0	0
T97	872	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	1597921	0	0
T16	120540	1218	0	0
T17	82484	263	0	0
T18	9200	0	0	0
T19	205176	438	0	0
T20	26922	0	0	0
T21	9924	0	0	0
T22	32200	2124	0	0
T28	3880	135	0	0
T29	2425	0	0	0
T30	3360	0	0	0
T31	2010	0	0	0
T32	2200	0	0	0
T33	49644	1740	0	0
T34	3798	0	0	0
T47	0	442	0	0
T49	0	1611	0	0
T50	0	122	0	0
T52	0	248	0	0
T53	0	1685	0	0
T54	0	366	0	0
T57	0	66	0	0
T62	4041	0	0	0
T63	4707	0	0	0
T72	2410	0	0	0
T76	0	31	0	0
T79	0	62	0	0
T89	0	178	0	0
T92	0	20	0	0
T93	0	1225	0	0
T94	0	156	0	0
T95	0	16	0	0
T96	0	55	0	0
T97	872	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	144848035	0	0
T14	17082	6648	0	0
T15	4231344	4220910	0	0
T16	783510	770872	0	0
T28	20176	9746	0	0
T29	12610	2184	0	0
T30	17472	7046	0	0
T44	13104	2678	0	0
T45	10660	234	0	0
T46	11050	624	0	0
T71	12532	2106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	2107	0	0
T33	5516	30	0	0
T47	7199	1	0	0
T49	0	13	0	0
T60	30171	0	0	0
T67	12892	0	0	0
T69	1386	0	0	0
T76	37425	1	0	0
T77	25318	9	0	0
T78	0	1	0	0
T79	615	1	0	0
T88	0	1	0	0
T93	0	25	0	0
T101	0	4	0	0
T102	0	4	0	0
T103	4916	13	0	0
T104	31472	1	0	0
T105	0	12	0	0
T106	0	3	0	0
T107	0	4	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	2	0	0
T112	0	1	0	0
T113	444	0	0	0
T114	504	0	0	0
T115	431	0	0	0
T116	521	0	0	0
T117	10599	0	0	0
T118	527	0	0	0
T119	2700	0	0	0
T120	484	0	0	0
T121	522	0	0	0
T122	3192	0	0	0
T123	490	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	1252315	0	0
T16	30135	793	0	0
T17	0	208	0	0
T19	0	162	0	0
T22	16100	1945	0	0
T23	660	0	0	0
T28	1552	11	0	0
T29	970	0	0	0
T30	1344	0	0	0
T31	804	0	0	0
T32	880	0	0	0
T33	11032	0	0	0
T34	844	0	0	0
T47	0	446	0	0
T48	0	143	0	0
T50	0	24	0	0
T52	7582	34	0	0
T53	38251	633	0	0
T54	0	114	0	0
T57	0	11	0	0
T60	0	687	0	0
T62	898	0	0	0
T63	1046	0	0	0
T72	482	0	0	0
T76	0	12	0	0
T79	0	12	0	0
T89	0	19	0	0
T94	0	15	0	0
T95	0	7	0	0
T96	0	10	0	0
T97	436	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0
T124	0	4	0	0
T125	0	7	0	0
T126	404	0	0	0
T127	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	6314	0	0
T16	30135	9	0	0
T17	0	3	0	0
T19	0	3	0	0
T22	16100	26	0	0
T23	660	0	0	0
T28	1552	2	0	0
T29	970	0	0	0
T30	1344	0	0	0
T31	804	0	0	0
T32	880	0	0	0
T33	11032	0	0	0
T34	844	0	0	0
T47	0	6	0	0
T48	0	11	0	0
T50	0	4	0	0
T52	7582	1	0	0
T53	38251	10	0	0
T54	0	2	0	0
T57	0	2	0	0
T60	0	7	0	0
T62	898	0	0	0
T63	1046	0	0	0
T72	482	0	0	0
T76	0	2	0	0
T79	0	1	0	0
T89	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	436	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	404	0	0	0
T127	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	136526032	0	0
T14	17082	4126	0	0
T15	4231344	3733982	0	0
T16	783510	748994	0	0
T28	20176	9524	0	0
T29	12610	2184	0	0
T30	17472	7046	0	0
T44	13104	2678	0	0
T45	10660	234	0	0
T46	11050	624	0	0
T71	12532	2106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	136576746	0	0
T14	17082	4142	0	0
T15	4231344	3734008	0	0
T16	783510	749258	0	0
T28	20176	9549	0	0
T29	12610	2210	0	0
T30	17472	7072	0	0
T44	13104	2704	0	0
T45	10660	260	0	0
T46	11050	650	0	0
T71	12532	2132	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	10077	0	0
T16	120540	13	0	0
T17	82484	4	0	0
T18	9200	0	0	0
T19	205176	4	0	0
T20	26922	0	0	0
T21	9924	0	0	0
T22	32200	26	0	0
T28	3880	2	0	0
T29	2425	0	0	0
T30	3360	0	0	0
T31	2010	0	0	0
T32	2200	0	0	0
T33	49644	30	0	0
T34	3798	0	0	0
T47	0	10	0	0
T49	0	28	0	0
T50	0	5	0	0
T52	0	2	0	0
T53	0	13	0	0
T54	0	4	0	0
T57	0	2	0	0
T62	4041	0	0	0
T63	4707	0	0	0
T72	2410	0	0	0
T76	0	2	0	0
T79	0	2	0	0
T89	0	3	0	0
T92	0	1	0	0
T93	0	25	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	872	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	9324	0	0
T16	120540	9	0	0
T17	82484	3	0	0
T18	9200	0	0	0
T19	205176	3	0	0
T20	26922	0	0	0
T21	9924	0	0	0
T22	32200	26	0	0
T28	3880	2	0	0
T29	2425	0	0	0
T30	3360	0	0	0
T31	2010	0	0	0
T32	2200	0	0	0
T33	49644	30	0	0
T34	3798	0	0	0
T47	0	10	0	0
T50	0	4	0	0
T52	0	1	0	0
T53	0	10	0	0
T54	0	2	0	0
T57	0	2	0	0
T60	0	7	0	0
T62	4041	0	0	0
T63	4707	0	0	0
T72	2410	0	0	0
T76	0	2	0	0
T79	0	2	0	0
T89	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	872	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0
T124	0	1	0	0
T125	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	6314	0	0
T16	30135	9	0	0
T17	0	3	0	0
T19	0	3	0	0
T22	16100	26	0	0
T23	660	0	0	0
T28	1552	2	0	0
T29	970	0	0	0
T30	1344	0	0	0
T31	804	0	0	0
T32	880	0	0	0
T33	11032	0	0	0
T34	844	0	0	0
T47	0	6	0	0
T48	0	11	0	0
T50	0	4	0	0
T52	7582	1	0	0
T53	38251	10	0	0
T54	0	2	0	0
T57	0	2	0	0
T60	0	7	0	0
T62	898	0	0	0
T63	1046	0	0	0
T72	482	0	0	0
T76	0	2	0	0
T79	0	1	0	0
T89	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	436	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	404	0	0	0
T127	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	6314	0	0
T16	30135	9	0	0
T17	0	3	0	0
T19	0	3	0	0
T22	16100	26	0	0
T23	660	0	0	0
T28	1552	2	0	0
T29	970	0	0	0
T30	1344	0	0	0
T31	804	0	0	0
T32	880	0	0	0
T33	11032	0	0	0
T34	844	0	0	0
T47	0	6	0	0
T48	0	11	0	0
T50	0	4	0	0
T52	7582	1	0	0
T53	38251	10	0	0
T54	0	2	0	0
T57	0	2	0	0
T60	0	7	0	0
T62	898	0	0	0
T63	1046	0	0	0
T72	482	0	0	0
T76	0	2	0	0
T79	0	1	0	0
T89	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	436	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	404	0	0	0
T127	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	159415022	1245284	0	0
T16	30135	784	0	0
T17	0	205	0	0
T19	0	159	0	0
T22	16100	1915	0	0
T23	660	0	0	0
T28	1552	9	0	0
T29	970	0	0	0
T30	1344	0	0	0
T31	804	0	0	0
T32	880	0	0	0
T33	11032	0	0	0
T34	844	0	0	0
T47	0	440	0	0
T48	0	132	0	0
T50	0	20	0	0
T52	7582	33	0	0
T53	38251	623	0	0
T54	0	112	0	0
T57	0	9	0	0
T60	0	680	0	0
T62	898	0	0	0
T63	1046	0	0	0
T72	482	0	0	0
T76	0	10	0	0
T79	0	11	0	0
T89	0	17	0	0
T94	0	13	0	0
T95	0	6	0	0
T96	0	9	0	0
T97	436	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0
T124	0	3	0	0
T125	0	5	0	0
T126	404	0	0	0
T127	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55182123	55761	0	0
T14	5913	4	0	0
T15	1464696	8	0	0
T16	271215	83	0	0
T18	0	5	0	0
T28	6984	9	0	0
T29	4365	82	0	0
T30	6048	8	0	0
T32	0	86	0	0
T33	0	111	0	0
T44	4536	44	0	0
T45	3690	0	0	0
T46	3825	41	0	0
T62	0	71	0	0
T63	0	28	0	0
T71	4338	73	0	0
T72	0	37	0	0
T128	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30656735	27869720	0	0
T14	3285	1285	0	0
T15	813720	811720	0	0
T16	150675	148315	0	0
T28	3880	1880	0	0
T29	2425	425	0	0
T30	3360	1360	0	0
T44	2520	520	0	0
T45	2050	50	0	0
T46	2125	125	0	0
T71	2410	410	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104232899	94757048	0	0
T14	11169	4369	0	0
T15	2766648	2759848	0	0
T16	512295	504271	0	0
T28	13192	6392	0	0
T29	8245	1445	0	0
T30	11424	4624	0	0
T44	8568	1768	0	0
T45	6970	170	0	0
T46	7225	425	0	0
T71	8194	1394	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55182123	50165496	0	0
T14	5913	2313	0	0
T15	1464696	1461096	0	0
T16	271215	266967	0	0
T28	6984	3384	0	0
T29	4365	765	0	0
T30	6048	2448	0	0
T44	4536	936	0	0
T45	3690	90	0	0
T46	3825	225	0	0
T71	4338	738	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141020981	5431	0	0
T16	30135	9	0	0
T17	0	3	0	0
T19	0	3	0	0
T22	16100	22	0	0
T23	660	0	0	0
T28	1552	2	0	0
T29	970	0	0	0
T30	1344	0	0	0
T31	804	0	0	0
T32	880	0	0	0
T33	11032	0	0	0
T34	844	0	0	0
T47	0	5	0	0
T50	0	4	0	0
T52	7582	1	0	0
T53	38251	10	0	0
T54	0	2	0	0
T57	0	2	0	0
T60	0	7	0	0
T62	898	0	0	0
T63	1046	0	0	0
T72	482	0	0	0
T75	0	5	0	0
T76	0	2	0	0
T79	0	1	0	0
T89	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	436	0	0	0
T98	4402	0	0	0
T99	502	0	0	0
T100	424	0	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	404	0	0	0
T127	422	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18394041	1947460	0	0
T15	325488	162087	0	0
T16	60270	0	0	0
T28	1552	0	0	0
T29	970	0	0	0
T30	1344	0	0	0
T31	804	0	0	0
T32	880	0	0	0
T33	11032	0	0	0
T34	844	0	0	0
T50	7979	170	0	0
T51	2384	601	0	0
T55	594	0	0	0
T56	0	372	0	0
T62	898	0	0	0
T64	0	109	0	0
T65	2706	336	0	0
T66	0	1217195	0	0
T67	0	310	0	0
T68	0	56	0	0
T69	0	414	0	0
T86	0	312	0	0
T95	565	0	0	0
T96	706	0	0	0
T102	13785	0	0	0
T125	768	0	0	0
T129	0	258	0	0
T130	0	119	0	0
T131	0	337	0	0
T132	0	580	0	0
T133	0	95	0	0
T134	0	86	0	0
T135	674	0	0	0
T136	429	0	0	0