Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T64,T68,T67

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T64,T68,T67

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T64,T68,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T64,T72
1	0	Covered	T42,T43,T44
1	1	Covered	T64,T68,T67

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T64,T68,T67
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T64,T68,T67
0	1	Covered	T163,T206,T208
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T64,T68,T67
1	-	Covered	T163,T206,T208

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T64,T68,T67
0	1	Covered	T64,T68,T67
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T64,T68,T67
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T64,T68,T67
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T64,T68,T67
DebounceSt	-	0	1	0	-	-	-	Covered	T127
DebounceSt	-	0	0	-	-	-	-	Covered	T64,T68,T67
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T64,T68,T67
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T163,T206,T208
StableSt	-	-	-	-	-	-	0	Covered	T64,T68,T67
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	82	0	0
CntIncr_A	7802930	28429	0	0
CntNoWrap_A	7802930	7196349	0	0
DetectStDropOut_A	7802930	0	0	0
DetectedOut_A	7802930	3116	0	0
DetectedPulseOut_A	7802930	40	0	0
DisabledIdleSt_A	7802930	7131769	0	0
DisabledNoDetection_A	7802930	7133973	0	0
EnterDebounceSt_A	7802930	42	0	0
EnterDetectSt_A	7802930	40	0	0
EnterStableSt_A	7802930	40	0	0
PulseIsPulse_A	7802930	40	0	0
StayInStableSt	7802930	3051	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	82	0	0
T64	620	2	0	0
T67	0	2	0	0
T68	0	2	0	0
T70	480	0	0	0
T97	0	1	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	2	0	0
T183	0	2	0	0
T206	0	4	0	0
T208	0	4	0	0
T209	0	2	0	0
T210	0	2	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	28429	0	0
T64	620	32	0	0
T67	0	70	0	0
T68	0	87	0	0
T70	480	0	0	0
T97	0	20	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	90	0	0
T183	0	99	0	0
T206	0	144	0	0
T208	0	74	0	0
T209	0	56	0	0
T210	0	2265	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196349	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	3116	0	0
T64	620	94	0	0
T67	0	46	0	0
T68	0	129	0	0
T70	480	0	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	136	0	0
T183	0	90	0	0
T206	0	80	0	0
T208	0	79	0	0
T209	0	188	0	0
T210	0	46	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0
T217	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	40	0	0
T64	620	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	480	0	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	1	0	0
T183	0	1	0	0
T206	0	2	0	0
T208	0	2	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7131769	0	0
T16	625	3	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7133973	0	0
T16	625	3	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	42	0	0
T64	620	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	480	0	0	0
T97	0	1	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	1	0	0
T183	0	1	0	0
T206	0	2	0	0
T208	0	2	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	40	0	0
T64	620	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	480	0	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	1	0	0
T183	0	1	0	0
T206	0	2	0	0
T208	0	2	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	40	0	0
T64	620	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	480	0	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	1	0	0
T183	0	1	0	0
T206	0	2	0	0
T208	0	2	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	40	0	0
T64	620	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	480	0	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	1	0	0
T183	0	1	0	0
T206	0	2	0	0
T208	0	2	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	3051	0	0
T64	620	92	0	0
T67	0	44	0	0
T68	0	127	0	0
T70	480	0	0	0
T108	669	0	0	0
T109	677	0	0	0
T163	0	135	0	0
T183	0	88	0	0
T206	0	77	0	0
T208	0	76	0	0
T209	0	186	0	0
T210	0	44	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T215	723	0	0	0
T216	806	0	0	0
T217	0	52	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	14	0	0
T163	2509	1	0	0
T164	502	0	0	0
T165	405	0	0	0
T197	0	1	0	0
T206	860	1	0	0
T208	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0
T224	577	0	0	0
T225	7969	0	0	0
T226	407	0	0	0
T227	422	0	0	0
T228	842	0	0	0
T229	699	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T19,T23,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T19,T23,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T19,T23,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T23,T25
1	0	Covered	T42,T44,T103
1	1	Covered	T19,T23,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T25
0	1	Covered	T187,T193,T230
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T25
0	1	Covered	T19,T23,T25
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T23,T25
1	-	Covered	T19,T23,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T23,T25
0	1	Covered	T19,T23,T25
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T23,T25
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T23,T25
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T23,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T231,T232,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T23,T25
DetectSt	-	-	-	-	1	-	-	Covered	T187,T193,T230
DetectSt	-	-	-	-	0	1	-	Covered	T19,T23,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T23,T25
StableSt	-	-	-	-	-	-	0	Covered	T19,T23,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	150	0	0
CntIncr_A	7802930	77504	0	0
CntNoWrap_A	7802930	7196281	0	0
DetectStDropOut_A	7802930	4	0	0
DetectedOut_A	7802930	9353	0	0
DetectedPulseOut_A	7802930	69	0	0
DisabledIdleSt_A	7802930	7044935	0	0
DisabledNoDetection_A	7802930	7047140	0	0
EnterDebounceSt_A	7802930	77	0	0
EnterDetectSt_A	7802930	73	0	0
EnterStableSt_A	7802930	69	0	0
PulseIsPulse_A	7802930	69	0	0
StayInStableSt	7802930	9253	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802930	3363	0	0
gen_low_level_sva.LowLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	150	0	0
T19	3084	4	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	6	0	0
T25	0	4	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	2	0	0
T64	0	2	0	0
T65	0	4	0	0
T67	0	2	0	0
T69	0	2	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	2	0	0
T99	0	4	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	77504	0	0
T19	3084	130	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	54	0	0
T25	0	50	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1332	0	0
T64	0	32	0	0
T65	0	48	0	0
T67	0	70	0	0
T69	0	89	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	17	0	0
T99	0	30	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196281	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	4	0	0
T125	658	0	0	0
T126	43392	0	0	0
T137	715	0	0	0
T138	90396	0	0	0
T139	555	0	0	0
T187	910	1	0	0
T193	87484	1	0	0
T197	0	1	0	0
T202	422	0	0	0
T203	8764	0	0	0
T230	0	1	0	0
T234	466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	9353	0	0
T19	3084	150	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	32	0	0
T25	0	87	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1230	0	0
T64	0	54	0	0
T65	0	84	0	0
T67	0	29	0	0
T69	0	6	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	43	0	0
T99	0	97	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	69	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	3	0	0
T25	0	2	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T99	0	2	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7044935	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7047140	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	77	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	3	0	0
T25	0	2	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T99	0	2	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	73	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	3	0	0
T25	0	2	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T99	0	2	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	69	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	3	0	0
T25	0	2	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T99	0	2	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	69	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	3	0	0
T25	0	2	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T99	0	2	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	9253	0	0
T19	3084	147	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	29	0	0
T25	0	84	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1228	0	0
T64	0	53	0	0
T65	0	81	0	0
T67	0	28	0	0
T69	0	5	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	41	0	0
T99	0	94	0	0
T112	522	0	0	0
T113	443	0	0	0
T233	484	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	3363	0	0
T16	625	1	0	0
T29	500	4	0	0
T30	2227	12	0	0
T31	526	4	0	0
T33	0	4	0	0
T42	1536	3	0	0
T43	681	0	0	0
T44	503	6	0	0
T91	482	6	0	0
T103	525	5	0	0
T111	522	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	37	0	0
T19	3084	1	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	3	0	0
T25	0	1	0	0
T50	6967	0	0	0
T52	469	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T99	0	1	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	1	0	0
T206	0	2	0	0
T233	484	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T44,T103,T91

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T44,T103,T91
1	1	Covered	T44,T103,T91

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T19,T23,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T19,T23,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T19,T23,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T23,T25
1	0	Covered	T44,T103,T91
1	1	Covered	T19,T23,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T25
0	1	Covered	T106,T235,T236
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T23,T25
0	1	Covered	T19,T23,T25
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T23,T25
1	-	Covered	T19,T23,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T23,T25
0	1	Covered	T19,T23,T25
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T23,T25
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T23,T25
IdleSt	0	-	-	-	-	-	-	Covered	T44,T103,T91
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T23,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T208,T198,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T23,T25
DetectSt	-	-	-	-	1	-	-	Covered	T106,T235,T236
DetectSt	-	-	-	-	0	1	-	Covered	T19,T23,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T23,T25
StableSt	-	-	-	-	-	-	0	Covered	T19,T23,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	158	0	0
CntIncr_A	7802930	202799	0	0
CntNoWrap_A	7802930	7196273	0	0
DetectStDropOut_A	7802930	4	0	0
DetectedOut_A	7802930	165662	0	0
DetectedPulseOut_A	7802930	73	0	0
DisabledIdleSt_A	7802930	6484911	0	0
DisabledNoDetection_A	7802930	6487110	0	0
EnterDebounceSt_A	7802930	81	0	0
EnterDetectSt_A	7802930	77	0	0
EnterStableSt_A	7802930	73	0	0
PulseIsPulse_A	7802930	73	0	0
StayInStableSt	7802930	165560	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	158	0	0
T19	3084	4	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	4	0	0
T25	0	6	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	2	0	0
T65	0	4	0	0
T72	0	2	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	2	0	0
T106	0	2	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	2	0	0
T199	0	2	0	0
T233	484	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	202799	0	0
T19	3084	130	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	36	0	0
T25	0	189	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1332	0	0
T65	0	48	0	0
T72	0	47	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	17	0	0
T106	0	59	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	90	0	0
T199	0	20	0	0
T233	484	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196273	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	4	0	0
T96	26492	0	0	0
T106	570	1	0	0
T194	10336	0	0	0
T232	0	1	0	0
T235	646	1	0	0
T236	625	1	0	0
T238	20783	0	0	0
T239	407	0	0	0
T240	16627	0	0	0
T241	405	0	0	0
T242	694	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	165662	0	0
T19	3084	60	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	62	0	0
T25	0	190	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	875	0	0
T65	0	120	0	0
T72	0	80	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	43	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	338	0	0
T199	0	75	0	0
T209	0	91	0	0
T233	484	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	73	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T65	0	2	0	0
T72	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	1	0	0
T199	0	1	0	0
T209	0	1	0	0
T233	484	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6484911	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6487110	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	81	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T65	0	2	0	0
T72	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T106	0	1	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	1	0	0
T199	0	1	0	0
T233	484	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	77	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T65	0	2	0	0
T72	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T106	0	1	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	1	0	0
T199	0	1	0	0
T233	484	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	73	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T65	0	2	0	0
T72	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	1	0	0
T199	0	1	0	0
T209	0	1	0	0
T233	484	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	73	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T65	0	2	0	0
T72	0	1	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	1	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	1	0	0
T199	0	1	0	0
T209	0	1	0	0
T233	484	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	165560	0	0
T19	3084	58	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	59	0	0
T25	0	186	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	874	0	0
T65	0	118	0	0
T72	0	78	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	41	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	337	0	0
T199	0	74	0	0
T209	0	89	0	0
T233	484	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	43	0	0
T19	3084	2	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T50	6967	0	0	0
T52	469	0	0	0
T57	0	1	0	0
T65	0	2	0	0
T75	4139	0	0	0
T76	506	0	0	0
T100	0	1	0	0
T112	522	0	0	0
T113	443	0	0	0
T163	0	1	0	0
T199	0	1	0	0
T208	0	1	0	0
T210	0	1	0	0
T233	484	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T44,T103,T91
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T103,T91
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T16,T25,T64

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T16,T25,T64

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T16,T25,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T25,T64
1	0	Covered	T42,T44,T103
1	1	Covered	T16,T25,T64

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T25,T64
0	1	Covered	T66,T138
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T25,T64
0	1	Covered	T16,T25,T64
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T25,T64
1	-	Covered	T16,T25,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T25,T64
0	1	Covered	T16,T25,T64
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T25,T64
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T25,T64
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T25,T64
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T25,T64
DetectSt	-	-	-	-	1	-	-	Covered	T66,T138
DetectSt	-	-	-	-	0	1	-	Covered	T16,T25,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T25,T64
StableSt	-	-	-	-	-	-	0	Covered	T16,T25,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	85	0	0
CntIncr_A	7802930	49277	0	0
CntNoWrap_A	7802930	7196346	0	0
DetectStDropOut_A	7802930	2	0	0
DetectedOut_A	7802930	18276	0	0
DetectedPulseOut_A	7802930	40	0	0
DisabledIdleSt_A	7802930	6834499	0	0
DisabledNoDetection_A	7802930	6836709	0	0
EnterDebounceSt_A	7802930	43	0	0
EnterDetectSt_A	7802930	42	0	0
EnterStableSt_A	7802930	40	0	0
PulseIsPulse_A	7802930	40	0	0
StayInStableSt	7802930	18215	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802930	7371	0	0
gen_low_level_sva.LowLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	85	0	0
T16	625	2	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	2	0	0
T66	0	2	0	0
T97	0	1	0	0
T99	0	2	0	0
T106	0	2	0	0
T163	0	2	0	0
T210	0	2	0	0
T235	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	49277	0	0
T16	625	25	0	0
T25	0	48	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	32	0	0
T66	0	88	0	0
T97	0	20	0	0
T99	0	15	0	0
T106	0	59	0	0
T163	0	90	0	0
T210	0	2265	0	0
T235	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196346	0	0
T16	625	222	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	2	0	0
T66	1060	1	0	0
T138	90396	1	0	0
T139	555	0	0	0
T140	446	0	0	0
T141	803	0	0	0
T142	423	0	0	0
T143	707	0	0	0
T144	5019	0	0	0
T201	508	0	0	0
T243	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	18276	0	0
T16	625	40	0	0
T25	0	79	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	12	0	0
T99	0	40	0	0
T106	0	44	0	0
T163	0	134	0	0
T203	0	166	0	0
T210	0	2632	0	0
T235	0	42	0	0
T244	0	13110	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	40	0	0
T16	625	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T99	0	1	0	0
T106	0	1	0	0
T163	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0
T235	0	1	0	0
T244	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6834499	0	0
T16	625	3	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6836709	0	0
T16	625	3	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	43	0	0
T16	625	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T97	0	1	0	0
T99	0	1	0	0
T106	0	1	0	0
T163	0	1	0	0
T210	0	1	0	0
T235	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	42	0	0
T16	625	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T66	0	1	0	0
T99	0	1	0	0
T106	0	1	0	0
T163	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0
T235	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	40	0	0
T16	625	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T99	0	1	0	0
T106	0	1	0	0
T163	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0
T235	0	1	0	0
T244	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	40	0	0
T16	625	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T99	0	1	0	0
T106	0	1	0	0
T163	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0
T235	0	1	0	0
T244	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	18215	0	0
T16	625	39	0	0
T25	0	78	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	11	0	0
T99	0	39	0	0
T106	0	42	0	0
T163	0	132	0	0
T203	0	164	0	0
T210	0	2630	0	0
T235	0	40	0	0
T244	0	13109	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7371	0	0
T16	625	1	0	0
T29	500	0	0	0
T30	2227	11	0	0
T31	526	5	0	0
T32	8457	0	0	0
T33	505	8	0	0
T35	0	9	0	0
T36	0	2	0	0
T44	503	6	0	0
T91	482	12	0	0
T103	525	3	0	0
T111	522	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	18	0	0
T16	625	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T64	0	1	0	0
T99	0	1	0	0
T129	0	1	0	0
T181	0	1	0	0
T194	0	1	0	0
T219	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T44,T103,T91

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T44,T103,T91
1	1	Covered	T44,T103,T91

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T25,T64,T67

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T25,T64,T67

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T25,T64,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T64,T67
1	0	Covered	T44,T103,T91
1	1	Covered	T25,T64,T67

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T64,T67
0	1	Covered	T221,T246,T247
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T64,T67
0	1	Covered	T25,T64,T67
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T64,T67
1	-	Covered	T25,T64,T67

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T64,T67
0	1	Covered	T25,T64,T67
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T64,T67
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T64,T67
IdleSt	0	-	-	-	-	-	-	Covered	T44,T103,T91
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T64,T67
DebounceSt	-	0	1	0	-	-	-	Covered	T248,T249
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T64,T67
DetectSt	-	-	-	-	1	-	-	Covered	T221,T246,T247
DetectSt	-	-	-	-	0	1	-	Covered	T25,T64,T67
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T64,T67
StableSt	-	-	-	-	-	-	0	Covered	T25,T64,T67
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	125	0	0
CntIncr_A	7802930	197524	0	0
CntNoWrap_A	7802930	7196306	0	0
DetectStDropOut_A	7802930	4	0	0
DetectedOut_A	7802930	77019	0	0
DetectedPulseOut_A	7802930	57	0	0
DisabledIdleSt_A	7802930	6476424	0	0
DisabledNoDetection_A	7802930	6478631	0	0
EnterDebounceSt_A	7802930	64	0	0
EnterDetectSt_A	7802930	61	0	0
EnterStableSt_A	7802930	57	0	0
PulseIsPulse_A	7802930	57	0	0
StayInStableSt	7802930	76935	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	125	0	0
T25	27520	4	0	0
T57	0	2	0	0
T64	620	2	0	0
T67	0	2	0	0
T70	480	0	0	0
T90	0	2	0	0
T97	0	1	0	0
T100	0	4	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T209	0	4	0	0
T210	0	2	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	197524	0	0
T25	27520	96	0	0
T57	0	1332	0	0
T64	620	32	0	0
T67	0	70	0	0
T70	480	0	0	0
T90	0	17	0	0
T97	0	20	0	0
T100	0	143	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T209	0	112	0	0
T210	0	2265	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196306	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	4	0	0
T95	30511	0	0	0
T128	6151	0	0	0
T221	45094	2	0	0
T246	3238	1	0	0
T247	0	1	0	0
T250	502	0	0	0
T251	480	0	0	0
T252	599	0	0	0
T253	2693	0	0	0
T254	505	0	0	0
T255	21934	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	77019	0	0
T25	27520	221	0	0
T57	0	875	0	0
T64	620	85	0	0
T67	0	29	0	0
T70	480	0	0	0
T90	0	65	0	0
T100	0	242	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T208	0	198	0	0
T209	0	79	0	0
T210	0	40	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	141	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	57	0	0
T25	27520	2	0	0
T57	0	1	0	0
T64	620	1	0	0
T67	0	1	0	0
T70	480	0	0	0
T90	0	1	0	0
T100	0	2	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T208	0	1	0	0
T209	0	2	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6476424	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6478631	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	64	0	0
T25	27520	2	0	0
T57	0	1	0	0
T64	620	1	0	0
T67	0	1	0	0
T70	480	0	0	0
T90	0	1	0	0
T97	0	1	0	0
T100	0	2	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T209	0	2	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	61	0	0
T25	27520	2	0	0
T57	0	1	0	0
T64	620	1	0	0
T67	0	1	0	0
T70	480	0	0	0
T90	0	1	0	0
T100	0	2	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T208	0	1	0	0
T209	0	2	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	57	0	0
T25	27520	2	0	0
T57	0	1	0	0
T64	620	1	0	0
T67	0	1	0	0
T70	480	0	0	0
T90	0	1	0	0
T100	0	2	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T208	0	1	0	0
T209	0	2	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	57	0	0
T25	27520	2	0	0
T57	0	1	0	0
T64	620	1	0	0
T67	0	1	0	0
T70	480	0	0	0
T90	0	1	0	0
T100	0	2	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T208	0	1	0	0
T209	0	2	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	76935	0	0
T25	27520	218	0	0
T57	0	874	0	0
T64	620	84	0	0
T67	0	28	0	0
T70	480	0	0	0
T90	0	63	0	0
T100	0	240	0	0
T108	669	0	0	0
T109	677	0	0	0
T188	422	0	0	0
T208	0	197	0	0
T209	0	76	0	0
T210	0	39	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T235	0	139	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	29	0	0
T25	27520	1	0	0
T57	0	1	0	0
T64	620	1	0	0
T67	0	1	0	0
T70	480	0	0	0
T100	0	2	0	0
T108	669	0	0	0
T109	677	0	0	0
T183	0	1	0	0
T188	422	0	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	599	0	0	0
T212	433	0	0	0
T213	516	0	0	0
T214	525	0	0	0
T256	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T44,T103,T91
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T103,T91
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T16,T19,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T16,T19,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T16,T19,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T25
1	0	Covered	T42,T44,T103
1	1	Covered	T16,T19,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T25
0	1	Covered	T181
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T25
0	1	Covered	T16,T19,T25
1	0	Covered	T98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T19,T25
1	-	Covered	T16,T19,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T19,T25
0	1	Covered	T16,T19,T25
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T19,T25
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T19,T25
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T19,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T198,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T19,T25
DetectSt	-	-	-	-	1	-	-	Covered	T181
DetectSt	-	-	-	-	0	1	-	Covered	T16,T19,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T19,T25
StableSt	-	-	-	-	-	-	0	Covered	T16,T19,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	90	0	0
CntIncr_A	7802930	114196	0	0
CntNoWrap_A	7802930	7196341	0	0
DetectStDropOut_A	7802930	1	0	0
DetectedOut_A	7802930	16923	0	0
DetectedPulseOut_A	7802930	42	0	0
DisabledIdleSt_A	7802930	6372002	0	0
DisabledNoDetection_A	7802930	6374203	0	0
EnterDebounceSt_A	7802930	47	0	0
EnterDetectSt_A	7802930	43	0	0
EnterStableSt_A	7802930	42	0	0
PulseIsPulse_A	7802930	42	0	0
StayInStableSt	7802930	16859	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7802930	7072	0	0
gen_low_level_sva.LowLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	90	0	0
T16	625	2	0	0
T19	0	4	0	0
T25	0	4	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	2	0	0
T69	0	2	0	0
T97	0	1	0	0
T100	0	2	0	0
T183	0	2	0	0
T206	0	2	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	114196	0	0
T16	625	25	0	0
T19	0	130	0	0
T25	0	73	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1332	0	0
T69	0	89	0	0
T97	0	20	0	0
T100	0	54	0	0
T183	0	99	0	0
T206	0	72	0	0
T208	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7196341	0	0
T16	625	222	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1	0	0
T127	24866	0	0	0
T177	1478	0	0	0
T181	865	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	16923	0	0
T16	625	40	0	0
T19	0	78	0	0
T25	0	146	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1230	0	0
T69	0	138	0	0
T100	0	38	0	0
T183	0	92	0	0
T206	0	40	0	0
T207	0	40	0	0
T208	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	42	0	0
T16	625	1	0	0
T19	0	2	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1	0	0
T69	0	1	0	0
T100	0	1	0	0
T183	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6372002	0	0
T16	625	3	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6374203	0	0
T16	625	3	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	47	0	0
T16	625	1	0	0
T19	0	2	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1	0	0
T69	0	1	0	0
T97	0	1	0	0
T100	0	1	0	0
T183	0	1	0	0
T206	0	1	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	43	0	0
T16	625	1	0	0
T19	0	2	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1	0	0
T69	0	1	0	0
T100	0	1	0	0
T183	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	42	0	0
T16	625	1	0	0
T19	0	2	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1	0	0
T69	0	1	0	0
T100	0	1	0	0
T183	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	42	0	0
T16	625	1	0	0
T19	0	2	0	0
T25	0	2	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1	0	0
T69	0	1	0	0
T100	0	1	0	0
T183	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	16859	0	0
T16	625	39	0	0
T19	0	75	0	0
T25	0	143	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T57	0	1228	0	0
T69	0	136	0	0
T100	0	36	0	0
T183	0	91	0	0
T206	0	38	0	0
T207	0	38	0	0
T208	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7072	0	0
T16	625	1	0	0
T29	500	0	0	0
T30	2227	11	0	0
T31	526	5	0	0
T32	8457	0	0	0
T33	505	4	0	0
T35	0	9	0	0
T36	0	2	0	0
T44	503	4	0	0
T91	482	10	0	0
T103	525	5	0	0
T111	522	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	19	0	0
T16	625	1	0	0
T19	0	1	0	0
T25	0	1	0	0
T29	500	0	0	0
T30	2227	0	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T183	0	1	0	0
T187	0	1	0	0
T194	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T244	0	1	0	0
T257	0	1	0	0