Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.31	93.48	90.91		83.33	90.48	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.31	93.48	90.91		83.33	90.48	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T5 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T12 T53 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T12 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T12 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T12 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T12 T53 
163        1/1                    state_d = IdleSt;
           Tests:       T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T12 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T12 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T12 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T12 T53 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T12 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T12 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T12 T53 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T12 T53 
191        1/1                      state_d = StableSt;
           Tests:       T11 T12 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T12 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T12 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T12 T53 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T12 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T12 T54 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T12 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T12,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T12,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T12,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T46
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T12,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T53
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T53
0	1	Covered	T11,T54,T50
1	0	Covered	T12

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T53
1	-	Covered	T11,T54,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T53
DetectSt	168	Covered	T11,T12,T53
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T12,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T53
DebounceSt->IdleSt	163	Covered	T55
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T12,T53
IdleSt->DebounceSt	148	Covered	T11,T12,T53
StableSt->IdleSt	206	Covered	T11,T12,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T53
0	1	Covered	T11,T12,T53
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T53
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T53
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T53
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T53
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T54
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	35	0	0
CntIncr_A	7365022	715	0	0
CntNoWrap_A	7365022	6893609	0	0
DetectStDropOut_A	7365022	0	0	0
DetectedOut_A	7365022	872	0	0
DetectedPulseOut_A	7365022	17	0	0
DisabledIdleSt_A	7365022	6885959	0	0
DisabledNoDetection_A	7365022	6887793	0	0
EnterDebounceSt_A	7365022	18	0	0
EnterDetectSt_A	7365022	17	0	0
EnterStableSt_A	7365022	17	0	0
PulseIsPulse_A	7365022	17	0	0
StayInStableSt	7365022	848	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T11	694	4	0	0
T12	7268	2	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	4	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	2	0	0
T160	0	4	0	0
T178	0	2	0	0
T180	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	715	0	0
T11	694	84	0	0
T12	7268	15	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	36	0	0
T53	0	11	0	0
T54	0	11	0	0
T55	0	28	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	88	0	0
T160	0	108	0	0
T178	0	66	0	0
T180	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6893609	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	872	0	0
T11	694	84	0	0
T12	7268	19	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	49	0	0
T53	0	40	0	0
T54	0	53	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	219	0	0
T160	0	93	0	0
T178	0	39	0	0
T180	0	41	0	0
T181	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	17	0	0
T11	694	2	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	1	0	0
T160	0	2	0	0
T178	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6885959	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6887793	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	18	0	0
T11	694	2	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	1	0	0
T160	0	2	0	0
T178	0	1	0	0
T180	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	17	0	0
T11	694	2	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	1	0	0
T160	0	2	0	0
T178	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	17	0	0
T11	694	2	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	1	0	0
T160	0	2	0	0
T178	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	17	0	0
T11	694	2	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	1	0	0
T160	0	2	0	0
T178	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	848	0	0
T11	694	81	0	0
T12	7268	18	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	46	0	0
T53	0	38	0	0
T54	0	52	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	218	0	0
T160	0	91	0	0
T178	0	38	0	0
T180	0	39	0	0
T181	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	9	0	0
T11	694	1	0	0
T12	7268	0	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T154	0	1	0	0
T160	0	2	0	0
T167	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T5 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T7 T11 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T7 T11 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T7 T11 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T7 T11 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T7 T11 T12 
163        1/1                    state_d = IdleSt;
           Tests:       T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T7 T11 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T11 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T7 T11 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T7 T11 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T165 T167 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T7 T11 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T7 T11 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T7 T11 T12 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T7 T11 T12 
191        1/1                      state_d = StableSt;
           Tests:       T7 T11 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T7 T11 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T7 T11 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T7 T11 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T7 T11 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T12 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T7 T11 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T12
1	0	Covered	T4,T5,T13
1	1	Covered	T7,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T12
0	1	Covered	T11,T45,T54
1	0	Covered	T12

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T12
1	-	Covered	T11,T45,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T12
DetectSt	168	Covered	T7,T11,T12
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T12
DebounceSt->IdleSt	163	Covered	T11,T55,T165
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T11,T12
IdleSt->DebounceSt	148	Covered	T7,T11,T12
StableSt->IdleSt	206	Covered	T11,T12,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T11,T12
0	1	Covered	T7,T11,T12
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T12
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T165,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T45
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	88	0	0
CntIncr_A	7365022	2480	0	0
CntNoWrap_A	7365022	6893556	0	0
DetectStDropOut_A	7365022	0	0	0
DetectedOut_A	7365022	4735	0	0
DetectedPulseOut_A	7365022	42	0	0
DisabledIdleSt_A	7365022	6881604	0	0
DisabledNoDetection_A	7365022	6883429	0	0
EnterDebounceSt_A	7365022	46	0	0
EnterDetectSt_A	7365022	42	0	0
EnterStableSt_A	7365022	42	0	0
PulseIsPulse_A	7365022	42	0	0
StayInStableSt	7365022	4675	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7365022	1784	0	0
gen_low_level_sva.LowLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	88	0	0
T7	615	2	0	0
T10	480	0	0	0
T11	694	3	0	0
T12	0	2	0	0
T29	471	0	0	0
T45	0	2	0	0
T54	0	4	0	0
T55	0	1	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	6	0	0
T180	0	2	0	0
T182	0	2	0	0
T183	0	2	0	0
T184	420	0	0	0
T185	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	2480	0	0
T7	615	96	0	0
T10	480	0	0	0
T11	694	84	0	0
T12	0	15	0	0
T29	471	0	0	0
T45	0	95	0	0
T54	0	22	0	0
T55	0	29	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	162	0	0
T180	0	56	0	0
T182	0	31	0	0
T183	0	47	0	0
T184	420	0	0	0
T185	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6893556	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	4735	0	0
T7	615	39	0	0
T10	480	0	0	0
T11	694	31	0	0
T12	0	19	0	0
T29	471	0	0	0
T45	0	296	0	0
T54	0	99	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	192	0	0
T179	0	258	0	0
T180	0	28	0	0
T182	0	66	0	0
T183	0	69	0	0
T184	420	0	0	0
T185	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	42	0	0
T7	615	1	0	0
T10	480	0	0	0
T11	694	1	0	0
T12	0	1	0	0
T29	471	0	0	0
T45	0	1	0	0
T54	0	2	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	3	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	420	0	0	0
T185	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6881604	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6883429	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	46	0	0
T7	615	1	0	0
T10	480	0	0	0
T11	694	2	0	0
T12	0	1	0	0
T29	471	0	0	0
T45	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	3	0	0
T180	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	420	0	0	0
T185	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	42	0	0
T7	615	1	0	0
T10	480	0	0	0
T11	694	1	0	0
T12	0	1	0	0
T29	471	0	0	0
T45	0	1	0	0
T54	0	2	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	3	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	420	0	0	0
T185	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	42	0	0
T7	615	1	0	0
T10	480	0	0	0
T11	694	1	0	0
T12	0	1	0	0
T29	471	0	0	0
T45	0	1	0	0
T54	0	2	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	3	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	420	0	0	0
T185	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	42	0	0
T7	615	1	0	0
T10	480	0	0	0
T11	694	1	0	0
T12	0	1	0	0
T29	471	0	0	0
T45	0	1	0	0
T54	0	2	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	3	0	0
T179	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	420	0	0	0
T185	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	4675	0	0
T7	615	37	0	0
T10	480	0	0	0
T11	694	30	0	0
T12	0	18	0	0
T29	471	0	0	0
T45	0	295	0	0
T54	0	96	0	0
T78	927	0	0	0
T86	505	0	0	0
T87	2375	0	0	0
T88	523	0	0	0
T160	0	188	0	0
T179	0	257	0	0
T180	0	27	0	0
T182	0	64	0	0
T183	0	67	0	0
T184	420	0	0	0
T185	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1784	0	0
T2	483	0	0	0
T3	709	1	0	0
T4	447	5	0	0
T5	496	7	0	0
T13	422	1	0	0
T14	523	6	0	0
T15	708	4	0	0
T16	674	0	0	0
T17	1522	1	0	0
T18	497	5	0	0
T26	0	6	0	0
T65	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	23	0	0
T11	694	1	0	0
T12	7268	0	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T148	0	1	0	0
T160	0	2	0	0
T163	0	2	0	0
T165	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T11 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T11 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T11 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T11 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T11 T12 
163        1/1                    state_d = IdleSt;
           Tests:       T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T11 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T11 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T11 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T11 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T54 T186 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T11 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T11 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T11 T12 
186        1/1                    state_d = IdleSt;
           Tests:       T54 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T54 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T11 T12 
191        1/1                      state_d = StableSt;
           Tests:       T3 T11 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T11 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T11 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T11 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T11 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T154 T177 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T11 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T4,T5,T13
1	1	Covered	T3,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T54
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T154,T177,T178
1	0	Covered	T12

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T12
1	-	Covered	T154,T177,T178

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T12
DetectSt	168	Covered	T3,T11,T12
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T12
DebounceSt->IdleSt	163	Covered	T54,T55,T186
DetectSt->IdleSt	186	Covered	T54
DetectSt->StableSt	191	Covered	T3,T11,T12
IdleSt->DebounceSt	148	Covered	T3,T11,T12
StableSt->IdleSt	206	Covered	T12,T154,T177

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T54
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T154,T177
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	75	0	0
CntIncr_A	7365022	1821	0	0
CntNoWrap_A	7365022	6893569	0	0
DetectStDropOut_A	7365022	1	0	0
DetectedOut_A	7365022	2936	0	0
DetectedPulseOut_A	7365022	35	0	0
DisabledIdleSt_A	7365022	6884691	0	0
DisabledNoDetection_A	7365022	6886520	0	0
EnterDebounceSt_A	7365022	39	0	0
EnterDetectSt_A	7365022	36	0	0
EnterStableSt_A	7365022	35	0	0
PulseIsPulse_A	7365022	35	0	0
StayInStableSt	7365022	2880	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	75	0	0
T3	709	2	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T26	502	0	0	0
T47	0	2	0	0
T49	0	2	0	0
T54	0	5	0	0
T55	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	4	0	0
T161	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1821	0	0
T3	709	53	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	42	0	0
T12	0	15	0	0
T26	502	0	0	0
T47	0	30	0	0
T49	0	27	0	0
T54	0	33	0	0
T55	0	29	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	176	0	0
T161	0	34	0	0
T177	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6893569	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1	0	0
T42	14065	0	0	0
T54	608	1	0	0
T55	6882	0	0	0
T187	521	0	0	0
T188	768	0	0	0
T189	502	0	0	0
T190	454	0	0	0
T191	4402	0	0	0
T192	402	0	0	0
T193	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	2936	0	0
T3	709	192	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	43	0	0
T12	0	20	0	0
T26	502	0	0	0
T47	0	122	0	0
T49	0	169	0	0
T54	0	45	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	321	0	0
T161	0	104	0	0
T177	0	1	0	0
T178	0	58	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	502	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T54	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	2	0	0
T161	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6884691	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6886520	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	39	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	502	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	2	0	0
T161	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	36	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	502	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T54	0	2	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	2	0	0
T161	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	502	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T54	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	2	0	0
T161	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	502	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T54	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	2	0	0
T161	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	2880	0	0
T3	709	190	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T11	0	41	0	0
T12	0	19	0	0
T26	502	0	0	0
T47	0	120	0	0
T49	0	167	0	0
T54	0	43	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T154	0	318	0	0
T161	0	102	0	0
T178	0	57	0	0
T194	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	13	0	0
T39	26369	0	0	0
T94	5216	0	0	0
T95	6637	0	0	0
T154	1127	1	0	0
T155	406	0	0	0
T156	422	0	0	0
T157	764	0	0	0
T158	1010	0	0	0
T164	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T181	0	1	0	0
T186	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	493	0	0	0
T198	156132	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T12 T48 T55 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T12 T48 T55 
149        1/1                    cnt_en = 1'b1;
           Tests:       T12 T48 T55 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T12 T48 T55 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T12 T48 T55 
163        1/1                    state_d = IdleSt;
           Tests:       T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T12 T48 T55 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T48 T50 
167        1/1                    if (trigger_active) begin
           Tests:       T12 T48 T50 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T48 T50 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T159 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T48 T50 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T48 T50 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T48 T50 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T48 T50 
191        1/1                      state_d = StableSt;
           Tests:       T12 T48 T50 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T48 T50 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T48 T50 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T48 T50 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T48 T50 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T48 T50 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T48 T50 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T48,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T48,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T48,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T48
1	0	Covered	T4,T5,T13
1	1	Covered	T12,T48,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T48,T50
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T48,T50
0	1	Covered	T48,T50,T154
1	0	Covered	T12

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T48,T50
1	-	Covered	T48,T50,T154

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T48,T55
DetectSt	168	Covered	T12,T48,T50
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T48,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T48,T50
DebounceSt->IdleSt	163	Covered	T55,T159
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T48,T50
IdleSt->DebounceSt	148	Covered	T12,T48,T55
StableSt->IdleSt	206	Covered	T12,T48,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T48,T55
0	1	Covered	T12,T48,T55
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T48,T50
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T48,T55
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T48,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T48,T55
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T48,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T48,T50
StableSt	-	-	-	-	-	-	0	Covered	T12,T48,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	44	0	0
CntIncr_A	7365022	33355	0	0
CntNoWrap_A	7365022	6893600	0	0
DetectStDropOut_A	7365022	0	0	0
DetectedOut_A	7365022	95647	0	0
DetectedPulseOut_A	7365022	21	0	0
DisabledIdleSt_A	7365022	6716307	0	0
DisabledNoDetection_A	7365022	6718133	0	0
EnterDebounceSt_A	7365022	23	0	0
EnterDetectSt_A	7365022	21	0	0
EnterStableSt_A	7365022	21	0	0
PulseIsPulse_A	7365022	21	0	0
StayInStableSt	7365022	95620	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7365022	5321	0	0
gen_low_level_sva.LowLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	44	0	0
T12	7268	2	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	2	0	0
T50	0	4	0	0
T51	0	2	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	2	0	0
T160	0	2	0	0
T179	0	4	0	0
T181	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	33355	0	0
T12	7268	15	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	97	0	0
T50	0	36	0	0
T51	0	46	0	0
T55	0	27	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	88	0	0
T160	0	54	0	0
T179	0	164	0	0
T181	0	36	0	0
T183	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6893600	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	95647	0	0
T12	7268	20	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	160	0	0
T50	0	83	0	0
T51	0	86	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	131	0	0
T160	0	244	0	0
T164	0	16	0	0
T179	0	51	0	0
T181	0	43	0	0
T183	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	21	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T179	0	2	0	0
T181	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6716307	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6718133	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	23	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	1	0	0
T160	0	1	0	0
T179	0	2	0	0
T181	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	21	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T179	0	2	0	0
T181	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	21	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T179	0	2	0	0
T181	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	21	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T179	0	2	0	0
T181	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	95620	0	0
T12	7268	19	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T48	0	159	0	0
T50	0	80	0	0
T51	0	84	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T154	0	130	0	0
T160	0	243	0	0
T164	0	15	0	0
T179	0	49	0	0
T181	0	42	0	0
T183	0	49	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	5321	0	0
T2	483	0	0	0
T3	709	0	0	0
T4	447	3	0	0
T5	496	7	0	0
T6	0	7	0	0
T13	422	3	0	0
T14	523	3	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	1	0	0
T18	497	10	0	0
T26	0	4	0	0
T65	0	3	0	0
T74	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	14	0	0
T30	5171	0	0	0
T48	1201	1	0	0
T50	0	1	0	0
T59	2117	0	0	0
T81	494	0	0	0
T148	0	2	0	0
T154	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T179	0	2	0	0
T181	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	505	0	0	0
T202	523	0	0	0
T203	449	0	0	0
T204	598	0	0	0
T205	749	0	0	0
T206	409	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T5 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T12 T45 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T12 T45 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T12 T45 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T12 T45 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T12 T45 
163        1/1                    state_d = IdleSt;
           Tests:       T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T12 T45 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T12 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T12 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T12 T45 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T194 T207 T183 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T12 T45 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T12 T45 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T12 T45 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T12 T45 
191        1/1                      state_d = StableSt;
           Tests:       T11 T12 T45 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T12 T45 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T12 T45 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T12 T45 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T12 T45 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T12 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T12 T45 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T12,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T12,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T12,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T45
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T12,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T45
0	1	Covered	T11,T45,T52
1	0	Covered	T12

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T45
1	-	Covered	T11,T45,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T45
DetectSt	168	Covered	T11,T12,T45
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T12,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T45
DebounceSt->IdleSt	163	Covered	T55,T194,T207
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T12,T45
IdleSt->DebounceSt	148	Covered	T11,T12,T45
StableSt->IdleSt	206	Covered	T11,T12,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T45
0	1	Covered	T11,T12,T45
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T45
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T194,T207,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	76	0	0
CntIncr_A	7365022	2314	0	0
CntNoWrap_A	7365022	6893568	0	0
DetectStDropOut_A	7365022	0	0	0
DetectedOut_A	7365022	3192	0	0
DetectedPulseOut_A	7365022	35	0	0
DisabledIdleSt_A	7365022	6882994	0	0
DisabledNoDetection_A	7365022	6884821	0	0
EnterDebounceSt_A	7365022	41	0	0
EnterDetectSt_A	7365022	35	0	0
EnterStableSt_A	7365022	35	0	0
PulseIsPulse_A	7365022	35	0	0
StayInStableSt	7365022	3144	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	76	0	0
T11	694	2	0	0
T12	7268	2	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	2	0	0
T47	0	2	0	0
T50	0	4	0	0
T51	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	2314	0	0
T11	694	42	0	0
T12	7268	15	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	95	0	0
T47	0	30	0	0
T50	0	36	0	0
T51	0	46	0	0
T52	0	25	0	0
T54	0	11	0	0
T55	0	28	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6893568	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	3192	0	0
T11	694	82	0	0
T12	7268	20	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	204	0	0
T47	0	122	0	0
T50	0	53	0	0
T51	0	175	0	0
T52	0	68	0	0
T54	0	53	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	38	0	0
T178	0	391	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T11	694	1	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6882994	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6884821	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	41	0	0
T11	694	1	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T11	694	1	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T11	694	1	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	35	0	0
T11	694	1	0	0
T12	7268	1	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	3144	0	0
T11	694	81	0	0
T12	7268	19	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	203	0	0
T47	0	120	0	0
T50	0	50	0	0
T51	0	173	0	0
T52	0	67	0	0
T54	0	52	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T124	0	36	0	0
T178	0	390	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	21	0	0
T11	694	1	0	0
T12	7268	0	0	0
T27	683	0	0	0
T28	705	0	0	0
T29	471	0	0	0
T45	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	453	0	0	0
T66	448	0	0	0
T67	404	0	0	0
T88	523	0	0	0
T103	1311	0	0	0
T163	0	2	0	0
T178	0	1	0	0
T179	0	1	0	0
T181	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T5 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T12 T48 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T12 T48 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T12 T48 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T12 T48 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T12 T48 
163        1/1                    state_d = IdleSt;
           Tests:       T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T12 T48 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T12 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T12 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T12 T48 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T12 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T12 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T12 T48 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T12 T48 
191        1/1                      state_d = StableSt;
           Tests:       T3 T12 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T12 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T12 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T12 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T12 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T48 T179 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T12 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T12,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T12,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T12,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T12
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T12,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T48
0	1	Covered	T48,T179,T181
1	0	Covered	T12

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T48
1	-	Covered	T48,T179,T181

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T48
DetectSt	168	Covered	T3,T12,T48
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T12,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T48
DebounceSt->IdleSt	163	Covered	T55
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T12,T48
IdleSt->DebounceSt	148	Covered	T3,T12,T48
StableSt->IdleSt	206	Covered	T12,T48,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T12,T48
0	1	Covered	T3,T12,T48
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T48
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T48
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T48
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T48,T179
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	37	0	0
CntIncr_A	7365022	869	0	0
CntNoWrap_A	7365022	6893607	0	0
DetectStDropOut_A	7365022	0	0	0
DetectedOut_A	7365022	1312	0	0
DetectedPulseOut_A	7365022	18	0	0
DisabledIdleSt_A	7365022	6719561	0	0
DisabledNoDetection_A	7365022	6721391	0	0
EnterDebounceSt_A	7365022	19	0	0
EnterDetectSt_A	7365022	18	0	0
EnterStableSt_A	7365022	18	0	0
PulseIsPulse_A	7365022	18	0	0
StayInStableSt	7365022	1282	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7365022	4967	0	0
gen_low_level_sva.LowLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	5	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	37	0	0
T3	709	2	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	2	0	0
T26	502	0	0	0
T48	0	4	0	0
T49	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T55	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	4	0	0
T180	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	869	0	0
T3	709	53	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	15	0	0
T26	502	0	0	0
T48	0	194	0	0
T49	0	27	0	0
T52	0	25	0	0
T53	0	11	0	0
T55	0	28	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	164	0	0
T180	0	56	0	0
T194	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6893607	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1312	0	0
T3	709	41	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	19	0	0
T26	502	0	0	0
T48	0	346	0	0
T49	0	44	0	0
T52	0	42	0	0
T53	0	40	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	178	0	0
T180	0	40	0	0
T181	0	80	0	0
T194	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	18	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	1	0	0
T26	502	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6719561	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6721391	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	19	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	1	0	0
T26	502	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	2	0	0
T180	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	18	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	1	0	0
T26	502	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	18	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	1	0	0
T26	502	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	18	0	0
T3	709	1	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	1	0	0
T26	502	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1282	0	0
T3	709	39	0	0
T6	1143	0	0	0
T8	507	0	0	0
T9	484	0	0	0
T12	0	18	0	0
T26	502	0	0	0
T48	0	343	0	0
T49	0	42	0	0
T52	0	40	0	0
T53	0	38	0	0
T64	402	0	0	0
T65	422	0	0	0
T74	502	0	0	0
T75	523	0	0	0
T76	441	0	0	0
T179	0	176	0	0
T180	0	38	0	0
T181	0	79	0	0
T194	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	4967	0	0
T1	505	1	0	0
T2	483	1	0	0
T3	0	1	0	0
T4	447	5	0	0
T5	496	7	0	0
T13	422	2	0	0
T14	523	3	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	1	0	0
T18	497	8	0	0
T26	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	5	0	0
T30	5171	0	0	0
T48	1201	1	0	0
T59	2117	0	0	0
T81	494	0	0	0
T179	0	2	0	0
T181	0	1	0	0
T201	505	0	0	0
T202	523	0	0	0
T203	449	0	0	0
T204	598	0	0	0
T205	749	0	0	0
T206	409	0	0	0
T208	0	1	0	0