Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T39
0	1	Covered	T2,T39,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T39
1	-	Covered	T2,T39,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T39
DetectSt	168	Covered	T2,T7,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T39
DebounceSt->IdleSt	163	Covered	T73,T158,T74
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T7,T39
IdleSt->DebounceSt	148	Covered	T2,T7,T39
StableSt->IdleSt	206	Covered	T2,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T39
0	1	Covered	T2,T7,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T158
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T39,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	89	0	0
CntIncr_A	8184812	2011	0	0
CntNoWrap_A	8184812	7524853	0	0
DetectStDropOut_A	8184812	0	0	0
DetectedOut_A	8184812	2812	0	0
DetectedPulseOut_A	8184812	43	0	0
DisabledIdleSt_A	8184812	7392599	0	0
DisabledNoDetection_A	8184812	7394985	0	0
EnterDebounceSt_A	8184812	46	0	0
EnterDetectSt_A	8184812	43	0	0
EnterStableSt_A	8184812	43	0	0
PulseIsPulse_A	8184812	43	0	0
StayInStableSt	8184812	2747	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	89	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	4	0	0
T39	0	6	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T137	0	2	0	0
T138	0	4	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2011	0	0
T2	14635	11	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	81	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	154	0	0
T39	0	54	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	39	0	0
T137	0	25	0	0
T138	0	86	0	0
T158	0	58	0	0
T159	0	67	0	0
T160	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524853	0	0
T1	32514	32087	0	0
T2	14635	2995	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2812	0	0
T2	14635	6	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	127	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	79	0	0
T39	0	127	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	75	0	0
T138	0	128	0	0
T157	0	79	0	0
T159	0	41	0	0
T160	0	151	0	0
T161	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	2	0	0
T39	0	3	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	1	0	0
T138	0	2	0	0
T157	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7392599	0	0
T1	32514	32087	0	0
T2	14635	2785	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7394985	0	0
T1	32514	32101	0	0
T2	14635	2813	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	46	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	2	0	0
T39	0	3	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	2	0	0
T39	0	3	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	1	0	0
T138	0	2	0	0
T157	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	2	0	0
T39	0	3	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	1	0	0
T138	0	2	0	0
T157	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	2	0	0
T39	0	3	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	1	0	0
T138	0	2	0	0
T157	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2747	0	0
T2	14635	5	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	125	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	77	0	0
T39	0	123	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	73	0	0
T138	0	125	0	0
T157	0	76	0	0
T159	0	39	0	0
T160	0	149	0	0
T161	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	21	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T113	0	1	0	0
T138	0	1	0	0
T151	0	2	0	0
T157	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T9,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T9,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T38
0	1	Covered	T148
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T38
0	1	Covered	T2,T38,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T38
1	-	Covered	T2,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T38
DetectSt	168	Covered	T2,T9,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T38
DebounceSt->IdleSt	163	Covered	T39,T136,T73
DetectSt->IdleSt	186	Covered	T148
DetectSt->StableSt	191	Covered	T2,T9,T38
IdleSt->DebounceSt	148	Covered	T2,T9,T38
StableSt->IdleSt	206	Covered	T2,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T38
0	1	Covered	T2,T9,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T136,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T38
DetectSt	-	-	-	-	1	-	-	Covered	T148
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	120	0	0
CntIncr_A	8184812	103648	0	0
CntNoWrap_A	8184812	7524822	0	0
DetectStDropOut_A	8184812	1	0	0
DetectedOut_A	8184812	4810	0	0
DetectedPulseOut_A	8184812	55	0	0
DisabledIdleSt_A	8184812	6980144	0	0
DisabledNoDetection_A	8184812	6982530	0	0
EnterDebounceSt_A	8184812	64	0	0
EnterDetectSt_A	8184812	56	0	0
EnterStableSt_A	8184812	55	0	0
PulseIsPulse_A	8184812	55	0	0
StayInStableSt	8184812	4732	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	2965	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	120	0	0
T2	14635	4	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	6	0	0
T38	0	2	0	0
T39	0	5	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T102	0	2	0	0
T103	0	2	0	0
T136	0	5	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	103648	0	0
T2	14635	22	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	17	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	231	0	0
T38	0	74	0	0
T39	0	54	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	38	0	0
T102	0	58	0	0
T103	0	37	0	0
T136	0	240	0	0
T153	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524822	0	0
T1	32514	32087	0	0
T2	14635	2993	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1	0	0
T94	21180	0	0	0
T148	820	1	0	0
T166	503	0	0	0
T167	418	0	0	0
T168	18482	0	0	0
T169	654	0	0	0
T170	8898	0	0	0
T171	23938	0	0	0
T172	29764	0	0	0
T173	748	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	4810	0	0
T2	14635	90	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	117	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	295	0	0
T38	0	132	0	0
T39	0	21	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	50	0	0
T103	0	184	0	0
T136	0	58	0	0
T153	0	110	0	0
T155	0	123	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	55	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0
T136	0	2	0	0
T153	0	1	0	0
T155	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6980144	0	0
T1	32514	32087	0	0
T2	14635	2785	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6982530	0	0
T1	32514	32101	0	0
T2	14635	2813	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	64	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	3	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T136	0	3	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	56	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0
T136	0	2	0	0
T153	0	1	0	0
T155	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	55	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0
T136	0	2	0	0
T153	0	1	0	0
T155	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	55	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0
T136	0	2	0	0
T153	0	1	0	0
T155	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	4732	0	0
T2	14635	87	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T9	0	115	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	291	0	0
T38	0	131	0	0
T39	0	19	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	48	0	0
T103	0	182	0	0
T136	0	55	0	0
T153	0	108	0	0
T155	0	120	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2965	0	0
T1	32514	0	0	0
T2	14635	46	0	0
T3	0	25	0	0
T4	492	5	0	0
T5	551	3	0	0
T13	422	2	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	6	0	0
T17	495	4	0	0
T18	503	6	0	0
T19	0	6	0	0
T20	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	32	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0
T150	0	1	0	0
T155	0	1	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T38
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T7,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T38
0	1	Covered	T80,T81,T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T38
0	1	Covered	T2,T7,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T38
1	-	Covered	T2,T7,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T38
DetectSt	168	Covered	T2,T7,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T38
DebounceSt->IdleSt	163	Covered	T73,T80,T148
DetectSt->IdleSt	186	Covered	T80,T81,T152
DetectSt->StableSt	191	Covered	T2,T7,T38
IdleSt->DebounceSt	148	Covered	T2,T7,T38
StableSt->IdleSt	206	Covered	T2,T7,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T38
0	1	Covered	T2,T7,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T148,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T38
DetectSt	-	-	-	-	1	-	-	Covered	T80,T81,T152
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T38
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	122	0	0
CntIncr_A	8184812	152949	0	0
CntNoWrap_A	8184812	7524820	0	0
DetectStDropOut_A	8184812	6	0	0
DetectedOut_A	8184812	61399	0	0
DetectedPulseOut_A	8184812	51	0	0
DisabledIdleSt_A	8184812	7013283	0	0
DisabledNoDetection_A	8184812	7015667	0	0
EnterDebounceSt_A	8184812	65	0	0
EnterDetectSt_A	8184812	57	0	0
EnterStableSt_A	8184812	51	0	0
PulseIsPulse_A	8184812	51	0	0
StayInStableSt	8184812	61328	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	122	0	0
T2	14635	4	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	4	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	3	0	0
T137	0	2	0	0
T148	0	3	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	152949	0	0
T2	14635	22	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	162	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	138	0	0
T38	0	148	0	0
T41	0	53	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	39	0	0
T80	0	60	0	0
T137	0	25	0	0
T148	0	100	0	0
T155	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524820	0	0
T1	32514	32087	0	0
T2	14635	2993	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6	0	0
T77	6012	0	0	0
T80	34822	1	0	0
T81	0	1	0	0
T89	5320	0	0	0
T118	11955	0	0	0
T135	0	1	0	0
T152	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	15444	0	0	0
T177	490	0	0	0
T178	14075	0	0	0
T179	727	0	0	0
T180	1261	0	0	0
T181	24218	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	61399	0	0
T2	14635	57	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	168	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	226	0	0
T38	0	56	0	0
T41	0	46	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	42	0	0
T148	0	16	0	0
T155	0	1	0	0
T156	0	56844	0	0
T160	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	51	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	1	0	0
T148	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7013283	0	0
T1	32514	32087	0	0
T2	14635	2785	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7015667	0	0
T1	32514	32101	0	0
T2	14635	2813	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	65	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	2	0	0
T137	0	1	0	0
T148	0	2	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	57	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T137	0	1	0	0
T148	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	51	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	1	0	0
T148	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	51	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	1	0	0
T148	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	61328	0	0
T2	14635	55	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	165	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	223	0	0
T38	0	53	0	0
T41	0	45	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T137	0	40	0	0
T148	0	15	0	0
T156	0	56843	0	0
T160	0	80	0	0
T161	0	58	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	31	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T41
0	1	Covered	T2,T40,T148
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T40,T41
1	-	Covered	T2,T40,T148

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T40,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T40,T41
DebounceSt->IdleSt	163	Covered	T3,T7,T73
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T40,T41
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T40,T148

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T40,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T40,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T7
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T148
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	74	0	0
CntIncr_A	8184812	79215	0	0
CntNoWrap_A	8184812	7524868	0	0
DetectStDropOut_A	8184812	0	0	0
DetectedOut_A	8184812	83268	0	0
DetectedPulseOut_A	8184812	35	0	0
DisabledIdleSt_A	8184812	7100121	0	0
DisabledNoDetection_A	8184812	7102512	0	0
EnterDebounceSt_A	8184812	40	0	0
EnterDetectSt_A	8184812	35	0	0
EnterStableSt_A	8184812	35	0	0
PulseIsPulse_A	8184812	35	0	0
StayInStableSt	8184812	83214	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	6461	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	74	0	0
T2	14635	4	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	4	0	0
T41	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T81	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	79215	0	0
T2	14635	22	0	0
T3	11546	30	0	0
T6	31846	0	0	0
T7	0	81	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	164	0	0
T41	0	53	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	38	0	0
T148	0	100	0	0
T149	0	42	0	0
T155	0	72	0	0
T156	0	2374	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524868	0	0
T1	32514	32087	0	0
T2	14635	2993	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	83268	0	0
T2	14635	88	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	81	0	0
T41	0	39	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T81	0	42	0	0
T113	0	48	0	0
T148	0	192	0	0
T149	0	205	0	0
T151	0	290	0	0
T155	0	41	0	0
T182	0	190	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	35	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T81	0	1	0	0
T113	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	2	0	0
T155	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7100121	0	0
T1	32514	32087	0	0
T2	14635	2785	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7102512	0	0
T1	32514	32101	0	0
T2	14635	2813	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	40	0	0
T2	14635	2	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	35	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T81	0	1	0	0
T113	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	2	0	0
T155	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	35	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T81	0	1	0	0
T113	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	2	0	0
T155	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	35	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T81	0	1	0	0
T113	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T151	0	2	0	0
T155	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	83214	0	0
T2	14635	85	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	78	0	0
T41	0	37	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T81	0	40	0	0
T113	0	46	0	0
T148	0	189	0	0
T149	0	203	0	0
T151	0	288	0	0
T155	0	39	0	0
T182	0	189	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6461	0	0
T1	32514	15	0	0
T2	14635	48	0	0
T3	0	31	0	0
T4	492	7	0	0
T5	551	0	0	0
T13	422	3	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	6	0	0
T18	503	6	0	0
T19	0	10	0	0
T20	0	3	0	0
T43	0	16	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	16	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T140	0	1	0	0
T148	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Covered	T152,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Covered	T2,T3,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T38
1	-	Covered	T2,T3,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T9
DetectSt	168	Covered	T2,T3,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T3,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T38
DebounceSt->IdleSt	163	Covered	T9,T103,T73
DetectSt->IdleSt	186	Covered	T152,T186
DetectSt->StableSt	191	Covered	T2,T3,T38
IdleSt->DebounceSt	148	Covered	T2,T3,T9
StableSt->IdleSt	206	Covered	T2,T3,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T103,T113
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T152,T186
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T38
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	111	0	0
CntIncr_A	8184812	59674	0	0
CntNoWrap_A	8184812	7524831	0	0
DetectStDropOut_A	8184812	2	0	0
DetectedOut_A	8184812	60802	0	0
DetectedPulseOut_A	8184812	50	0	0
DisabledIdleSt_A	8184812	7359624	0	0
DisabledNoDetection_A	8184812	7362019	0	0
EnterDebounceSt_A	8184812	60	0	0
EnterDetectSt_A	8184812	52	0	0
EnterStableSt_A	8184812	50	0	0
PulseIsPulse_A	8184812	50	0	0
StayInStableSt	8184812	60733	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	111	0	0
T2	14635	8	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	4	0	0
T103	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	59674	0	0
T2	14635	56	0	0
T3	11546	30	0	0
T6	31846	0	0	0
T9	0	17	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	24	0	0
T37	0	69	0	0
T38	0	148	0	0
T39	0	18	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	38	0	0
T80	0	60	0	0
T103	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524831	0	0
T1	32514	32087	0	0
T2	14635	2989	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2	0	0
T152	705	1	0	0
T186	0	1	0	0
T187	60780	0	0	0
T188	3028	0	0	0
T189	814	0	0	0
T190	408	0	0	0
T191	502	0	0	0
T192	15102	0	0	0
T193	428	0	0	0
T194	503	0	0	0
T195	19796	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60802	0	0
T2	14635	160	0	0
T3	11546	55	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	44	0	0
T37	0	163	0	0
T38	0	79	0	0
T39	0	77	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	117	0	0
T103	0	39	0	0
T137	0	41	0	0
T138	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	50	0	0
T2	14635	4	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7359624	0	0
T1	32514	32087	0	0
T2	14635	2541	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7362019	0	0
T1	32514	32101	0	0
T2	14635	2568	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60	0	0
T2	14635	4	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	2	0	0
T103	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	52	0	0
T2	14635	4	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	50	0	0
T2	14635	4	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	50	0	0
T2	14635	4	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60733	0	0
T2	14635	156	0	0
T3	11546	54	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	43	0	0
T37	0	162	0	0
T38	0	76	0	0
T39	0	76	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	114	0	0
T103	0	37	0	0
T137	0	40	0	0
T138	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	31	0	0
T2	14635	4	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T35,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T35,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T35,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T35,T39
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T35,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T35,T39
0	1	Covered	T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T35,T39
0	1	Covered	T36,T103,T80
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T35,T39
1	-	Covered	T36,T103,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T35,T39
DetectSt	168	Covered	T2,T35,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T35,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T35,T39
DebounceSt->IdleSt	163	Covered	T2,T73,T155
DetectSt->IdleSt	186	Covered	T196
DetectSt->StableSt	191	Covered	T2,T35,T39
IdleSt->DebounceSt	148	Covered	T2,T35,T39
StableSt->IdleSt	206	Covered	T2,T36,T103

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T35,T39
0	1	Covered	T2,T35,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T35,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T35,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T35,T39
DetectSt	-	-	-	-	1	-	-	Covered	T196
DetectSt	-	-	-	-	0	1	-	Covered	T2,T35,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T103,T80
StableSt	-	-	-	-	-	-	0	Covered	T2,T35,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	82	0	0
CntIncr_A	8184812	2063	0	0
CntNoWrap_A	8184812	7524860	0	0
DetectStDropOut_A	8184812	1	0	0
DetectedOut_A	8184812	3378	0	0
DetectedPulseOut_A	8184812	38	0	0
DisabledIdleSt_A	8184812	7354244	0	0
DisabledNoDetection_A	8184812	7356631	0	0
EnterDebounceSt_A	8184812	43	0	0
EnterDetectSt_A	8184812	39	0	0
EnterStableSt_A	8184812	38	0	0
PulseIsPulse_A	8184812	38	0	0
StayInStableSt	8184812	3318	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	6078	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	82	0	0
T2	14635	3	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	2	0	0
T103	0	2	0	0
T155	0	1	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2063	0	0
T2	14635	34	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	16	0	0
T36	0	77	0	0
T39	0	18	0	0
T40	0	82	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	38	0	0
T80	0	30	0	0
T103	0	37	0	0
T155	0	72	0	0
T159	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524860	0	0
T1	32514	32087	0	0
T2	14635	2994	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1	0	0
T83	948	0	0	0
T196	6797	1	0	0
T197	8402	0	0	0
T198	1336	0	0	0
T199	877	0	0	0
T200	1461	0	0	0
T201	502	0	0	0
T202	402	0	0	0
T203	505	0	0	0
T204	14381	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	3378	0	0
T2	14635	79	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	40	0	0
T36	0	49	0	0
T39	0	69	0	0
T40	0	168	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	84	0	0
T103	0	107	0	0
T159	0	41	0	0
T160	0	84	0	0
T205	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7354244	0	0
T1	32514	32087	0	0
T2	14635	2753	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7356631	0	0
T1	32514	32101	0	0
T2	14635	2781	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	1	0	0
T103	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	39	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	3318	0	0
T2	14635	77	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	38	0	0
T36	0	48	0	0
T39	0	67	0	0
T40	0	166	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	83	0	0
T103	0	106	0	0
T159	0	39	0	0
T160	0	81	0	0
T205	0	53	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6078	0	0
T1	32514	7	0	0
T2	14635	53	0	0
T3	0	31	0	0
T4	492	6	0	0
T5	551	0	0	0
T13	422	2	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	7	0	0
T18	503	6	0	0
T19	0	8	0	0
T20	0	4	0	0
T43	0	19	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	16	0	0
T36	3051	1	0	0
T37	976	0	0	0
T59	6493	0	0	0
T66	16087	0	0	0
T71	44971	0	0	0
T80	0	1	0	0
T99	768	0	0	0
T103	0	1	0	0
T107	40216	0	0	0
T113	0	1	0	0
T151	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	1298	0	0	0
T210	633	0	0	0
T211	417	0	0	0