dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.92 91.67 81.25 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.00 91.67 81.25 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 95.83 87.50 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T19,T98
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T19,T98

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T19,T98

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T19,T98
10CoveredT6,T21,T34
11CoveredT6,T19,T98

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T19,T98
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T19,T98
01CoveredT98,T105,T85
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T19,T98
1-CoveredT98,T105,T85

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T19,T98
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T19,T98
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T19,T98
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T19,T98
DebounceSt - 0 1 0 - - - Covered T57,T109,T38
DebounceSt - 0 0 - - - - Covered T6,T19,T98
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T19,T98
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T98,T105,T85
StableSt - - - - - - 0 Covered T6,T19,T98
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3355686 0 0
CntIncr_A 3964510 122131 0 0
CntNoWrap_A 3964510 122131 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 30956 0 0
DetectedPulseOut_A 3964510 19 0 0
DisabledIdleSt_A 3964510 3126212 0 0
DisabledNoDetection_A 3964510 3127460 0 0
EnterDebounceSt_A 3964510 27 0 0
EnterDetectSt_A 3964510 19 0 0
EnterStableSt_A 3964510 19 0 0
PulseIsPulse_A 3964510 19 0 0
StayInStableSt 3964510 30929 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 11 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3355686 0 0
T6 64351 61918 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 468 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 122131 0 0
T6 64351 27 0 0
T19 963 94 0 0
T38 10871 144 0 0
T57 3273 172 0 0
T85 14254 41 0 0
T93 539 36 0 0
T98 559 30 0 0
T103 951 99 0 0
T105 592 52 0 0
T109 507 20 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 122131 0 0
T6 64351 27 0 0
T19 963 94 0 0
T38 10871 144 0 0
T57 3273 172 0 0
T85 14254 41 0 0
T93 539 36 0 0
T98 559 30 0 0
T103 951 99 0 0
T105 592 52 0 0
T109 507 20 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 30956 0 0
T6 64351 38 0 0
T19 963 219 0 0
T38 10871 42 0 0
T57 3273 37 0 0
T85 14254 124 0 0
T93 539 83 0 0
T98 559 43 0 0
T103 951 160 0 0
T104 157503 12820 0 0
T105 592 112 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T6 64351 1 0 0
T19 963 1 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T93 539 2 0 0
T98 559 2 0 0
T103 951 1 0 0
T104 157503 1 0 0
T105 592 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3126212 0 0
T6 64351 61762 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 3 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3127460 0 0
T6 64351 61767 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 3 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 27 0 0
T6 64351 1 0 0
T19 963 1 0 0
T38 10871 2 0 0
T57 3273 2 0 0
T85 14254 1 0 0
T93 539 2 0 0
T98 559 2 0 0
T103 951 1 0 0
T105 592 2 0 0
T109 507 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T6 64351 1 0 0
T19 963 1 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T93 539 2 0 0
T98 559 2 0 0
T103 951 1 0 0
T104 157503 1 0 0
T105 592 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T6 64351 1 0 0
T19 963 1 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T93 539 2 0 0
T98 559 2 0 0
T103 951 1 0 0
T104 157503 1 0 0
T105 592 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T6 64351 1 0 0
T19 963 1 0 0
T38 10871 1 0 0
T57 3273 1 0 0
T85 14254 1 0 0
T93 539 2 0 0
T98 559 2 0 0
T103 951 1 0 0
T104 157503 1 0 0
T105 592 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 30929 0 0
T6 64351 36 0 0
T19 963 217 0 0
T38 10871 40 0 0
T57 3273 35 0 0
T85 14254 123 0 0
T93 539 80 0 0
T98 559 40 0 0
T103 951 159 0 0
T104 157503 12819 0 0
T105 592 109 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 11 0 0
T85 14254 1 0 0
T93 539 1 0 0
T95 907 1 0 0
T98 559 1 0 0
T100 668 1 0 0
T103 951 1 0 0
T104 157503 1 0 0
T105 592 1 0 0
T113 531 1 0 0
T114 631 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT20,T109,T105
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT20,T109,T105

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT109,T88,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T20,T110
10CoveredT6,T21,T34
11CoveredT20,T109,T105

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT109,T88,T85
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT109,T88,T85
01CoveredT109,T38,T104
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT109,T88,T85
1-CoveredT109,T38,T104

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T20,T109,T105
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T109,T88,T85
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T20,T109,T105
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T109,T88,T85
DebounceSt - 0 1 0 - - - Covered T20,T105
DebounceSt - 0 0 - - - - Covered T20,T109,T105
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T109,T88,T85
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T109,T38,T104
StableSt - - - - - - 0 Covered T109,T88,T85
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3399392 0 0
CntIncr_A 3964510 78425 0 0
CntNoWrap_A 3964510 78425 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 772 0 0
DetectedPulseOut_A 3964510 13 0 0
DisabledIdleSt_A 3964510 2995562 0 0
DisabledNoDetection_A 3964510 2996810 0 0
EnterDebounceSt_A 3964510 15 0 0
EnterDetectSt_A 3964510 13 0 0
EnterStableSt_A 3964510 13 0 0
PulseIsPulse_A 3964510 13 0 0
StayInStableSt 3964510 751 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 3208 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 5 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3399392 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78425 0 0
T20 3758 50 0 0
T38 10871 72 0 0
T85 14254 41 0 0
T88 5876 83 0 0
T90 623 39 0 0
T102 748 92 0 0
T104 157503 77870 0 0
T105 592 26 0 0
T109 507 20 0 0
T114 631 74 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78425 0 0
T20 3758 50 0 0
T38 10871 72 0 0
T85 14254 41 0 0
T88 5876 83 0 0
T90 623 39 0 0
T102 748 92 0 0
T104 157503 77870 0 0
T105 592 26 0 0
T109 507 20 0 0
T114 631 74 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 772 0 0
T38 10871 35 0 0
T85 14254 35 0 0
T88 5876 201 0 0
T90 623 94 0 0
T97 2538 35 0 0
T102 748 35 0 0
T104 157503 70 0 0
T109 507 70 0 0
T112 624 126 0 0
T114 631 71 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T97 2538 1 0 0
T102 748 1 0 0
T104 157503 2 0 0
T109 507 2 0 0
T112 624 1 0 0
T114 631 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2995562 0 0
T6 64351 61634 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2996810 0 0
T6 64351 61639 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 15 0 0
T20 3758 1 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T102 748 1 0 0
T104 157503 2 0 0
T105 592 1 0 0
T109 507 2 0 0
T114 631 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T97 2538 1 0 0
T102 748 1 0 0
T104 157503 2 0 0
T109 507 2 0 0
T112 624 1 0 0
T114 631 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T97 2538 1 0 0
T102 748 1 0 0
T104 157503 2 0 0
T109 507 2 0 0
T112 624 1 0 0
T114 631 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13 0 0
T38 10871 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T97 2538 1 0 0
T102 748 1 0 0
T104 157503 2 0 0
T109 507 2 0 0
T112 624 1 0 0
T114 631 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 751 0 0
T38 10871 34 0 0
T85 14254 33 0 0
T88 5876 199 0 0
T90 623 92 0 0
T97 2538 34 0 0
T102 748 33 0 0
T104 157503 67 0 0
T109 507 67 0 0
T112 624 124 0 0
T114 631 68 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3208 0 0
T6 64351 5 0 0
T21 482 9 0 0
T30 1872 14 0 0
T34 524 3 0 0
T35 524 6 0 0
T36 502 5 0 0
T49 446 10 0 0
T75 422 4 0 0
T76 423 5 0 0
T77 410 1 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 5 0 0
T38 10871 1 0 0
T97 2538 1 0 0
T104 157503 1 0 0
T109 507 1 0 0
T114 631 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T45,T98
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T45,T98

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T45,T98

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T45,T98
10CoveredT6,T21,T34
11CoveredT6,T45,T98

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T45,T98
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T45,T98
01CoveredT6,T45,T88
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T45,T98
1-CoveredT6,T45,T88

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T45,T98
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T45,T98
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T45,T98
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T45,T98
DebounceSt - 0 1 0 - - - Covered T112
DebounceSt - 0 0 - - - - Covered T6,T45,T98
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T45,T98
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T6,T45,T88
StableSt - - - - - - 0 Covered T6,T45,T98
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3312626 0 0
CntIncr_A 3964510 165191 0 0
CntNoWrap_A 3964510 165191 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 62326 0 0
DetectedPulseOut_A 3964510 24 0 0
DisabledIdleSt_A 3964510 3125925 0 0
DisabledNoDetection_A 3964510 3127172 0 0
EnterDebounceSt_A 3964510 25 0 0
EnterDetectSt_A 3964510 24 0 0
EnterStableSt_A 3964510 24 0 0
PulseIsPulse_A 3964510 24 0 0
StayInStableSt 3964510 62291 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 13 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3312626 0 0
T6 64351 61891 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 165191 0 0
T6 64351 54 0 0
T43 6768 122 0 0
T45 852 184 0 0
T85 14254 41 0 0
T88 5876 83 0 0
T92 566 22 0 0
T93 539 18 0 0
T98 559 15 0 0
T99 537 19 0 0
T106 1935 12 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 165191 0 0
T6 64351 54 0 0
T43 6768 122 0 0
T45 852 184 0 0
T85 14254 41 0 0
T88 5876 83 0 0
T92 566 22 0 0
T93 539 18 0 0
T98 559 15 0 0
T99 537 19 0 0
T106 1935 12 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 62326 0 0
T6 64351 62 0 0
T43 6768 151 0 0
T45 852 80 0 0
T85 14254 35 0 0
T88 5876 35 0 0
T92 566 137 0 0
T93 539 48 0 0
T98 559 63 0 0
T99 537 111 0 0
T106 1935 41 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T6 64351 2 0 0
T43 6768 2 0 0
T45 852 2 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T98 559 1 0 0
T99 537 1 0 0
T106 1935 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3125925 0 0
T6 64351 61762 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3127172 0 0
T6 64351 61767 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 25 0 0
T6 64351 2 0 0
T43 6768 2 0 0
T45 852 2 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T98 559 1 0 0
T99 537 1 0 0
T106 1935 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T6 64351 2 0 0
T43 6768 2 0 0
T45 852 2 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T98 559 1 0 0
T99 537 1 0 0
T106 1935 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T6 64351 2 0 0
T43 6768 2 0 0
T45 852 2 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T98 559 1 0 0
T99 537 1 0 0
T106 1935 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T6 64351 2 0 0
T43 6768 2 0 0
T45 852 2 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T92 566 1 0 0
T93 539 1 0 0
T98 559 1 0 0
T99 537 1 0 0
T106 1935 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 62291 0 0
T6 64351 59 0 0
T43 6768 148 0 0
T45 852 77 0 0
T85 14254 34 0 0
T88 5876 34 0 0
T92 566 135 0 0
T93 539 47 0 0
T98 559 61 0 0
T99 537 109 0 0
T106 1935 40 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13 0 0
T6 64351 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T93 539 1 0 0
T94 850 1 0 0
T103 951 1 0 0
T104 157503 1 0 0
T106 1935 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT19,T20,T85
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT19,T20,T85

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT19,T20,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T19,T20
10CoveredT6,T21,T34
11CoveredT19,T20,T85

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT19,T20,T85
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT19,T20,T85
01CoveredT19,T90,T94
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT19,T20,T85
1-CoveredT19,T90,T94

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T19,T20,T85
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T19,T20,T85
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T19,T20,T85
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T19,T20,T85
DebounceSt - 0 1 0 - - - Covered T104
DebounceSt - 0 0 - - - - Covered T19,T20,T85
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T19,T20,T85
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T19,T90,T94
StableSt - - - - - - 0 Covered T19,T20,T85
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3438206 0 0
CntIncr_A 3964510 39611 0 0
CntNoWrap_A 3964510 39611 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 661 0 0
DetectedPulseOut_A 3964510 10 0 0
DisabledIdleSt_A 3964510 3315564 0 0
DisabledNoDetection_A 3964510 3316811 0 0
EnterDebounceSt_A 3964510 11 0 0
EnterDetectSt_A 3964510 10 0 0
EnterStableSt_A 3964510 10 0 0
PulseIsPulse_A 3964510 10 0 0
StayInStableSt 3964510 645 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 3175 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 4 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3438206 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 468 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 39611 0 0
T19 963 94 0 0
T20 3758 50 0 0
T85 14254 77 0 0
T90 623 39 0 0
T94 850 90 0 0
T95 907 94 0 0
T102 748 92 0 0
T103 951 99 0 0
T104 157503 38935 0 0
T112 624 41 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 39611 0 0
T19 963 94 0 0
T20 3758 50 0 0
T85 14254 77 0 0
T90 623 39 0 0
T94 850 90 0 0
T95 907 94 0 0
T102 748 92 0 0
T103 951 99 0 0
T104 157503 38935 0 0
T112 624 41 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 661 0 0
T19 963 88 0 0
T20 3758 74 0 0
T85 14254 175 0 0
T90 623 15 0 0
T94 850 76 0 0
T95 907 125 0 0
T102 748 35 0 0
T103 951 37 0 0
T112 624 36 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T20 3758 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T102 748 1 0 0
T103 951 1 0 0
T112 624 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3315564 0 0
T6 64351 61634 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 3 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3316811 0 0
T6 64351 61639 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 3 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 11 0 0
T19 963 1 0 0
T20 3758 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T102 748 1 0 0
T103 951 1 0 0
T104 157503 1 0 0
T112 624 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T20 3758 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T102 748 1 0 0
T103 951 1 0 0
T112 624 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T20 3758 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T102 748 1 0 0
T103 951 1 0 0
T112 624 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 10 0 0
T19 963 1 0 0
T20 3758 1 0 0
T85 14254 2 0 0
T90 623 1 0 0
T94 850 1 0 0
T95 907 1 0 0
T102 748 1 0 0
T103 951 1 0 0
T112 624 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 645 0 0
T19 963 87 0 0
T20 3758 72 0 0
T85 14254 171 0 0
T90 623 14 0 0
T94 850 75 0 0
T95 907 123 0 0
T102 748 34 0 0
T103 951 35 0 0
T112 624 34 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3175 0 0
T6 64351 5 0 0
T19 963 1 0 0
T21 482 9 0 0
T30 1872 11 0 0
T34 524 6 0 0
T35 524 4 0 0
T36 502 4 0 0
T49 446 12 0 0
T75 422 4 0 0
T76 423 4 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4 0 0
T19 963 1 0 0
T90 623 1 0 0
T94 850 1 0 0
T102 748 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT20,T28,T98
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT20,T28,T98

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT20,T28,T98

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT20,T28,T98
10CoveredT6,T21,T34
11CoveredT20,T28,T98

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT20,T28,T98
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT20,T28,T98
01CoveredT20,T28,T98
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT20,T28,T98
1-CoveredT20,T28,T98

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T20,T28,T98
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T20,T28,T98
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T20,T28,T98
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T20,T28,T98
DebounceSt - 0 1 0 - - - Covered T85,T100,T102
DebounceSt - 0 0 - - - - Covered T20,T28,T98
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T20,T28,T98
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T20,T28,T98
StableSt - - - - - - 0 Covered T20,T28,T98
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3398974 0 0
CntIncr_A 3964510 78843 0 0
CntNoWrap_A 3964510 78843 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 13921 0 0
DetectedPulseOut_A 3964510 19 0 0
DisabledIdleSt_A 3964510 2995464 0 0
DisabledNoDetection_A 3964510 2996711 0 0
EnterDebounceSt_A 3964510 22 0 0
EnterDetectSt_A 3964510 19 0 0
EnterStableSt_A 3964510 19 0 0
PulseIsPulse_A 3964510 19 0 0
StayInStableSt 3964510 13894 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 11 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3398974 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78843 0 0
T20 3758 50 0 0
T28 299733 72 0 0
T43 6768 61 0 0
T85 14254 82 0 0
T88 5876 83 0 0
T89 6770 140 0 0
T92 566 22 0 0
T98 559 15 0 0
T105 592 52 0 0
T109 507 10 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 78843 0 0
T20 3758 50 0 0
T28 299733 72 0 0
T43 6768 61 0 0
T85 14254 82 0 0
T88 5876 83 0 0
T89 6770 140 0 0
T92 566 22 0 0
T98 559 15 0 0
T105 592 52 0 0
T109 507 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13921 0 0
T20 3758 35 0 0
T28 299733 65 0 0
T43 6768 9 0 0
T85 14254 35 0 0
T88 5876 189 0 0
T89 6770 68 0 0
T92 566 99 0 0
T98 559 35 0 0
T105 592 112 0 0
T109 507 38 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T89 6770 2 0 0
T92 566 1 0 0
T98 559 1 0 0
T105 592 2 0 0
T109 507 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2995464 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 2996711 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 22 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T85 14254 2 0 0
T88 5876 1 0 0
T89 6770 2 0 0
T92 566 1 0 0
T98 559 1 0 0
T105 592 2 0 0
T109 507 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T89 6770 2 0 0
T92 566 1 0 0
T98 559 1 0 0
T105 592 2 0 0
T109 507 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T89 6770 2 0 0
T92 566 1 0 0
T98 559 1 0 0
T105 592 2 0 0
T109 507 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T20 3758 1 0 0
T28 299733 2 0 0
T43 6768 1 0 0
T85 14254 1 0 0
T88 5876 1 0 0
T89 6770 2 0 0
T92 566 1 0 0
T98 559 1 0 0
T105 592 2 0 0
T109 507 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 13894 0 0
T20 3758 34 0 0
T28 299733 62 0 0
T43 6768 8 0 0
T85 14254 33 0 0
T88 5876 188 0 0
T89 6770 65 0 0
T92 566 97 0 0
T98 559 34 0 0
T105 592 109 0 0
T109 507 37 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 11 0 0
T20 3758 1 0 0
T28 299733 1 0 0
T43 6768 1 0 0
T88 5876 1 0 0
T89 6770 1 0 0
T98 559 1 0 0
T104 157503 1 0 0
T105 592 1 0 0
T108 762 1 0 0
T109 507 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL484491.67
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343088.24
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 0 1
189 0 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T19,T20
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT6,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT6,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T19,T20
10CoveredT6,T21,T34
11CoveredT6,T19,T20

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T19,T20
01Not Covered
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T19,T20
01CoveredT107,T94,T97
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T19,T20
1-CoveredT107,T94,T97

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Not Covered
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T6,T19,T20
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T19,T20
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T19,T20
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T6,T19,T20
DebounceSt - 0 1 0 - - - Covered T105,T89
DebounceSt - 0 0 - - - - Covered T6,T19,T20
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T19,T20
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T107,T94,T97
StableSt - - - - - - 0 Covered T6,T19,T20
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3476746 0 0
CntIncr_A 3964510 1071 0 0
CntNoWrap_A 3964510 1071 0 0
DetectStDropOut_A 3964510 0 0 0
DetectedOut_A 3964510 1375 0 0
DetectedPulseOut_A 3964510 16 0 0
DisabledIdleSt_A 3964510 3471226 0 0
DisabledNoDetection_A 3964510 3472469 0 0
EnterDebounceSt_A 3964510 18 0 0
EnterDetectSt_A 3964510 16 0 0
EnterStableSt_A 3964510 16 0 0
PulseIsPulse_A 3964510 16 0 0
StayInStableSt 3964510 1346 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 3964510 3818 0 0
gen_low_level_sva.LowLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 3 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3476746 0 0
T6 64351 61869 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 468 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1071 0 0
T6 64351 76 0 0
T19 963 94 0 0
T20 3758 50 0 0
T43 6768 61 0 0
T45 852 92 0 0
T88 5876 83 0 0
T101 231264 21 0 0
T105 592 26 0 0
T107 670 53 0 0
T109 507 10 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1071 0 0
T6 64351 76 0 0
T19 963 94 0 0
T20 3758 50 0 0
T43 6768 61 0 0
T45 852 92 0 0
T88 5876 83 0 0
T101 231264 21 0 0
T105 592 26 0 0
T107 670 53 0 0
T109 507 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1375 0 0
T6 64351 73 0 0
T19 963 36 0 0
T20 3758 74 0 0
T43 6768 237 0 0
T45 852 214 0 0
T88 5876 34 0 0
T90 623 94 0 0
T101 231264 43 0 0
T107 670 82 0 0
T109 507 35 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 16 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T101 231264 1 0 0
T107 670 1 0 0
T109 507 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3471226 0 0
T6 64351 61451 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 3 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3472469 0 0
T6 64351 61455 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 3 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 18 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T88 5876 1 0 0
T101 231264 1 0 0
T105 592 1 0 0
T107 670 1 0 0
T109 507 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 16 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T101 231264 1 0 0
T107 670 1 0 0
T109 507 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 16 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T101 231264 1 0 0
T107 670 1 0 0
T109 507 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 16 0 0
T6 64351 1 0 0
T19 963 1 0 0
T20 3758 1 0 0
T43 6768 1 0 0
T45 852 1 0 0
T88 5876 1 0 0
T90 623 1 0 0
T101 231264 1 0 0
T107 670 1 0 0
T109 507 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 1346 0 0
T6 64351 71 0 0
T19 963 34 0 0
T20 3758 72 0 0
T43 6768 235 0 0
T45 852 212 0 0
T88 5876 32 0 0
T90 623 92 0 0
T101 231264 41 0 0
T107 670 81 0 0
T109 507 33 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3818 0 0
T6 64351 12 0 0
T7 2247 12 0 0
T8 25853 1 0 0
T19 963 1 0 0
T21 482 10 0 0
T34 524 6 0 0
T35 524 6 0 0
T36 502 5 0 0
T49 446 11 0 0
T75 422 3 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3 0 0
T94 850 1 0 0
T97 2538 1 0 0
T107 670 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL484695.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT20,T24,T25
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT20,T24,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT16,T29,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT20,T24,T25
10CoveredT6,T21,T34
11CoveredT20,T24,T25

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T29,T12
01CoveredT41,T64,T65
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT16,T29,T12
01CoveredT16,T29,T12
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT16,T29,T12
1-CoveredT16,T29,T12

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Covered T10
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 10 90.91
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T20,T24,T25
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T29,T12
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T20,T24,T25
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T16,T29,T12
DebounceSt - 0 1 0 - - - Covered T20,T24,T25
DebounceSt - 0 0 - - - - Covered T20,T24,T25
DetectSt - - - - 1 - - Covered T41,T64,T65
DetectSt - - - - 0 1 - Covered T16,T29,T12
DetectSt - - - - 0 0 - Covered T16,T29,T12
StableSt - - - - - - 1 Covered T16,T29,T12
StableSt - - - - - - 0 Covered T16,T29,T12
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3470942 0 0
CntIncr_A 3964510 6875 0 0
CntNoWrap_A 3964510 6875 0 0
DetectStDropOut_A 3964510 4 0 0
DetectedOut_A 3964510 516 0 0
DetectedPulseOut_A 3964510 19 0 0
DisabledIdleSt_A 3964510 3429167 0 0
DisabledNoDetection_A 3964510 3430211 0 0
EnterDebounceSt_A 3964510 132 0 0
EnterDetectSt_A 3964510 23 0 0
EnterStableSt_A 3964510 19 0 0
PulseIsPulse_A 3964510 19 0 0
StayInStableSt 3964510 496 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 18 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3470942 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 6875 0 0
T16 821 133 0 0
T20 3758 64 0 0
T24 452 32 0 0
T25 459 32 0 0
T28 299733 96 0 0
T50 453 32 0 0
T51 456 32 0 0
T52 454 32 0 0
T53 460 32 0 0
T54 2751 32 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 6875 0 0
T16 821 133 0 0
T20 3758 64 0 0
T24 452 32 0 0
T25 459 32 0 0
T28 299733 96 0 0
T50 453 32 0 0
T51 456 32 0 0
T52 454 32 0 0
T53 460 32 0 0
T54 2751 32 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4 0 0
T41 9422 1 0 0
T64 999 1 0 0
T65 772 2 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 516 0 0
T12 873 52 0 0
T16 821 9 0 0
T29 1024 34 0 0
T39 3033 9 0 0
T43 6768 28 0 0
T70 886 8 0 0
T71 3353 63 0 0
T72 1000 19 0 0
T73 1033 5 0 0
T74 1085 73 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T12 873 1 0 0
T16 821 1 0 0
T29 1024 1 0 0
T39 3033 1 0 0
T43 6768 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T72 1000 1 0 0
T73 1033 1 0 0
T74 1085 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3429167 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3430211 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 132 0 0
T16 821 1 0 0
T20 3758 2 0 0
T24 452 1 0 0
T25 459 1 0 0
T28 299733 3 0 0
T50 453 1 0 0
T51 456 1 0 0
T52 454 1 0 0
T53 460 1 0 0
T54 2751 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 23 0 0
T12 873 1 0 0
T16 821 1 0 0
T29 1024 1 0 0
T39 3033 1 0 0
T41 9422 1 0 0
T43 6768 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T72 1000 1 0 0
T73 1033 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T12 873 1 0 0
T16 821 1 0 0
T29 1024 1 0 0
T39 3033 1 0 0
T43 6768 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T72 1000 1 0 0
T73 1033 1 0 0
T74 1085 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 19 0 0
T12 873 1 0 0
T16 821 1 0 0
T29 1024 1 0 0
T39 3033 1 0 0
T43 6768 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T72 1000 1 0 0
T73 1033 1 0 0
T74 1085 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 496 0 0
T12 873 51 0 0
T16 821 8 0 0
T29 1024 33 0 0
T39 3033 8 0 0
T43 6768 27 0 0
T70 886 7 0 0
T71 3353 62 0 0
T72 1000 18 0 0
T73 1033 4 0 0
T74 1085 72 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 18 0 0
T12 873 1 0 0
T16 821 1 0 0
T29 1024 1 0 0
T39 3033 1 0 0
T43 6768 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T72 1000 1 0 0
T73 1033 1 0 0
T74 1085 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL484695.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT15,T16,T17
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT15,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT15,T17,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT26,T15,T16
10CoveredT6,T21,T34
11CoveredT15,T16,T17

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT15,T17,T29
01CoveredT42,T43,T66
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT15,T17,T29
01CoveredT15,T17,T29
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT15,T17,T29
1-CoveredT15,T17,T29

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Covered T10
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 10 90.91
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T15,T16,T17
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T15,T17,T29
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T15,T16,T17
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T15,T17,T29
DebounceSt - 0 1 0 - - - Covered T16,T70,T115
DebounceSt - 0 0 - - - - Covered T15,T16,T17
DetectSt - - - - 1 - - Covered T42,T43,T66
DetectSt - - - - 0 1 - Covered T15,T17,T29
DetectSt - - - - 0 0 - Covered T15,T17,T29
StableSt - - - - - - 1 Covered T15,T17,T29
StableSt - - - - - - 0 Covered T15,T17,T29
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3473728 0 0
CntIncr_A 3964510 4089 0 0
CntNoWrap_A 3964510 4089 0 0
DetectStDropOut_A 3964510 3 0 0
DetectedOut_A 3964510 908 0 0
DetectedPulseOut_A 3964510 26 0 0
DisabledIdleSt_A 3964510 3433752 0 0
DisabledNoDetection_A 3964510 3434889 0 0
EnterDebounceSt_A 3964510 35 0 0
EnterDetectSt_A 3964510 29 0 0
EnterStableSt_A 3964510 26 0 0
PulseIsPulse_A 3964510 26 0 0
StayInStableSt 3964510 882 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 26 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3473728 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4089 0 0
T15 881 93 0 0
T16 821 83 0 0
T17 10031 91 0 0
T29 1024 97 0 0
T41 9422 133 0 0
T42 2902 161 0 0
T43 6768 135 0 0
T70 886 175 0 0
T71 3353 108 0 0
T116 998 88 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4089 0 0
T15 881 93 0 0
T16 821 83 0 0
T17 10031 91 0 0
T29 1024 97 0 0
T41 9422 133 0 0
T42 2902 161 0 0
T43 6768 135 0 0
T70 886 175 0 0
T71 3353 108 0 0
T116 998 88 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3 0 0
T42 2902 1 0 0
T43 6768 1 0 0
T66 1052 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 908 0 0
T15 881 51 0 0
T17 10031 47 0 0
T29 1024 46 0 0
T38 10871 32 0 0
T41 9422 31 0 0
T62 6115 27 0 0
T70 886 37 0 0
T71 3353 98 0 0
T116 998 87 0 0
T117 736 29 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 26 0 0
T15 881 1 0 0
T17 10031 1 0 0
T29 1024 1 0 0
T38 10871 1 0 0
T41 9422 1 0 0
T62 6115 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T117 736 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3433752 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3434889 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 35 0 0
T15 881 1 0 0
T16 821 1 0 0
T17 10031 1 0 0
T29 1024 1 0 0
T41 9422 1 0 0
T42 2902 1 0 0
T43 6768 1 0 0
T70 886 2 0 0
T71 3353 1 0 0
T116 998 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 29 0 0
T15 881 1 0 0
T17 10031 1 0 0
T29 1024 1 0 0
T38 10871 1 0 0
T41 9422 1 0 0
T42 2902 1 0 0
T43 6768 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T116 998 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 26 0 0
T15 881 1 0 0
T17 10031 1 0 0
T29 1024 1 0 0
T38 10871 1 0 0
T41 9422 1 0 0
T62 6115 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T117 736 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 26 0 0
T15 881 1 0 0
T17 10031 1 0 0
T29 1024 1 0 0
T38 10871 1 0 0
T41 9422 1 0 0
T62 6115 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T117 736 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 882 0 0
T15 881 50 0 0
T17 10031 46 0 0
T29 1024 45 0 0
T38 10871 31 0 0
T41 9422 30 0 0
T62 6115 26 0 0
T70 886 36 0 0
T71 3353 97 0 0
T116 998 86 0 0
T117 736 28 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 26 0 0
T15 881 1 0 0
T17 10031 1 0 0
T29 1024 1 0 0
T38 10871 1 0 0
T41 9422 1 0 0
T62 6115 1 0 0
T70 886 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T117 736 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL484695.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT17,T71,T88
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT17,T71,T88

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT17,T71,T118

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT26,T15,T16
10CoveredT6,T21,T34
11CoveredT17,T71,T88

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT17,T71,T118
01CoveredT41,T38,T61
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT17,T71,T118
01CoveredT17,T71,T118
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT17,T71,T118
1-CoveredT17,T71,T118

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Covered T10
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 10 90.91
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T17,T71,T88
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T17,T71,T118
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T17,T71,T88
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T17,T71,T118
DebounceSt - 0 1 0 - - - Covered T116,T117,T115
DebounceSt - 0 0 - - - - Covered T17,T71,T88
DetectSt - - - - 1 - - Covered T41,T38,T61
DetectSt - - - - 0 1 - Covered T17,T71,T118
DetectSt - - - - 0 0 - Covered T17,T71,T118
StableSt - - - - - - 1 Covered T17,T71,T118
StableSt - - - - - - 0 Covered T17,T71,T118
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3473195 0 0
CntIncr_A 3964510 4622 0 0
CntNoWrap_A 3964510 4622 0 0
DetectStDropOut_A 3964510 8 0 0
DetectedOut_A 3964510 717 0 0
DetectedPulseOut_A 3964510 24 0 0
DisabledIdleSt_A 3964510 3436749 0 0
DisabledNoDetection_A 3964510 3437893 0 0
EnterDebounceSt_A 3964510 40 0 0
EnterDetectSt_A 3964510 32 0 0
EnterStableSt_A 3964510 24 0 0
PulseIsPulse_A 3964510 24 0 0
StayInStableSt 3964510 693 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 24 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3473195 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4622 0 0
T17 10031 120 0 0
T38 10871 101 0 0
T41 9422 237 0 0
T43 6768 114 0 0
T71 3353 195 0 0
T88 5876 5 0 0
T116 998 167 0 0
T117 736 46 0 0
T118 899 126 0 0
T119 9954 273 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4622 0 0
T17 10031 120 0 0
T38 10871 101 0 0
T41 9422 237 0 0
T43 6768 114 0 0
T71 3353 195 0 0
T88 5876 5 0 0
T116 998 167 0 0
T117 736 46 0 0
T118 899 126 0 0
T119 9954 273 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 8 0 0
T38 10871 1 0 0
T41 9422 1 0 0
T61 12059 1 0 0
T62 6115 2 0 0
T67 2776 1 0 0
T68 178308 2 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 717 0 0
T17 10031 5 0 0
T41 9422 8 0 0
T43 6768 21 0 0
T71 3353 11 0 0
T116 998 86 0 0
T118 899 16 0 0
T119 9954 13 0 0
T120 1874 10 0 0
T121 1267 36 0 0
T122 1225 20 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T17 10031 1 0 0
T41 9422 1 0 0
T43 6768 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T118 899 1 0 0
T119 9954 1 0 0
T120 1874 1 0 0
T121 1267 1 0 0
T122 1225 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3436749 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3437893 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 40 0 0
T17 10031 1 0 0
T38 10871 1 0 0
T41 9422 2 0 0
T43 6768 1 0 0
T71 3353 1 0 0
T88 5876 1 0 0
T116 998 2 0 0
T117 736 2 0 0
T118 899 1 0 0
T119 9954 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 32 0 0
T17 10031 1 0 0
T38 10871 1 0 0
T41 9422 2 0 0
T43 6768 1 0 0
T61 12059 1 0 0
T62 6115 2 0 0
T71 3353 1 0 0
T116 998 1 0 0
T118 899 1 0 0
T119 9954 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T17 10031 1 0 0
T41 9422 1 0 0
T43 6768 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T118 899 1 0 0
T119 9954 1 0 0
T120 1874 1 0 0
T121 1267 1 0 0
T122 1225 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T17 10031 1 0 0
T41 9422 1 0 0
T43 6768 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T118 899 1 0 0
T119 9954 1 0 0
T120 1874 1 0 0
T121 1267 1 0 0
T122 1225 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 693 0 0
T17 10031 4 0 0
T41 9422 7 0 0
T43 6768 20 0 0
T71 3353 10 0 0
T116 998 85 0 0
T118 899 15 0 0
T119 9954 12 0 0
T120 1874 9 0 0
T121 1267 35 0 0
T122 1225 18 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 24 0 0
T17 10031 1 0 0
T41 9422 1 0 0
T43 6768 1 0 0
T71 3353 1 0 0
T116 998 1 0 0
T118 899 1 0 0
T119 9954 1 0 0
T120 1874 1 0 0
T121 1267 1 0 0
T122 1225 2 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL484695.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125343294.12
ALWAYS22233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
151 1 1
162 1 1
164 1 1
165 0 1
166 0 1
167 1 1
168 1 1
169 1 1
170 1 1
172 1 1
MISSING_ELSE
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
MISSING_ELSE
204 1 1
208 1 1
209 1 1
212 1 1
Exclude Annotation: VC_COV_UNR
222 1 1
223 1 1
225 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT12,T71,T119
1CoveredT6,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT12,T71,T119

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T21,T34
1CoveredT12,T71,T119

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT26,T15,T16
10CoveredT6,T21,T34
11CoveredT12,T71,T119

 LINE       187
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT12,T71,T119
01CoveredT41,T63,T64
10Not Covered

 LINE       208
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT12,T71,T119
01CoveredT12,T71,T119
10Not Covered

 LINE       208
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT12,T71,T119
1-CoveredT12,T71,T119

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10
DetectSt 170 Covered T10
IdleSt 223 Covered T10
StableSt 193 Covered T10


transitionsLine No.CoveredTests
DebounceSt->DetectSt 170 Covered T10
DebounceSt->IdleSt 223 Covered T10
DetectSt->IdleSt 223 Covered T10
DetectSt->StableSt 193 Covered T10
IdleSt->DebounceSt 148 Covered T10
StableSt->IdleSt 223 Covered T10



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 10 90.91
IF 222 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T21,T34
0 1 Covered T12,T71,T119
0 0 Excluded VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T12,T71,T119
0 Covered T6,T21,T34


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 164 if ((!cfg_enable_i)) -4-: 167 if (cnt_done) -5-: 169 if (trigger_active) -6-: 187 if (((!cfg_enable_i) || (!trigger_active))) -7-: 192 if (cnt_done) -8-: 208 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T12,T71,T119
IdleSt 0 - - - - - - Covered T6,T21,T34
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T12,T71,T119
DebounceSt - 0 1 0 - - - Covered T123,T116,T124
DebounceSt - 0 0 - - - - Covered T12,T71,T119
DetectSt - - - - 1 - - Covered T41,T63,T64
DetectSt - - - - 0 1 - Covered T12,T71,T119
DetectSt - - - - 0 0 - Covered T12,T71,T119
StableSt - - - - - - 1 Covered T12,T71,T119
StableSt - - - - - - 0 Covered T12,T71,T119
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 222 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T21,T34
0 Covered T6,T21,T34


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 3964510 3473281 0 0
CntIncr_A 3964510 4536 0 0
CntNoWrap_A 3964510 4536 0 0
DetectStDropOut_A 3964510 4 0 0
DetectedOut_A 3964510 728 0 0
DetectedPulseOut_A 3964510 23 0 0
DisabledIdleSt_A 3964510 3432439 0 0
DisabledNoDetection_A 3964510 3433573 0 0
EnterDebounceSt_A 3964510 38 0 0
EnterDetectSt_A 3964510 28 0 0
EnterStableSt_A 3964510 23 0 0
PulseIsPulse_A 3964510 23 0 0
StayInStableSt 3964510 705 0 0
gen_high_level_sva.HighLevelEvent_A 3964510 3479082 0 0
gen_not_sticky_sva.StableStDropOut_A 3964510 23 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3473281 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4536 0 0
T12 873 62 0 0
T41 9422 164 0 0
T43 6768 258 0 0
T61 12059 177 0 0
T71 3353 201 0 0
T74 1085 85 0 0
T116 998 78 0 0
T119 9954 268 0 0
T123 820 63 0 0
T124 946 91 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4536 0 0
T12 873 62 0 0
T41 9422 164 0 0
T43 6768 258 0 0
T61 12059 177 0 0
T71 3353 201 0 0
T74 1085 85 0 0
T116 998 78 0 0
T119 9954 268 0 0
T123 820 63 0 0
T124 946 91 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 4 0 0
T41 9422 1 0 0
T63 7241 2 0 0
T64 999 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 728 0 0
T12 873 53 0 0
T43 6768 12 0 0
T61 12059 10 0 0
T62 6115 38 0 0
T71 3353 5 0 0
T119 9954 18 0 0
T121 1267 152 0 0
T122 1225 136 0 0
T125 1172 6 0 0
T126 940 60 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 23 0 0
T12 873 1 0 0
T43 6768 2 0 0
T61 12059 1 0 0
T62 6115 2 0 0
T71 3353 1 0 0
T119 9954 1 0 0
T121 1267 2 0 0
T122 1225 2 0 0
T125 1172 1 0 0
T126 940 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3432439 0 0
T6 64351 61945 0 0
T7 2247 1846 0 0
T8 25853 25452 0 0
T19 963 562 0 0
T21 482 81 0 0
T22 717 316 0 0
T34 524 123 0 0
T35 524 123 0 0
T36 502 101 0 0
T49 446 45 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3433573 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 38 0 0
T12 873 1 0 0
T41 9422 1 0 0
T43 6768 2 0 0
T61 12059 1 0 0
T71 3353 1 0 0
T74 1085 1 0 0
T116 998 1 0 0
T119 9954 1 0 0
T123 820 1 0 0
T124 946 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 28 0 0
T12 873 1 0 0
T41 9422 1 0 0
T43 6768 2 0 0
T61 12059 1 0 0
T62 6115 2 0 0
T63 7241 2 0 0
T71 3353 1 0 0
T119 9954 1 0 0
T125 1172 1 0 0
T126 940 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 23 0 0
T12 873 1 0 0
T43 6768 2 0 0
T61 12059 1 0 0
T62 6115 2 0 0
T71 3353 1 0 0
T119 9954 1 0 0
T121 1267 2 0 0
T122 1225 2 0 0
T125 1172 1 0 0
T126 940 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 23 0 0
T12 873 1 0 0
T43 6768 2 0 0
T61 12059 1 0 0
T62 6115 2 0 0
T71 3353 1 0 0
T119 9954 1 0 0
T121 1267 2 0 0
T122 1225 2 0 0
T125 1172 1 0 0
T126 940 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 705 0 0
T12 873 52 0 0
T43 6768 10 0 0
T61 12059 9 0 0
T62 6115 36 0 0
T71 3353 4 0 0
T119 9954 17 0 0
T121 1267 150 0 0
T122 1225 134 0 0
T125 1172 5 0 0
T126 940 59 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 3479082 0 0
T6 64351 61951 0 0
T7 2247 1847 0 0
T8 25853 25453 0 0
T19 963 563 0 0
T21 482 82 0 0
T22 717 317 0 0
T34 524 124 0 0
T35 524 124 0 0
T36 502 102 0 0
T49 446 46 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3964510 23 0 0
T12 873 1 0 0
T43 6768 2 0 0
T61 12059 1 0 0
T62 6115 2 0 0
T71 3353 1 0 0
T119 9954 1 0 0
T121 1267 2 0 0
T122 1225 2 0 0
T125 1172 1 0 0
T126 940 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%