Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T2 T4 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T4 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T21 T53 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T4 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T4 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T4 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T4 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T4 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T4 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T4 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T4 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T21 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T21 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T21 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T21 T53 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T21 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T21 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T21 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T21 T56 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T53 T219 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T21 T56 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T21 T56 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T21 T56 
186        1/1                    state_d = IdleSt;
           Tests:       T56 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T56 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T21 T54 
191        1/1                      state_d = StableSt;
           Tests:       T8 T21 T54 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T21 T54 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T21 T54 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T21 T54 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T21 T54 
206        1/1                    state_d = IdleSt;
           Tests:       T21 T54 T125 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T21 T54 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T21,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T8,T21,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T21,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T45,T21
1	0	Covered	T1,T2,T4
1	1	Covered	T8,T21,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T54
0	1	Not Covered
1	0	Covered	T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T54
0	1	Covered	T54,T125,T189
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T21,T54
1	-	Covered	T54,T125,T189

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T21,T53
DetectSt	168	Covered	T8,T21,T56
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T8,T21,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T21,T56
DebounceSt->IdleSt	163	Covered	T53,T193,T219
DetectSt->IdleSt	186	Covered	T56
DetectSt->StableSt	191	Covered	T8,T21,T54
IdleSt->DebounceSt	148	Covered	T8,T21,T53
StableSt->IdleSt	206	Covered	T21,T54,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T21,T53
0	1	Covered	T8,T21,T53
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T21,T56
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T21,T53
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T21,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T21,T53
DetectSt	-	-	-	-	1	-	-	Covered	T56
DetectSt	-	-	-	-	0	1	-	Covered	T8,T21,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T54,T125
StableSt	-	-	-	-	-	-	0	Covered	T8,T21,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	72	0	0
CntIncr_A	7014086	50483	0	0
CntNoWrap_A	7014086	6364778	0	0
DetectStDropOut_A	7014086	0	0	0
DetectedOut_A	7014086	85779	0	0
DetectedPulseOut_A	7014086	34	0	0
DisabledIdleSt_A	7014086	6160709	0	0
DisabledNoDetection_A	7014086	6163056	0	0
EnterDebounceSt_A	7014086	38	0	0
EnterDetectSt_A	7014086	35	0	0
EnterStableSt_A	7014086	34	0	0
PulseIsPulse_A	7014086	34	0	0
StayInStableSt	7014086	85727	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	72	0	0
T8	627	2	0	0
T21	0	2	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T53	0	1	0	0
T54	0	4	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	2	0	0
T217	0	2	0	0
T220	411	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	50483	0	0
T8	627	12	0	0
T21	0	32	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	84	0	0
T47	0	39	0	0
T53	0	90	0	0
T54	0	134	0	0
T55	0	72	0	0
T56	0	39	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	18	0	0
T217	0	49	0	0
T220	411	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6364778	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	85779	0	0
T8	627	41	0	0
T21	0	6	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	173	0	0
T47	0	39	0	0
T54	0	52	0	0
T55	0	39	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	40	0	0
T215	0	41	0	0
T217	0	38	0	0
T220	411	0	0	0
T221	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	34	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	1	0	0
T215	0	1	0	0
T217	0	1	0	0
T220	411	0	0	0
T221	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6160709	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6163056	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	38	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	1	0	0
T217	0	1	0	0
T220	411	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	35	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	1	0	0
T217	0	1	0	0
T220	411	0	0	0
T221	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	34	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	1	0	0
T215	0	1	0	0
T217	0	1	0	0
T220	411	0	0	0
T221	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	34	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	1	0	0
T215	0	1	0	0
T217	0	1	0	0
T220	411	0	0	0
T221	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	85727	0	0
T8	627	39	0	0
T21	0	5	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	171	0	0
T47	0	37	0	0
T54	0	49	0	0
T55	0	37	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T125	0	39	0	0
T215	0	39	0	0
T217	0	36	0	0
T220	411	0	0	0
T221	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	15	0	0
T41	33129	0	0	0
T50	856	0	0	0
T54	8961	1	0	0
T88	19114	0	0	0
T96	974	0	0	0
T125	0	1	0	0
T131	3969	0	0	0
T133	656	0	0	0
T180	0	1	0	0
T189	0	2	0	0
T206	0	2	0	0
T209	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0
T224	0	2	0	0
T225	0	1	0	0
T226	445	0	0	0
T227	502	0	0	0
T228	554	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T2 T4 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T4 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T49 T21 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T4 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T4 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T4 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T4 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T4 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T4 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T4 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T4 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T49 T21 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T49 T21 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T49 T21 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T49 T21 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T49 T21 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T49 T21 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T49 T21 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T49 T21 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T100 T229 T230 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T49 T21 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T49 T21 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T49 T21 
186        1/1                    state_d = IdleSt;
           Tests:       T56 T231 T225 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T56 T231 T225 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T49 T21 
191        1/1                      state_d = StableSt;
           Tests:       T8 T49 T21 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T49 T21 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T49 T21 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T49 T21 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T49 T21 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T21 T53 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T49 T21 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T49,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T8,T49,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T49,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T51,T45
1	0	Covered	T13,T14,T15
1	1	Covered	T8,T49,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T49,T21
0	1	Covered	T231,T225
1	0	Covered	T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T49,T21
0	1	Covered	T8,T53,T48
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T49,T21
1	-	Covered	T8,T53,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T49,T21
DetectSt	168	Covered	T8,T49,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T8,T49,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T49,T21
DebounceSt->IdleSt	163	Covered	T100,T229,T230
DetectSt->IdleSt	186	Covered	T56,T231,T225
DetectSt->StableSt	191	Covered	T8,T49,T21
IdleSt->DebounceSt	148	Covered	T8,T49,T21
StableSt->IdleSt	206	Covered	T8,T21,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T49,T21
0	1	Covered	T8,T49,T21
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T49,T21
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T49,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T49,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T229,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T49,T21
DetectSt	-	-	-	-	1	-	-	Covered	T56,T231,T225
DetectSt	-	-	-	-	0	1	-	Covered	T8,T49,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T21,T53
StableSt	-	-	-	-	-	-	0	Covered	T8,T49,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	124	0	0
CntIncr_A	7014086	52103	0	0
CntNoWrap_A	7014086	6364726	0	0
DetectStDropOut_A	7014086	2	0	0
DetectedOut_A	7014086	36180	0	0
DetectedPulseOut_A	7014086	57	0	0
DisabledIdleSt_A	7014086	6165170	0	0
DisabledNoDetection_A	7014086	6167508	0	0
EnterDebounceSt_A	7014086	64	0	0
EnterDetectSt_A	7014086	60	0	0
EnterStableSt_A	7014086	57	0	0
PulseIsPulse_A	7014086	57	0	0
StayInStableSt	7014086	36096	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7014086	2956	0	0
gen_low_level_sva.LowLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	124	0	0
T8	627	2	0	0
T21	0	2	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T53	0	4	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	3	0	0
T129	0	4	0	0
T220	411	0	0	0
T232	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	52103	0	0
T8	627	12	0	0
T21	0	32	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	36	0	0
T49	0	39	0	0
T53	0	180	0	0
T55	0	72	0	0
T56	0	39	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	108	0	0
T129	0	120	0	0
T220	411	0	0	0
T232	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6364726	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	2	0	0
T225	0	1	0	0
T231	560	1	0	0
T233	523	0	0	0
T234	652	0	0	0
T235	2882	0	0	0
T236	1795	0	0	0
T237	502	0	0	0
T238	19199	0	0	0
T239	407	0	0	0
T240	740	0	0	0
T241	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	36180	0	0
T8	627	6	0	0
T21	0	5	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	24	0	0
T49	0	215	0	0
T53	0	85	0	0
T55	0	19	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	37	0	0
T129	0	30	0	0
T192	0	175	0	0
T220	411	0	0	0
T232	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	57	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	1	0	0
T129	0	2	0	0
T192	0	2	0	0
T220	411	0	0	0
T232	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6165170	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6167508	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	64	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	2	0	0
T129	0	2	0	0
T220	411	0	0	0
T232	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	60	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	1	0	0
T129	0	2	0	0
T220	411	0	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	57	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	1	0	0
T129	0	2	0	0
T192	0	2	0	0
T220	411	0	0	0
T232	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	57	0	0
T8	627	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	1	0	0
T129	0	2	0	0
T192	0	2	0	0
T220	411	0	0	0
T232	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	36096	0	0
T8	627	5	0	0
T21	0	4	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	23	0	0
T49	0	213	0	0
T53	0	82	0	0
T55	0	18	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T100	0	35	0	0
T129	0	28	0	0
T192	0	172	0	0
T220	411	0	0	0
T232	0	27	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	2956	0	0
T3	481	0	0	0
T8	0	1	0	0
T13	523	5	0	0
T14	412	2	0	0
T15	423	4	0	0
T16	1038	5	0	0
T17	426	0	0	0
T22	491	3	0	0
T23	497	3	0	0
T25	0	5	0	0
T26	0	4	0	0
T31	448	0	0	0
T65	0	5	0	0
T74	403	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	29	0	0
T8	627	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T129	0	2	0	0
T192	0	1	0	0
T193	0	1	0	0
T203	0	1	0	0
T215	0	1	0	0
T220	411	0	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T12 T13 T14 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T12 T13 T14 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T10 T21 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T12 T13 T14 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T12 T13 T14 
129        1/1              cnt_en = 1'b0;
           Tests:       T12 T13 T14 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T12 T13 T14 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T12 T13 T14 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T12 T13 T14 
139                     
140        1/1              unique case (state_q)
           Tests:       T12 T13 T14 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T12 T13 T14 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T10 T21 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T10 T21 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T10 T21 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T10 T21 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T10 T21 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T10 T21 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T10 T21 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T10 T21 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T221 T230 T140 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T10 T21 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T10 T21 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T10 T21 
186        1/1                    state_d = IdleSt;
           Tests:       T125 T189 T242 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T125 T189 T242 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T10 T21 
191        1/1                      state_d = StableSt;
           Tests:       T8 T10 T21 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T10 T21 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T10 T21 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T10 T21 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T10 T21 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T10 T21 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T10 T21 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T12,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T10,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T8,T10,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T10,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T21
1	0	Covered	T12,T13,T14
1	1	Covered	T8,T10,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T21
0	1	Covered	T125,T189,T242
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T21
0	1	Covered	T8,T10,T52
1	0	Covered	T21,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T21
1	-	Covered	T8,T10,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T21
DetectSt	168	Covered	T8,T10,T21
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T8,T10,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T21
DebounceSt->IdleSt	163	Covered	T221,T230,T140
DetectSt->IdleSt	186	Covered	T125,T189,T242
DetectSt->StableSt	191	Covered	T8,T10,T21
IdleSt->DebounceSt	148	Covered	T8,T10,T21
StableSt->IdleSt	206	Covered	T8,T10,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T21
0	1	Covered	T8,T10,T21
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T21
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T21
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T221,T230,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T21
DetectSt	-	-	-	-	1	-	-	Covered	T125,T189,T242
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T21
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	164	0	0
CntIncr_A	7014086	88534	0	0
CntNoWrap_A	7014086	6364686	0	0
DetectStDropOut_A	7014086	3	0	0
DetectedOut_A	7014086	70893	0	0
DetectedPulseOut_A	7014086	76	0	0
DisabledIdleSt_A	7014086	6043444	0	0
DisabledNoDetection_A	7014086	6045778	0	0
EnterDebounceSt_A	7014086	85	0	0
EnterDetectSt_A	7014086	79	0	0
EnterStableSt_A	7014086	76	0	0
PulseIsPulse_A	7014086	76	0	0
StayInStableSt	7014086	70784	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	164	0	0
T8	627	4	0	0
T10	0	4	0	0
T21	0	2	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	2	0	0
T52	0	2	0	0
T54	0	4	0	0
T56	0	2	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	4	0	0
T125	0	4	0	0
T129	0	2	0	0
T220	411	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	88534	0	0
T8	627	24	0	0
T10	0	42	0	0
T21	0	32	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	36	0	0
T52	0	22	0	0
T54	0	134	0	0
T56	0	39	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	138	0	0
T125	0	36	0	0
T129	0	57	0	0
T220	411	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6364686	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	3	0	0
T125	648	1	0	0
T174	45552	0	0	0
T175	3027	0	0	0
T176	450	0	0	0
T177	427	0	0	0
T178	38567	0	0	0
T179	497	0	0	0
T189	0	1	0	0
T242	0	1	0	0
T243	689	0	0	0
T244	830	0	0	0
T245	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	70893	0	0
T8	627	43	0	0
T10	0	85	0	0
T21	0	7	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	44	0	0
T52	0	1	0	0
T54	0	47	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	224	0	0
T125	0	40	0	0
T129	0	21	0	0
T220	411	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	76	0	0
T8	627	2	0	0
T10	0	2	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	2	0	0
T125	0	1	0	0
T129	0	1	0	0
T220	411	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6043444	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6045778	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	85	0	0
T8	627	2	0	0
T10	0	2	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	2	0	0
T125	0	2	0	0
T129	0	1	0	0
T220	411	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	79	0	0
T8	627	2	0	0
T10	0	2	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	2	0	0
T125	0	2	0	0
T129	0	1	0	0
T220	411	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	76	0	0
T8	627	2	0	0
T10	0	2	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	2	0	0
T125	0	1	0	0
T129	0	1	0	0
T220	411	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	76	0	0
T8	627	2	0	0
T10	0	2	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	2	0	0
T125	0	1	0	0
T129	0	1	0	0
T220	411	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	70784	0	0
T8	627	40	0	0
T10	0	82	0	0
T21	0	6	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	42	0	0
T54	0	45	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	221	0	0
T125	0	39	0	0
T129	0	20	0	0
T194	0	36	0	0
T220	411	0	0	0
T246	0	191	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	41	0	0
T8	627	1	0	0
T10	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T52	0	1	0	0
T54	0	2	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T121	0	1	0	0
T125	0	1	0	0
T129	0	1	0	0
T192	0	2	0	0
T215	0	1	0	0
T220	411	0	0	0
T246	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T12 T13 T14 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T4 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T21 T52 T56 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T4 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T4 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T4 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T4 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T4 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T4 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T4 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T4 
148        1/1                    state_d = DebounceSt;
           Tests:       T21 T52 T56 
149        1/1                    cnt_en = 1'b1;
           Tests:       T21 T52 T56 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T21 T52 T56 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T21 T52 T56 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T21 T52 T56 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T52 T56 
167        1/1                    if (trigger_active) begin
           Tests:       T21 T52 T56 
168        1/1                      state_d = DetectSt;
           Tests:       T21 T52 T56 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T192 T247 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T21 T52 T56 
182        1/1                  cnt_en = 1'b1;
           Tests:       T21 T52 T56 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T21 T52 T56 
186        1/1                    state_d = IdleSt;
           Tests:       T56 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T56 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T21 T52 T50 
191        1/1                      state_d = StableSt;
           Tests:       T21 T52 T50 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T21 T52 T50 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T21 T52 T50 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T21 T52 T50 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T21 T52 T50 
206        1/1                    state_d = IdleSt;
           Tests:       T21 T121 T246 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T21 T52 T50 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T21,T52,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T21,T52,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T21,T52,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T51,T49,T21
1	0	Covered	T12,T13,T14
1	1	Covered	T21,T52,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T52,T50
0	1	Not Covered
1	0	Covered	T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T52,T50
0	1	Covered	T121,T246,T192
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T52,T50
1	-	Covered	T121,T246,T192

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T52,T56
DetectSt	168	Covered	T21,T52,T56
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T21,T52,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T52,T56
DebounceSt->IdleSt	163	Covered	T192,T247
DetectSt->IdleSt	186	Covered	T56
DetectSt->StableSt	191	Covered	T21,T52,T50
IdleSt->DebounceSt	148	Covered	T21,T52,T56
StableSt->IdleSt	206	Covered	T21,T121,T129

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T52,T56
0	1	Covered	T21,T52,T56
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T52,T56
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T52,T56
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T52,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T192,T247
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T52,T56
DetectSt	-	-	-	-	1	-	-	Covered	T56
DetectSt	-	-	-	-	0	1	-	Covered	T21,T52,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T121,T246
StableSt	-	-	-	-	-	-	0	Covered	T21,T52,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	80	0	0
CntIncr_A	7014086	12002	0	0
CntNoWrap_A	7014086	6364770	0	0
DetectStDropOut_A	7014086	0	0	0
DetectedOut_A	7014086	24828	0	0
DetectedPulseOut_A	7014086	38	0	0
DisabledIdleSt_A	7014086	6268286	0	0
DisabledNoDetection_A	7014086	6270625	0	0
EnterDebounceSt_A	7014086	41	0	0
EnterDetectSt_A	7014086	39	0	0
EnterStableSt_A	7014086	38	0	0
PulseIsPulse_A	7014086	38	0	0
StayInStableSt	7014086	24769	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7014086	6619	0	0
gen_low_level_sva.LowLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	80	0	0
T21	7856	2	0	0
T32	20109	0	0	0
T46	0	2	0	0
T50	0	2	0	0
T52	0	2	0	0
T56	0	2	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	2	0	0
T129	0	2	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	3	0	0
T221	0	2	0	0
T246	0	4	0	0
T248	834	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	12002	0	0
T21	7856	32	0	0
T32	20109	0	0	0
T46	0	84	0	0
T50	0	75	0	0
T52	0	22	0	0
T56	0	39	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	69	0	0
T129	0	57	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	178	0	0
T221	0	62	0	0
T246	0	140	0	0
T248	834	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6364770	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	24828	0	0
T21	7856	5	0	0
T32	20109	0	0	0
T46	0	174	0	0
T50	0	148	0	0
T52	0	38	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	43	0	0
T129	0	41	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	40	0	0
T193	0	67	0	0
T221	0	37	0	0
T246	0	165	0	0
T248	834	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	38	0	0
T21	7856	1	0	0
T32	20109	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	1	0	0
T129	0	1	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	1	0	0
T193	0	1	0	0
T221	0	1	0	0
T246	0	2	0	0
T248	834	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6268286	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6270625	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	41	0	0
T21	7856	1	0	0
T32	20109	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	1	0	0
T129	0	1	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	2	0	0
T221	0	1	0	0
T246	0	2	0	0
T248	834	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	39	0	0
T21	7856	1	0	0
T32	20109	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	1	0	0
T129	0	1	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	1	0	0
T221	0	1	0	0
T246	0	2	0	0
T248	834	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	38	0	0
T21	7856	1	0	0
T32	20109	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	1	0	0
T129	0	1	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	1	0	0
T193	0	1	0	0
T221	0	1	0	0
T246	0	2	0	0
T248	834	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	38	0	0
T21	7856	1	0	0
T32	20109	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	1	0	0
T129	0	1	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	1	0	0
T193	0	1	0	0
T221	0	1	0	0
T246	0	2	0	0
T248	834	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	24769	0	0
T21	7856	4	0	0
T32	20109	0	0	0
T46	0	172	0	0
T50	0	146	0	0
T52	0	36	0	0
T72	1746	0	0	0
T77	524	0	0	0
T121	0	42	0	0
T129	0	39	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T192	0	39	0	0
T193	0	65	0	0
T221	0	35	0	0
T246	0	162	0	0
T248	834	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6619	0	0
T3	481	0	0	0
T5	0	2	0	0
T12	747	5	0	0
T13	523	7	0	0
T14	412	1	0	0
T15	423	1	0	0
T16	1038	0	0	0
T17	426	4	0	0
T22	491	5	0	0
T23	0	9	0	0
T25	0	6	0	0
T26	0	3	0	0
T31	448	0	0	0
T74	403	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	16	0	0
T100	7630	0	0	0
T117	0	1	0	0
T121	23409	1	0	0
T192	0	1	0	0
T206	0	2	0	0
T219	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0
T246	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0
T251	12908	0	0	0
T252	503	0	0	0
T253	637	0	0	0
T254	591	0	0	0
T255	514	0	0	0
T256	496	0	0	0
T257	404	0	0	0
T258	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T2 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T10 T51 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T10 T51 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T10 T51 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T10 T51 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T10 T51 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T10 T51 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T10 T51 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T10 T51 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T10 T51 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T115 T117 T259 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T10 T51 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T10 T51 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T10 T51 
186        1/1                    state_d = IdleSt;
           Tests:       T56 T115 T260 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T56 T115 T260 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T10 T51 
191        1/1                      state_d = StableSt;
           Tests:       T8 T10 T51 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T10 T51 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T10 T51 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T10 T51 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T10 T51 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T10 T51 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T10 T51 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T10,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T8,T10,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T10,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T51
1	0	Covered	T1,T2,T13
1	1	Covered	T8,T10,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T51
0	1	Covered	T115,T260,T207
1	0	Covered	T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T51
0	1	Covered	T8,T10,T51
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T51
1	-	Covered	T8,T10,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T51
DetectSt	168	Covered	T8,T10,T51
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T8,T10,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T51
DebounceSt->IdleSt	163	Covered	T115,T117,T259
DetectSt->IdleSt	186	Covered	T56,T115,T260
DetectSt->StableSt	191	Covered	T8,T10,T51
IdleSt->DebounceSt	148	Covered	T8,T10,T51
StableSt->IdleSt	206	Covered	T8,T10,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T51
0	1	Covered	T8,T10,T51
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T51
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T51
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T115,T117,T259
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T51
DetectSt	-	-	-	-	1	-	-	Covered	T56,T115,T260
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T51
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	189	0	0
CntIncr_A	7014086	44359	0	0
CntNoWrap_A	7014086	6364661	0	0
DetectStDropOut_A	7014086	3	0	0
DetectedOut_A	7014086	10119	0	0
DetectedPulseOut_A	7014086	87	0	0
DisabledIdleSt_A	7014086	6226768	0	0
DisabledNoDetection_A	7014086	6229092	0	0
EnterDebounceSt_A	7014086	99	0	0
EnterDetectSt_A	7014086	91	0	0
EnterStableSt_A	7014086	87	0	0
PulseIsPulse_A	7014086	87	0	0
StayInStableSt	7014086	9992	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	46	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	189	0	0
T8	627	2	0	0
T10	0	2	0	0
T21	0	2	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T56	0	2	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	2	0	0
T220	411	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	44359	0	0
T8	627	12	0	0
T10	0	21	0	0
T21	0	32	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	36	0	0
T49	0	39	0	0
T50	0	75	0	0
T51	0	88	0	0
T52	0	22	0	0
T56	0	39	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	44	0	0
T220	411	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6364661	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	3	0	0
T97	735	0	0	0
T115	5277	1	0	0
T125	648	0	0	0
T162	1182	0	0	0
T173	502	0	0	0
T174	45552	0	0	0
T175	3027	0	0	0
T176	450	0	0	0
T177	427	0	0	0
T178	38567	0	0	0
T207	0	1	0	0
T260	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	10119	0	0
T8	627	151	0	0
T10	0	55	0	0
T21	0	6	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	24	0	0
T49	0	133	0	0
T50	0	40	0	0
T51	0	37	0	0
T52	0	38	0	0
T55	0	39	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	9	0	0
T220	411	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	87	0	0
T8	627	1	0	0
T10	0	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	1	0	0
T220	411	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6226768	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6229092	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	99	0	0
T8	627	1	0	0
T10	0	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	1	0	0
T220	411	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	91	0	0
T8	627	1	0	0
T10	0	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	1	0	0
T220	411	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	87	0	0
T8	627	1	0	0
T10	0	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	1	0	0
T220	411	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	87	0	0
T8	627	1	0	0
T10	0	1	0	0
T21	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	1	0	0
T220	411	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	9992	0	0
T8	627	150	0	0
T10	0	54	0	0
T21	0	5	0	0
T24	490	0	0	0
T29	456	0	0	0
T48	0	23	0	0
T49	0	132	0	0
T50	0	39	0	0
T51	0	36	0	0
T52	0	36	0	0
T55	0	37	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	8	0	0
T220	411	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	46	0	0
T8	627	1	0	0
T10	0	1	0	0
T24	490	0	0	0
T29	456	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T57	443	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T131	0	1	0	0
T220	411	0	0	0
T254	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T2 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T4 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T8 T51 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T4 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T4 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T4 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T4 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T4 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T4 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T4 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T4 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T8 T51 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T8 T51 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T51 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T8 T51 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T8 T51 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T8 T51 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T8 T51 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T8 T51 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T191 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T8 T51 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T51 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T8 T51 
186        1/1                    state_d = IdleSt;
           Tests:       T56 T261 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T56 T261 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T8 T51 
191        1/1                      state_d = StableSt;
           Tests:       T3 T8 T51 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T8 T51 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T8 T51 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T8 T51 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T8 T51 
206        1/1                    state_d = IdleSt;
           Tests:       T21 T125 T126 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T8 T51 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T8,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T8,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T8,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T51
1	0	Covered	T1,T2,T13
1	1	Covered	T3,T8,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T51
0	1	Covered	T261
1	0	Covered	T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T51
0	1	Covered	T125,T126,T192
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T51
1	-	Covered	T125,T126,T192

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T51
DetectSt	168	Covered	T3,T8,T51
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T8,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T51
DebounceSt->IdleSt	163	Covered	T131,T191
DetectSt->IdleSt	186	Covered	T56,T261
DetectSt->StableSt	191	Covered	T3,T8,T51
IdleSt->DebounceSt	148	Covered	T3,T8,T51
StableSt->IdleSt	206	Covered	T21,T125,T100

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T51
0	1	Covered	T3,T8,T51
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T51
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T51
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T191
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T51
DetectSt	-	-	-	-	1	-	-	Covered	T56,T261
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T125,T126
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	105	0	0
CntIncr_A	7014086	100575	0	0
CntNoWrap_A	7014086	6364745	0	0
DetectStDropOut_A	7014086	1	0	0
DetectedOut_A	7014086	47965	0	0
DetectedPulseOut_A	7014086	50	0	0
DisabledIdleSt_A	7014086	5974060	0	0
DisabledNoDetection_A	7014086	5976394	0	0
EnterDebounceSt_A	7014086	54	0	0
EnterDetectSt_A	7014086	52	0	0
EnterStableSt_A	7014086	50	0	0
PulseIsPulse_A	7014086	50	0	0
StayInStableSt	7014086	47886	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7014086	6427	0	0
gen_low_level_sva.LowLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	105	0	0
T3	481	2	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	2	0	0
T21	0	2	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T56	0	2	0	0
T74	403	0	0	0
T81	405	0	0	0
T100	0	2	0	0
T125	0	4	0	0
T254	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	100575	0	0
T3	481	13	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	12	0	0
T21	0	32	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	39	0	0
T50	0	75	0	0
T51	0	88	0	0
T56	0	39	0	0
T74	403	0	0	0
T81	405	0	0	0
T125	0	36	0	0
T131	0	36	0	0
T254	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6364745	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	78	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	1	0	0
T261	2326	1	0	0
T262	225948	0	0	0
T263	494	0	0	0
T264	912	0	0	0
T265	9375	0	0	0
T266	417	0	0	0
T267	502	0	0	0
T268	425	0	0	0
T269	630	0	0	0
T270	2525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	47965	0	0
T3	481	41	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	42	0	0
T21	0	7	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	43	0	0
T50	0	148	0	0
T51	0	60	0	0
T74	403	0	0	0
T81	405	0	0	0
T100	0	92	0	0
T125	0	165	0	0
T126	0	261	0	0
T254	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	50	0	0
T3	481	1	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	1	0	0
T21	0	1	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T74	403	0	0	0
T81	405	0	0	0
T100	0	1	0	0
T125	0	2	0	0
T126	0	1	0	0
T254	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5974060	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	4	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5976394	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	4	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	54	0	0
T3	481	1	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	1	0	0
T21	0	1	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T56	0	1	0	0
T74	403	0	0	0
T81	405	0	0	0
T125	0	2	0	0
T131	0	1	0	0
T254	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	52	0	0
T3	481	1	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	1	0	0
T21	0	1	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T56	0	1	0	0
T74	403	0	0	0
T81	405	0	0	0
T100	0	1	0	0
T125	0	2	0	0
T254	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	50	0	0
T3	481	1	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	1	0	0
T21	0	1	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T74	403	0	0	0
T81	405	0	0	0
T100	0	1	0	0
T125	0	2	0	0
T126	0	1	0	0
T254	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	50	0	0
T3	481	1	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	1	0	0
T21	0	1	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T74	403	0	0	0
T81	405	0	0	0
T100	0	1	0	0
T125	0	2	0	0
T126	0	1	0	0
T254	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	47886	0	0
T3	481	39	0	0
T5	689	0	0	0
T7	506	0	0	0
T8	0	40	0	0
T21	0	6	0	0
T22	491	0	0	0
T23	497	0	0	0
T25	502	0	0	0
T26	501	0	0	0
T31	448	0	0	0
T49	0	41	0	0
T50	0	146	0	0
T51	0	58	0	0
T74	403	0	0	0
T81	405	0	0	0
T100	0	90	0	0
T125	0	162	0	0
T126	0	260	0	0
T254	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6427	0	0
T1	509	1	0	0
T2	486	1	0	0
T3	481	1	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	6	0	0
T14	412	0	0	0
T15	423	1	0	0
T16	1038	0	0	0
T17	426	3	0	0
T22	0	9	0	0
T23	0	6	0	0
T31	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	20	0	0
T125	648	1	0	0
T126	0	1	0	0
T174	45552	0	0	0
T175	3027	0	0	0
T176	450	0	0	0
T177	427	0	0	0
T178	38567	0	0	0
T179	497	0	0	0
T189	0	2	0	0
T192	0	1	0	0
T205	0	1	0	0
T207	0	2	0	0
T209	0	1	0	0
T215	0	1	0	0
T219	0	1	0	0
T243	689	0	0	0
T244	830	0	0	0
T245	402	0	0	0
T271	0	1	0	0