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Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.56 95.65 90.48 83.33 95.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.56 95.65 90.48 83.33 95.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT10,T11,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT10,T11,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT10,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T9,T10
10CoveredT1,T2,T4
11CoveredT10,T11,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT10,T35,T36
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT10,T35,T36
01CoveredT36,T33,T149
10CoveredT50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT10,T35,T36
1-CoveredT36,T33,T149

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10,T11,T35
DetectSt 168 Covered T10,T35,T36
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T10,T35,T36


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T10,T35,T36
DebounceSt->IdleSt 163 Covered T11,T100,T77
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T10,T35,T36
IdleSt->DebounceSt 148 Covered T10,T11,T35
StableSt->IdleSt 206 Covered T36,T33,T149



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T10,T11,T35
0 1 Covered T10,T11,T35
0 0 Excluded T1,T2,T4 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T10,T35,T36
0 Covered T1,T2,T4


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T10,T11,T35
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T77
DebounceSt - 0 1 1 - - - Covered T10,T35,T36
DebounceSt - 0 1 0 - - - Covered T11,T100,T181
DebounceSt - 0 0 - - - - Covered T10,T11,T35
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T10,T35,T36
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T36,T33,T149
StableSt - - - - - - 0 Covered T10,T35,T36
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6431240 100 0 0
CntIncr_A 6431240 17445 0 0
CntNoWrap_A 6431240 5736372 0 0
DetectStDropOut_A 6431240 0 0 0
DetectedOut_A 6431240 3689 0 0
DetectedPulseOut_A 6431240 47 0 0
DisabledIdleSt_A 6431240 5486064 0 0
DisabledNoDetection_A 6431240 5488474 0 0
EnterDebounceSt_A 6431240 53 0 0
EnterDetectSt_A 6431240 47 0 0
EnterStableSt_A 6431240 47 0 0
PulseIsPulse_A 6431240 47 0 0
StayInStableSt 6431240 3615 0 0
gen_high_level_sva.HighLevelEvent_A 6431240 5738952 0 0
gen_not_sticky_sva.StableStDropOut_A 6431240 19 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 100 0 0
T10 665 2 0 0
T11 646 1 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 4 0 0
T35 897 2 0 0
T36 0 4 0 0
T52 803 0 0 0
T58 491 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 2 0 0
T149 0 2 0 0
T150 0 2 0 0
T163 429 0 0 0
T182 0 2 0 0
T183 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 17445 0 0
T10 665 35 0 0
T11 646 41 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 123 0 0
T35 897 100 0 0
T36 0 108 0 0
T52 803 0 0 0
T58 491 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 88 0 0
T149 0 37 0 0
T150 0 45 0 0
T163 429 0 0 0
T182 0 37 0 0
T183 0 79 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5736372 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 3689 0 0
T10 665 45 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 213 0 0
T35 897 42 0 0
T36 0 94 0 0
T52 803 0 0 0
T58 491 0 0 0
T86 0 117 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 245 0 0
T149 0 88 0 0
T150 0 41 0 0
T163 429 0 0 0
T182 0 48 0 0
T183 0 244 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 47 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 2 0 0
T35 897 1 0 0
T36 0 2 0 0
T52 803 0 0 0
T58 491 0 0 0
T86 0 2 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 1 0 0
T149 0 1 0 0
T150 0 1 0 0
T163 429 0 0 0
T182 0 1 0 0
T183 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5486064 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5488474 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 53 0 0
T10 665 1 0 0
T11 646 1 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 2 0 0
T35 897 1 0 0
T36 0 2 0 0
T52 803 0 0 0
T58 491 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 1 0 0
T149 0 1 0 0
T150 0 1 0 0
T163 429 0 0 0
T182 0 1 0 0
T183 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 47 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 2 0 0
T35 897 1 0 0
T36 0 2 0 0
T52 803 0 0 0
T58 491 0 0 0
T86 0 2 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 1 0 0
T149 0 1 0 0
T150 0 1 0 0
T163 429 0 0 0
T182 0 1 0 0
T183 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 47 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 2 0 0
T35 897 1 0 0
T36 0 2 0 0
T52 803 0 0 0
T58 491 0 0 0
T86 0 2 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 1 0 0
T149 0 1 0 0
T150 0 1 0 0
T163 429 0 0 0
T182 0 1 0 0
T183 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 47 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 2 0 0
T35 897 1 0 0
T36 0 2 0 0
T52 803 0 0 0
T58 491 0 0 0
T86 0 2 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 1 0 0
T149 0 1 0 0
T150 0 1 0 0
T163 429 0 0 0
T182 0 1 0 0
T183 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 3615 0 0
T10 665 43 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 210 0 0
T35 897 40 0 0
T36 0 91 0 0
T52 803 0 0 0
T58 491 0 0 0
T86 0 114 0 0
T91 424 0 0 0
T108 425 0 0 0
T136 0 243 0 0
T149 0 87 0 0
T150 0 39 0 0
T163 429 0 0 0
T182 0 46 0 0
T183 0 242 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5738952 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 19 0 0
T20 547 0 0 0
T27 16458 0 0 0
T30 16056 0 0 0
T33 0 1 0 0
T36 722 1 0 0
T41 2522 0 0 0
T42 4517 0 0 0
T43 39452 0 0 0
T51 831 0 0 0
T66 503 0 0 0
T82 0 1 0 0
T86 0 1 0 0
T126 0 1 0 0
T149 0 1 0 0
T151 0 1 0 0
T164 0 1 0 0
T177 0 1 0 0
T179 0 1 0 0
T184 450 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT32,T35,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT32,T35,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT32,T35,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT31,T32,T35
10CoveredT1,T4,T12
11CoveredT32,T35,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT32,T35,T33
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT32,T35,T33
01CoveredT32,T35,T182
10CoveredT50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT32,T35,T33
1-CoveredT32,T35,T182

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T32,T35,T33
DetectSt 168 Covered T32,T35,T33
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T32,T35,T33


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T32,T35,T33
DebounceSt->IdleSt 163 Covered T33,T151,T167
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T32,T35,T33
IdleSt->DebounceSt 148 Covered T32,T35,T33
StableSt->IdleSt 206 Covered T32,T35,T33



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T32,T35,T33
0 1 Covered T32,T35,T33
0 0 Excluded T1,T2,T4 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T32,T35,T33
0 Covered T1,T2,T4


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T32,T35,T33
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T77
DebounceSt - 0 1 1 - - - Covered T32,T35,T33
DebounceSt - 0 1 0 - - - Covered T33,T151,T167
DebounceSt - 0 0 - - - - Covered T32,T35,T33
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T32,T35,T33
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T32,T35,T182
StableSt - - - - - - 0 Covered T32,T35,T33
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6431240 112 0 0
CntIncr_A 6431240 3661 0 0
CntNoWrap_A 6431240 5736360 0 0
DetectStDropOut_A 6431240 0 0 0
DetectedOut_A 6431240 4399 0 0
DetectedPulseOut_A 6431240 53 0 0
DisabledIdleSt_A 6431240 5624849 0 0
DisabledNoDetection_A 6431240 5627283 0 0
EnterDebounceSt_A 6431240 59 0 0
EnterDetectSt_A 6431240 53 0 0
EnterStableSt_A 6431240 53 0 0
PulseIsPulse_A 6431240 53 0 0
StayInStableSt 6431240 4326 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 6431240 3070 0 0
gen_low_level_sva.LowLevelEvent_A 6431240 5738952 0 0
gen_not_sticky_sva.StableStDropOut_A 6431240 32 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 112 0 0
T32 2567 8 0 0
T33 0 5 0 0
T35 897 2 0 0
T37 17506 0 0 0
T50 0 2 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 4 0 0
T151 0 3 0 0
T166 0 2 0 0
T167 0 3 0 0
T182 0 2 0 0
T185 0 2 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 3661 0 0
T32 2567 166 0 0
T33 0 100 0 0
T35 897 100 0 0
T37 17506 0 0 0
T50 0 18 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 200 0 0
T151 0 66 0 0
T166 0 86 0 0
T167 0 73 0 0
T182 0 37 0 0
T185 0 78 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5736360 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 4399 0 0
T32 2567 144 0 0
T33 0 263 0 0
T35 897 143 0 0
T37 17506 0 0 0
T50 0 8 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 362 0 0
T151 0 99 0 0
T166 0 62 0 0
T167 0 45 0 0
T182 0 6 0 0
T185 0 56 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 53 0 0
T32 2567 4 0 0
T33 0 2 0 0
T35 897 1 0 0
T37 17506 0 0 0
T50 0 1 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 2 0 0
T151 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T182 0 1 0 0
T185 0 1 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5624849 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5627283 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 59 0 0
T32 2567 4 0 0
T33 0 3 0 0
T35 897 1 0 0
T37 17506 0 0 0
T50 0 1 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 2 0 0
T151 0 2 0 0
T166 0 1 0 0
T167 0 2 0 0
T182 0 1 0 0
T185 0 1 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 53 0 0
T32 2567 4 0 0
T33 0 2 0 0
T35 897 1 0 0
T37 17506 0 0 0
T50 0 1 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 2 0 0
T151 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T182 0 1 0 0
T185 0 1 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 53 0 0
T32 2567 4 0 0
T33 0 2 0 0
T35 897 1 0 0
T37 17506 0 0 0
T50 0 1 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 2 0 0
T151 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T182 0 1 0 0
T185 0 1 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 53 0 0
T32 2567 4 0 0
T33 0 2 0 0
T35 897 1 0 0
T37 17506 0 0 0
T50 0 1 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 2 0 0
T151 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T182 0 1 0 0
T185 0 1 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 4326 0 0
T32 2567 140 0 0
T33 0 259 0 0
T35 897 142 0 0
T37 17506 0 0 0
T50 0 7 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 360 0 0
T151 0 97 0 0
T166 0 60 0 0
T167 0 43 0 0
T182 0 5 0 0
T185 0 54 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 3070 0 0
T1 353536 30 0 0
T2 599 0 0 0
T3 3608 5 0 0
T4 522 6 0 0
T5 18447 0 0 0
T6 0 1 0 0
T12 15235 0 0 0
T13 421 2 0 0
T14 403 0 0 0
T15 494 4 0 0
T16 494 2 0 0
T21 0 5 0 0
T48 0 5 0 0
T49 0 6 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5738952 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 32 0 0
T32 2567 4 0 0
T35 897 1 0 0
T37 17506 0 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T82 0 2 0 0
T100 0 2 0 0
T164 0 2 0 0
T165 0 1 0 0
T182 0 1 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0
T189 0 1 0 0
T190 0 1 0 0
T191 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT9,T10,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT9,T10,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT9,T10,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT9,T10,T32
10CoveredT1,T2,T4
11CoveredT9,T10,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT9,T10,T32
01CoveredT79,T192
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT9,T10,T32
01CoveredT9,T33,T34
10CoveredT50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT9,T10,T32
1-CoveredT9,T33,T34

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T9,T10,T32
DetectSt 168 Covered T9,T10,T32
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T9,T10,T32


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T9,T10,T32
DebounceSt->IdleSt 163 Covered T164,T77,T174
DetectSt->IdleSt 186 Covered T79,T192
DetectSt->StableSt 191 Covered T9,T10,T32
IdleSt->DebounceSt 148 Covered T9,T10,T32
StableSt->IdleSt 206 Covered T9,T33,T34



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T9,T10,T32
0 1 Covered T9,T10,T32
0 0 Excluded T1,T2,T4 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T32
0 Covered T1,T2,T4


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T9,T10,T32
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T77
DebounceSt - 0 1 1 - - - Covered T9,T10,T32
DebounceSt - 0 1 0 - - - Covered T164,T174,T193
DebounceSt - 0 0 - - - - Covered T9,T10,T32
DetectSt - - - - 1 - - Covered T79,T192
DetectSt - - - - 0 1 - Covered T9,T10,T32
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T9,T33,T34
StableSt - - - - - - 0 Covered T9,T10,T32
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6431240 148 0 0
CntIncr_A 6431240 43743 0 0
CntNoWrap_A 6431240 5736324 0 0
DetectStDropOut_A 6431240 2 0 0
DetectedOut_A 6431240 5207 0 0
DetectedPulseOut_A 6431240 69 0 0
DisabledIdleSt_A 6431240 5587017 0 0
DisabledNoDetection_A 6431240 5589435 0 0
EnterDebounceSt_A 6431240 77 0 0
EnterDetectSt_A 6431240 71 0 0
EnterStableSt_A 6431240 69 0 0
PulseIsPulse_A 6431240 69 0 0
StayInStableSt 6431240 5104 0 0
gen_high_level_sva.HighLevelEvent_A 6431240 5738952 0 0
gen_not_sticky_sva.StableStDropOut_A 6431240 33 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 148 0 0
T9 838 4 0 0
T10 665 2 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 2 0 0
T33 0 6 0 0
T34 0 2 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 2 0 0
T135 0 2 0 0
T136 0 4 0 0
T150 0 4 0 0
T163 429 0 0 0
T182 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 43743 0 0
T9 838 164 0 0
T10 665 35 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 15 0 0
T33 0 210 0 0
T34 0 58 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 60 0 0
T135 0 95 0 0
T136 0 176 0 0
T150 0 90 0 0
T163 429 0 0 0
T182 0 74 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5736324 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 2 0 0
T79 11905 1 0 0
T191 17121 0 0 0
T192 0 1 0 0
T194 492 0 0 0
T195 509 0 0 0
T196 447 0 0 0
T197 1457 0 0 0
T198 503 0 0 0
T199 1097 0 0 0
T200 419 0 0 0
T201 4414 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5207 0 0
T9 838 167 0 0
T10 665 173 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 46 0 0
T33 0 180 0 0
T34 0 24 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 155 0 0
T135 0 110 0 0
T136 0 127 0 0
T150 0 84 0 0
T163 429 0 0 0
T182 0 143 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 69 0 0
T9 838 2 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 1 0 0
T33 0 3 0 0
T34 0 1 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 1 0 0
T135 0 1 0 0
T136 0 2 0 0
T150 0 2 0 0
T163 429 0 0 0
T182 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5587017 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5589435 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 77 0 0
T9 838 2 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 1 0 0
T33 0 3 0 0
T34 0 1 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 1 0 0
T135 0 1 0 0
T136 0 2 0 0
T150 0 2 0 0
T163 429 0 0 0
T182 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 71 0 0
T9 838 2 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 1 0 0
T33 0 3 0 0
T34 0 1 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 1 0 0
T135 0 1 0 0
T136 0 2 0 0
T150 0 2 0 0
T163 429 0 0 0
T182 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 69 0 0
T9 838 2 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 1 0 0
T33 0 3 0 0
T34 0 1 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 1 0 0
T135 0 1 0 0
T136 0 2 0 0
T150 0 2 0 0
T163 429 0 0 0
T182 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 69 0 0
T9 838 2 0 0
T10 665 1 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 1 0 0
T33 0 3 0 0
T34 0 1 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 1 0 0
T135 0 1 0 0
T136 0 2 0 0
T150 0 2 0 0
T163 429 0 0 0
T182 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5104 0 0
T9 838 164 0 0
T10 665 171 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 44 0 0
T33 0 175 0 0
T34 0 23 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T133 0 153 0 0
T135 0 108 0 0
T136 0 124 0 0
T150 0 81 0 0
T163 429 0 0 0
T182 0 140 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5738952 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 33 0 0
T9 838 1 0 0
T10 665 0 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T33 0 1 0 0
T34 0 1 0 0
T58 491 0 0 0
T90 8402 0 0 0
T91 424 0 0 0
T100 0 1 0 0
T108 425 0 0 0
T136 0 1 0 0
T150 0 1 0 0
T163 429 0 0 0
T177 0 1 0 0
T182 0 1 0 0
T183 0 1 0 0
T202 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT9,T11,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT9,T11,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT9,T11,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT9,T11,T32
10CoveredT1,T2,T4
11CoveredT9,T11,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT9,T11,T34
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT9,T11,T34
01CoveredT9,T150,T149
10CoveredT50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT9,T11,T34
1-CoveredT9,T150,T149

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T9,T11,T34
DetectSt 168 Covered T9,T11,T34
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T9,T11,T34


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T9,T11,T34
DebounceSt->IdleSt 163 Covered T203,T77,T204
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T9,T11,T34
IdleSt->DebounceSt 148 Covered T9,T11,T34
StableSt->IdleSt 206 Covered T9,T57,T150



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T9,T11,T34
0 1 Covered T9,T11,T34
0 0 Excluded T1,T2,T4 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T9,T11,T34
0 Covered T1,T2,T4


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T9,T11,T34
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T77
DebounceSt - 0 1 1 - - - Covered T9,T11,T34
DebounceSt - 0 1 0 - - - Covered T203,T162
DebounceSt - 0 0 - - - - Covered T9,T11,T34
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T9,T11,T34
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T9,T150,T149
StableSt - - - - - - 0 Covered T9,T11,T34
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6431240 95 0 0
CntIncr_A 6431240 3011 0 0
CntNoWrap_A 6431240 5736377 0 0
DetectStDropOut_A 6431240 0 0 0
DetectedOut_A 6431240 3620 0 0
DetectedPulseOut_A 6431240 46 0 0
DisabledIdleSt_A 6431240 5585076 0 0
DisabledNoDetection_A 6431240 5587494 0 0
EnterDebounceSt_A 6431240 49 0 0
EnterDetectSt_A 6431240 46 0 0
EnterStableSt_A 6431240 46 0 0
PulseIsPulse_A 6431240 46 0 0
StayInStableSt 6431240 3555 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 6431240 6658 0 0
gen_low_level_sva.LowLevelEvent_A 6431240 5738952 0 0
gen_not_sticky_sva.StableStDropOut_A 6431240 26 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 95 0 0
T9 838 2 0 0
T10 665 0 0 0
T11 646 2 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 2 0 0
T50 0 2 0 0
T57 0 2 0 0
T58 491 0 0 0
T86 0 4 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 4 0 0
T150 0 2 0 0
T151 0 2 0 0
T163 429 0 0 0
T183 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 3011 0 0
T9 838 82 0 0
T10 665 0 0 0
T11 646 41 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 58 0 0
T50 0 18 0 0
T57 0 87 0 0
T58 491 0 0 0
T86 0 99 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 74 0 0
T150 0 45 0 0
T151 0 33 0 0
T163 429 0 0 0
T183 0 79 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5736377 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 3620 0 0
T9 838 13 0 0
T10 665 0 0 0
T11 646 164 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 44 0 0
T50 0 8 0 0
T57 0 51 0 0
T58 491 0 0 0
T86 0 170 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 130 0 0
T150 0 26 0 0
T151 0 100 0 0
T163 429 0 0 0
T183 0 120 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 46 0 0
T9 838 1 0 0
T10 665 0 0 0
T11 646 1 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 1 0 0
T50 0 1 0 0
T57 0 1 0 0
T58 491 0 0 0
T86 0 2 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 2 0 0
T150 0 1 0 0
T151 0 1 0 0
T163 429 0 0 0
T183 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5585076 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5587494 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 49 0 0
T9 838 1 0 0
T10 665 0 0 0
T11 646 1 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 1 0 0
T50 0 1 0 0
T57 0 1 0 0
T58 491 0 0 0
T86 0 2 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 2 0 0
T150 0 1 0 0
T151 0 1 0 0
T163 429 0 0 0
T183 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 46 0 0
T9 838 1 0 0
T10 665 0 0 0
T11 646 1 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 1 0 0
T50 0 1 0 0
T57 0 1 0 0
T58 491 0 0 0
T86 0 2 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 2 0 0
T150 0 1 0 0
T151 0 1 0 0
T163 429 0 0 0
T183 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 46 0 0
T9 838 1 0 0
T10 665 0 0 0
T11 646 1 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 1 0 0
T50 0 1 0 0
T57 0 1 0 0
T58 491 0 0 0
T86 0 2 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 2 0 0
T150 0 1 0 0
T151 0 1 0 0
T163 429 0 0 0
T183 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 46 0 0
T9 838 1 0 0
T10 665 0 0 0
T11 646 1 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 1 0 0
T50 0 1 0 0
T57 0 1 0 0
T58 491 0 0 0
T86 0 2 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 2 0 0
T150 0 1 0 0
T151 0 1 0 0
T163 429 0 0 0
T183 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 3555 0 0
T9 838 12 0 0
T10 665 0 0 0
T11 646 162 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T34 0 42 0 0
T50 0 7 0 0
T57 0 49 0 0
T58 491 0 0 0
T86 0 167 0 0
T90 8402 0 0 0
T91 424 0 0 0
T108 425 0 0 0
T149 0 127 0 0
T150 0 25 0 0
T151 0 98 0 0
T163 429 0 0 0
T183 0 119 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 6658 0 0
T1 353536 26 0 0
T2 599 1 0 0
T3 3608 14 0 0
T4 522 5 0 0
T5 18447 36 0 0
T12 15235 34 0 0
T13 421 2 0 0
T14 403 0 0 0
T15 494 6 0 0
T16 494 5 0 0
T48 0 5 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5738952 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 26 0 0
T9 838 1 0 0
T10 665 0 0 0
T11 646 0 0 0
T31 96676 0 0 0
T32 2567 0 0 0
T58 491 0 0 0
T78 0 1 0 0
T82 0 1 0 0
T86 0 1 0 0
T90 8402 0 0 0
T91 424 0 0 0
T100 0 1 0 0
T108 425 0 0 0
T126 0 1 0 0
T149 0 1 0 0
T150 0 1 0 0
T163 429 0 0 0
T183 0 1 0 0
T205 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T4,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T4,T12
11CoveredT1,T4,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT1,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT1,T6,T9
10CoveredT1,T4,T12
11CoveredT1,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT1,T6,T9
01CoveredT83,T164,T206
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T6,T9
01CoveredT6,T31,T32
10CoveredT50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT1,T6,T9
1-CoveredT6,T31,T32

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T1,T6,T9
DetectSt 168 Covered T1,T6,T9
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T1,T6,T9


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T1,T6,T9
DebounceSt->IdleSt 163 Covered T151,T165,T77
DetectSt->IdleSt 186 Covered T83,T164,T206
DetectSt->StableSt 191 Covered T1,T6,T9
IdleSt->DebounceSt 148 Covered T1,T6,T9
StableSt->IdleSt 206 Covered T1,T6,T31



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T6,T9
0 1 Covered T1,T6,T9
0 0 Excluded T1,T2,T4 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T6,T9
0 Covered T1,T2,T4


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T1,T6,T9
IdleSt 0 - - - - - - Covered T1,T4,T12
DebounceSt - 1 - - - - - Covered T77
DebounceSt - 0 1 1 - - - Covered T1,T6,T9
DebounceSt - 0 1 0 - - - Covered T151,T181,T207
DebounceSt - 0 0 - - - - Covered T1,T6,T9
DetectSt - - - - 1 - - Covered T83,T164,T206
DetectSt - - - - 0 1 - Covered T1,T6,T9
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T6,T31,T32
StableSt - - - - - - 0 Covered T1,T6,T9
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6431240 135 0 0
CntIncr_A 6431240 70672 0 0
CntNoWrap_A 6431240 5736337 0 0
DetectStDropOut_A 6431240 4 0 0
DetectedOut_A 6431240 40979 0 0
DetectedPulseOut_A 6431240 61 0 0
DisabledIdleSt_A 6431240 5547553 0 0
DisabledNoDetection_A 6431240 5549970 0 0
EnterDebounceSt_A 6431240 71 0 0
EnterDetectSt_A 6431240 65 0 0
EnterStableSt_A 6431240 61 0 0
PulseIsPulse_A 6431240 61 0 0
StayInStableSt 6431240 40887 0 0
gen_high_level_sva.HighLevelEvent_A 6431240 5738952 0 0
gen_not_sticky_sva.StableStDropOut_A 6431240 29 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 135 0 0
T1 353536 2 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 2 0 0
T9 0 2 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 2 0 0
T32 0 6 0 0
T33 0 6 0 0
T34 0 2 0 0
T55 0 2 0 0
T86 0 8 0 0
T166 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 70672 0 0
T1 353536 92 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 15 0 0
T9 0 82 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 41005 0 0
T32 0 204 0 0
T33 0 159 0 0
T34 0 58 0 0
T55 0 13 0 0
T86 0 153 0 0
T166 0 86 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5736337 0 0
T1 353536 346573 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 4 0 0
T83 10350 1 0 0
T164 0 1 0 0
T206 0 2 0 0
T208 523 0 0 0
T209 2382 0 0 0
T210 586 0 0 0
T211 426 0 0 0
T212 496 0 0 0
T213 502 0 0 0
T214 490 0 0 0
T215 19723 0 0 0
T216 502 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 40979 0 0
T1 353536 41 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 13 0 0
T9 0 347 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 14214 0 0
T32 0 250 0 0
T33 0 260 0 0
T34 0 127 0 0
T55 0 62 0 0
T86 0 457 0 0
T166 0 62 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 61 0 0
T1 353536 1 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 1 0 0
T9 0 1 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T33 0 3 0 0
T34 0 1 0 0
T55 0 1 0 0
T86 0 4 0 0
T166 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5547553 0 0
T1 353536 346345 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5549970 0 0
T1 353536 346365 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 71 0 0
T1 353536 1 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 1 0 0
T9 0 1 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T33 0 3 0 0
T34 0 1 0 0
T55 0 1 0 0
T86 0 4 0 0
T166 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 65 0 0
T1 353536 1 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 1 0 0
T9 0 1 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T33 0 3 0 0
T34 0 1 0 0
T55 0 1 0 0
T86 0 4 0 0
T166 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 61 0 0
T1 353536 1 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 1 0 0
T9 0 1 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T33 0 3 0 0
T34 0 1 0 0
T55 0 1 0 0
T86 0 4 0 0
T166 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 61 0 0
T1 353536 1 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 1 0 0
T9 0 1 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T33 0 3 0 0
T34 0 1 0 0
T55 0 1 0 0
T86 0 4 0 0
T166 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 40887 0 0
T1 353536 39 0 0
T2 599 0 0 0
T3 3608 0 0 0
T4 522 0 0 0
T5 18447 0 0 0
T6 0 12 0 0
T9 0 345 0 0
T12 15235 0 0 0
T13 421 0 0 0
T14 403 0 0 0
T15 494 0 0 0
T16 494 0 0 0
T31 0 14213 0 0
T32 0 246 0 0
T33 0 255 0 0
T34 0 125 0 0
T55 0 60 0 0
T86 0 451 0 0
T166 0 60 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5738952 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 29 0 0
T6 566 1 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 0 0 0
T21 494 0 0 0
T23 4517 0 0 0
T31 0 1 0 0
T32 0 2 0 0
T33 0 1 0 0
T49 526 0 0 0
T82 0 1 0 0
T86 0 2 0 0
T90 8402 0 0 0
T91 424 0 0 0
T126 0 1 0 0
T159 0 1 0 0
T178 0 1 0 0
T217 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T12
1CoveredT1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T4,T12
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT6,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T4 VC_COV_UNR
1CoveredT6,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT6,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT6,T10,T11
10CoveredT1,T4,T12
11CoveredT6,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT6,T10,T11
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT6,T10,T11
01CoveredT32,T33,T86
10CoveredT50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT6,T10,T11
1-CoveredT32,T33,T86

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6,T10,T11
DetectSt 168 Covered T6,T10,T11
IdleSt 163 Covered T1,T2,T4
StableSt 191 Covered T6,T10,T11


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6,T10,T11
DebounceSt->IdleSt 163 Covered T86,T77
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T6,T10,T11
IdleSt->DebounceSt 148 Covered T6,T10,T11
StableSt->IdleSt 206 Covered T32,T33,T86



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T6,T10,T11
0 1 Covered T6,T10,T11
0 0 Excluded T1,T2,T4 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T10,T11
0 Covered T1,T2,T4


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T6,T10,T11
IdleSt 0 - - - - - - Covered T1,T2,T4
DebounceSt - 1 - - - - - Covered T77
DebounceSt - 0 1 1 - - - Covered T6,T10,T11
DebounceSt - 0 1 0 - - - Covered T86
DebounceSt - 0 0 - - - - Covered T6,T10,T11
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T6,T10,T11
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T32,T33,T86
StableSt - - - - - - 0 Covered T6,T10,T11
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 6431240 74 0 0
CntIncr_A 6431240 2042 0 0
CntNoWrap_A 6431240 5736398 0 0
DetectStDropOut_A 6431240 0 0 0
DetectedOut_A 6431240 2721 0 0
DetectedPulseOut_A 6431240 36 0 0
DisabledIdleSt_A 6431240 5720020 0 0
DisabledNoDetection_A 6431240 5722445 0 0
EnterDebounceSt_A 6431240 38 0 0
EnterDetectSt_A 6431240 36 0 0
EnterStableSt_A 6431240 36 0 0
PulseIsPulse_A 6431240 36 0 0
StayInStableSt 6431240 2665 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 6431240 6397 0 0
gen_low_level_sva.LowLevelEvent_A 6431240 5738952 0 0
gen_not_sticky_sva.StableStDropOut_A 6431240 15 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 74 0 0
T6 566 2 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 2 0 0
T11 0 2 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 6 0 0
T33 0 2 0 0
T36 0 2 0 0
T49 526 0 0 0
T50 0 2 0 0
T86 0 3 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 2 0 0
T167 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 2042 0 0
T6 566 15 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 35 0 0
T11 0 41 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 151 0 0
T33 0 36 0 0
T36 0 54 0 0
T49 526 0 0 0
T50 0 18 0 0
T86 0 54 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 33 0 0
T167 0 41 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5736398 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 2721 0 0
T6 566 113 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 46 0 0
T11 0 165 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 289 0 0
T33 0 14 0 0
T36 0 203 0 0
T49 526 0 0 0
T50 0 8 0 0
T86 0 1 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 103 0 0
T167 0 41 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 36 0 0
T6 566 1 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 1 0 0
T11 0 1 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 3 0 0
T33 0 1 0 0
T36 0 1 0 0
T49 526 0 0 0
T50 0 1 0 0
T86 0 1 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 1 0 0
T167 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5720020 0 0
T1 353536 346575 0 0
T2 599 198 0 0
T3 3608 1604 0 0
T4 522 121 0 0
T5 18447 18015 0 0
T12 15235 14795 0 0
T13 421 20 0 0
T14 403 2 0 0
T15 494 93 0 0
T16 494 93 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5722445 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 38 0 0
T6 566 1 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 1 0 0
T11 0 1 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 3 0 0
T33 0 1 0 0
T36 0 1 0 0
T49 526 0 0 0
T50 0 1 0 0
T86 0 2 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 1 0 0
T167 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 36 0 0
T6 566 1 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 1 0 0
T11 0 1 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 3 0 0
T33 0 1 0 0
T36 0 1 0 0
T49 526 0 0 0
T50 0 1 0 0
T86 0 1 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 1 0 0
T167 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 36 0 0
T6 566 1 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 1 0 0
T11 0 1 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 3 0 0
T33 0 1 0 0
T36 0 1 0 0
T49 526 0 0 0
T50 0 1 0 0
T86 0 1 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 1 0 0
T167 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 36 0 0
T6 566 1 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 1 0 0
T11 0 1 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 3 0 0
T33 0 1 0 0
T36 0 1 0 0
T49 526 0 0 0
T50 0 1 0 0
T86 0 1 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 1 0 0
T167 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 2665 0 0
T6 566 111 0 0
T7 15844 0 0 0
T8 13312 0 0 0
T9 838 0 0 0
T10 665 44 0 0
T11 0 163 0 0
T21 494 0 0 0
T23 4517 0 0 0
T32 0 285 0 0
T33 0 13 0 0
T36 0 201 0 0
T49 526 0 0 0
T50 0 7 0 0
T90 8402 0 0 0
T91 424 0 0 0
T151 0 102 0 0
T167 0 39 0 0
T177 0 326 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 6397 0 0
T1 353536 19 0 0
T2 599 0 0 0
T3 3608 4 0 0
T4 522 6 0 0
T5 18447 41 0 0
T6 0 1 0 0
T12 15235 29 0 0
T13 421 2 0 0
T14 403 0 0 0
T15 494 8 0 0
T16 494 6 0 0
T48 0 5 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 5738952 0 0
T1 353536 346596 0 0
T2 599 199 0 0
T3 3608 1608 0 0
T4 522 122 0 0
T5 18447 18020 0 0
T12 15235 14800 0 0
T13 421 21 0 0
T14 403 3 0 0
T15 494 94 0 0
T16 494 94 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6431240 15 0 0
T32 2567 2 0 0
T33 0 1 0 0
T35 897 0 0 0
T37 17506 0 0 0
T52 803 0 0 0
T59 498 0 0 0
T64 522 0 0 0
T65 527 0 0 0
T86 0 1 0 0
T100 0 1 0 0
T151 0 1 0 0
T159 0 1 0 0
T160 0 1 0 0
T177 0 1 0 0
T181 0 2 0 0
T186 440 0 0 0
T187 403 0 0 0
T188 443 0 0 0
T205 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%