dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.61 97.83 95.24 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.61 97.83 95.24 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.61 97.83 95.24 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.61 97.83 95.24 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.64 95.65 90.48 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT44,T103,T91

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT42,T43,T44
10CoveredT44,T103,T91
11CoveredT44,T103,T91

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT16,T19,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT42,T43,T44 VC_COV_UNR
1CoveredT16,T19,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT16,T19,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T19,T24
10CoveredT44,T103,T91
11CoveredT16,T19,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T19,T24
01CoveredT68,T186,T187
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT16,T19,T24
01CoveredT16,T19,T24
10CoveredT98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT16,T19,T24
1-CoveredT16,T19,T24

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Covered T6
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T16,T19,T24
0 1 Covered T16,T19,T24
0 0 Excluded T42,T43,T44 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T19,T24
0 Covered T42,T43,T44


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T16,T19,T24
IdleSt 0 - - - - - - Covered T44,T103,T91
DebounceSt - 1 - - - - - Covered T97
DebounceSt - 0 1 1 - - - Covered T16,T19,T24
DebounceSt - 0 1 0 - - - Covered T24,T64,T63
DebounceSt - 0 0 - - - - Covered T16,T19,T24
DetectSt - - - - 1 - - Covered T68,T186,T187
DetectSt - - - - 0 1 - Covered T16,T19,T24
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T16,T19,T24
StableSt - - - - - - 0 Covered T16,T19,T24
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802930 151 0 0
CntIncr_A 7802930 185827 0 0
CntNoWrap_A 7802930 7196280 0 0
DetectStDropOut_A 7802930 6 0 0
DetectedOut_A 7802930 203642 0 0
DetectedPulseOut_A 7802930 65 0 0
DisabledIdleSt_A 7802930 6517148 0 0
DisabledNoDetection_A 7802930 6519346 0 0
EnterDebounceSt_A 7802930 80 0 0
EnterDetectSt_A 7802930 71 0 0
EnterStableSt_A 7802930 65 0 0
PulseIsPulse_A 7802930 65 0 0
StayInStableSt 7802930 203548 0 0
gen_high_level_sva.HighLevelEvent_A 7802930 7198689 0 0
gen_not_sticky_sva.StableStDropOut_A 7802930 35 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 151 0 0
T16 625 2 0 0
T19 0 4 0 0
T24 0 3 0 0
T25 0 4 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 3 0 0
T64 0 3 0 0
T68 0 4 0 0
T69 0 2 0 0
T90 0 2 0 0
T106 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 185827 0 0
T16 625 25 0 0
T19 0 130 0 0
T24 0 122 0 0
T25 0 50 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 72 0 0
T64 0 64 0 0
T68 0 174 0 0
T69 0 67 0 0
T90 0 17 0 0
T106 0 59 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7196280 0 0
T16 625 222 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6 0 0
T61 17339 0 0 0
T62 14326 0 0 0
T67 3184 0 0 0
T68 1088 1 0 0
T105 2729 0 0 0
T168 11702 0 0 0
T169 434 0 0 0
T174 422 0 0 0
T175 425 0 0 0
T176 539 0 0 0
T186 0 1 0 0
T187 0 1 0 0
T221 0 1 0 0
T223 0 1 0 0
T258 0 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 203642 0 0
T16 625 9 0 0
T19 0 164 0 0
T24 0 102 0 0
T25 0 52 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 47 0 0
T64 0 12 0 0
T68 0 249 0 0
T69 0 115 0 0
T90 0 65 0 0
T106 0 44 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 65 0 0
T16 625 1 0 0
T19 0 2 0 0
T24 0 1 0 0
T25 0 2 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 1 0 0
T64 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0
T90 0 1 0 0
T106 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6517148 0 0
T16 625 3 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6519346 0 0
T16 625 3 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 80 0 0
T16 625 1 0 0
T19 0 2 0 0
T24 0 2 0 0
T25 0 2 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 2 0 0
T64 0 2 0 0
T68 0 2 0 0
T69 0 1 0 0
T90 0 1 0 0
T106 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 71 0 0
T16 625 1 0 0
T19 0 2 0 0
T24 0 1 0 0
T25 0 2 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 1 0 0
T64 0 1 0 0
T68 0 2 0 0
T69 0 1 0 0
T90 0 1 0 0
T106 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 65 0 0
T16 625 1 0 0
T19 0 2 0 0
T24 0 1 0 0
T25 0 2 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 1 0 0
T64 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0
T90 0 1 0 0
T106 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 65 0 0
T16 625 1 0 0
T19 0 2 0 0
T24 0 1 0 0
T25 0 2 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 1 0 0
T64 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0
T90 0 1 0 0
T106 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 203548 0 0
T16 625 8 0 0
T19 0 161 0 0
T24 0 101 0 0
T25 0 49 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 45 0 0
T64 0 11 0 0
T68 0 248 0 0
T69 0 113 0 0
T90 0 63 0 0
T106 0 42 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7198689 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 35 0 0
T16 625 1 0 0
T19 0 1 0 0
T24 0 1 0 0
T25 0 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T64 0 1 0 0
T68 0 1 0 0
T100 0 2 0 0
T163 0 1 0 0
T209 0 1 0 0
T210 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464597.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323196.88
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT44,T103,T91
1CoveredT42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT44,T103,T91
10CoveredT42,T43,T44
11CoveredT42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT19,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT42,T43,T44 VC_COV_UNR
1CoveredT19,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT19,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT19,T23,T24
10CoveredT42,T44,T103
11CoveredT19,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT19,T23,T24
01CoveredT99,T100
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT19,T23,T24
01CoveredT19,T24,T66
10CoveredT98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT19,T23,T24
1-CoveredT19,T24,T66

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Covered T6
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T19,T23,T24
0 1 Covered T19,T23,T24
0 0 Excluded T42,T43,T44 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T19,T23,T24
0 Covered T42,T43,T44


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T19,T23,T24
IdleSt 0 - - - - - - Covered T42,T43,T44
DebounceSt - 1 - - - - - Covered T97
DebounceSt - 0 1 1 - - - Covered T19,T23,T24
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T19,T23,T24
DetectSt - - - - 1 - - Covered T99,T100
DetectSt - - - - 0 1 - Covered T19,T23,T24
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T19,T24,T66
StableSt - - - - - - 0 Covered T19,T23,T24
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802930 93 0 0
CntIncr_A 7802930 100974 0 0
CntNoWrap_A 7802930 7196338 0 0
DetectStDropOut_A 7802930 2 0 0
DetectedOut_A 7802930 89001 0 0
DetectedPulseOut_A 7802930 44 0 0
DisabledIdleSt_A 7802930 6734600 0 0
DisabledNoDetection_A 7802930 6736803 0 0
EnterDebounceSt_A 7802930 47 0 0
EnterDetectSt_A 7802930 46 0 0
EnterStableSt_A 7802930 44 0 0
PulseIsPulse_A 7802930 44 0 0
StayInStableSt 7802930 88935 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7802930 7092 0 0
gen_low_level_sva.LowLevelEvent_A 7802930 7198689 0 0
gen_not_sticky_sva.StableStDropOut_A 7802930 21 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 93 0 0
T19 3084 2 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 2 0 0
T24 0 4 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 2 0 0
T67 0 2 0 0
T68 0 4 0 0
T75 4139 0 0 0
T76 506 0 0 0
T97 0 1 0 0
T99 0 2 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 2 0 0
T209 0 2 0 0
T233 484 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 100974 0 0
T19 3084 65 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 18 0 0
T24 0 122 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 88 0 0
T67 0 70 0 0
T68 0 174 0 0
T75 4139 0 0 0
T76 506 0 0 0
T97 0 20 0 0
T99 0 15 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 20 0 0
T209 0 56 0 0
T233 484 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7196338 0 0
T16 625 224 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 2 0 0
T69 12228 0 0 0
T77 1564 0 0 0
T99 633 1 0 0
T100 0 1 0 0
T156 483 0 0 0
T157 11005 0 0 0
T158 533 0 0 0
T159 14048 0 0 0
T160 525 0 0 0
T161 1287 0 0 0
T162 17511 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 89001 0 0
T19 3084 40 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 170 0 0
T24 0 156 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 103 0 0
T67 0 46 0 0
T68 0 81 0 0
T75 4139 0 0 0
T76 506 0 0 0
T100 0 38 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 75 0 0
T208 0 74 0 0
T209 0 40 0 0
T233 484 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 44 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T24 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 1 0 0
T67 0 1 0 0
T68 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T100 0 1 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6734600 0 0
T16 625 224 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6736803 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 47 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T24 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 1 0 0
T67 0 1 0 0
T68 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T97 0 1 0 0
T99 0 1 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 46 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T24 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 1 0 0
T67 0 1 0 0
T68 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T99 0 1 0 0
T100 0 2 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 44 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T24 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 1 0 0
T67 0 1 0 0
T68 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T100 0 1 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 44 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T24 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 1 0 0
T67 0 1 0 0
T68 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T100 0 1 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 88935 0 0
T19 3084 39 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 168 0 0
T24 0 153 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 102 0 0
T67 0 44 0 0
T68 0 78 0 0
T75 4139 0 0 0
T76 506 0 0 0
T100 0 36 0 0
T112 522 0 0 0
T113 443 0 0 0
T199 0 74 0 0
T208 0 72 0 0
T209 0 39 0 0
T233 484 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7092 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 12 0 0
T31 526 4 0 0
T32 8457 0 0 0
T33 505 5 0 0
T35 0 7 0 0
T36 0 2 0 0
T44 503 4 0 0
T91 482 10 0 0
T103 525 5 0 0
T111 522 7 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7198689 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 21 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T24 0 1 0 0
T50 6967 0 0 0
T52 469 0 0 0
T66 0 1 0 0
T68 0 1 0 0
T75 4139 0 0 0
T76 506 0 0 0
T112 522 0 0 0
T113 443 0 0 0
T187 0 1 0 0
T198 0 1 0 0
T199 0 1 0 0
T203 0 1 0 0
T209 0 1 0 0
T218 0 1 0 0
T233 484 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT44,T103,T91

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT42,T43,T44
10CoveredT44,T103,T91
11CoveredT44,T103,T91

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT16,T65,T72

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT42,T43,T44 VC_COV_UNR
1CoveredT16,T65,T72

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT16,T65,T66

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T64,T65
10CoveredT44,T103,T91
11CoveredT16,T65,T72

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T65,T66
01CoveredT163,T138,T230
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT16,T65,T66
01CoveredT16,T65,T90
10CoveredT98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT16,T65,T66
1-CoveredT16,T65,T90

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Covered T6
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T16,T65,T72
0 1 Covered T16,T65,T72
0 0 Excluded T42,T43,T44 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T65,T66
0 Covered T42,T43,T44


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T16,T65,T72
IdleSt 0 - - - - - - Covered T44,T103,T91
DebounceSt - 1 - - - - - Covered T97
DebounceSt - 0 1 1 - - - Covered T16,T65,T66
DebounceSt - 0 1 0 - - - Covered T72,T69,T219
DebounceSt - 0 0 - - - - Covered T16,T65,T72
DetectSt - - - - 1 - - Covered T163,T138,T230
DetectSt - - - - 0 1 - Covered T16,T65,T66
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T16,T65,T90
StableSt - - - - - - 0 Covered T16,T65,T66
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802930 140 0 0
CntIncr_A 7802930 160204 0 0
CntNoWrap_A 7802930 7196291 0 0
DetectStDropOut_A 7802930 4 0 0
DetectedOut_A 7802930 191463 0 0
DetectedPulseOut_A 7802930 62 0 0
DisabledIdleSt_A 7802930 6445469 0 0
DisabledNoDetection_A 7802930 6447673 0 0
EnterDebounceSt_A 7802930 74 0 0
EnterDetectSt_A 7802930 66 0 0
EnterStableSt_A 7802930 62 0 0
PulseIsPulse_A 7802930 62 0 0
StayInStableSt 7802930 191370 0 0
gen_high_level_sva.HighLevelEvent_A 7802930 7198689 0 0
gen_not_sticky_sva.StableStDropOut_A 7802930 30 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 140 0 0
T16 625 2 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 2 0 0
T66 0 2 0 0
T67 0 2 0 0
T69 0 3 0 0
T72 0 1 0 0
T90 0 2 0 0
T99 0 4 0 0
T163 0 4 0 0
T209 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 160204 0 0
T16 625 25 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 24 0 0
T66 0 88 0 0
T67 0 70 0 0
T69 0 178 0 0
T72 0 47 0 0
T90 0 17 0 0
T99 0 30 0 0
T163 0 180 0 0
T209 0 56 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7196291 0 0
T16 625 222 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 4 0 0
T138 90396 1 0 0
T139 555 0 0 0
T140 446 0 0 0
T141 803 0 0 0
T142 423 0 0 0
T143 707 0 0 0
T144 5019 0 0 0
T163 2509 1 0 0
T164 502 0 0 0
T165 405 0 0 0
T184 0 1 0 0
T230 0 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 191463 0 0
T16 625 90 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 142 0 0
T66 0 449 0 0
T67 0 46 0 0
T69 0 138 0 0
T90 0 4 0 0
T99 0 153 0 0
T163 0 265 0 0
T209 0 40 0 0
T235 0 42 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 62 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 1 0 0
T66 0 1 0 0
T67 0 1 0 0
T69 0 1 0 0
T90 0 1 0 0
T99 0 2 0 0
T163 0 1 0 0
T209 0 1 0 0
T235 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6445469 0 0
T16 625 3 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6447673 0 0
T16 625 3 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 74 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 1 0 0
T66 0 1 0 0
T67 0 1 0 0
T69 0 2 0 0
T72 0 1 0 0
T90 0 1 0 0
T99 0 2 0 0
T163 0 2 0 0
T209 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 66 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 1 0 0
T66 0 1 0 0
T67 0 1 0 0
T69 0 1 0 0
T90 0 1 0 0
T99 0 2 0 0
T163 0 2 0 0
T209 0 1 0 0
T235 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 62 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 1 0 0
T66 0 1 0 0
T67 0 1 0 0
T69 0 1 0 0
T90 0 1 0 0
T99 0 2 0 0
T163 0 1 0 0
T209 0 1 0 0
T235 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 62 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 1 0 0
T66 0 1 0 0
T67 0 1 0 0
T69 0 1 0 0
T90 0 1 0 0
T99 0 2 0 0
T163 0 1 0 0
T209 0 1 0 0
T235 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 191370 0 0
T16 625 89 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 141 0 0
T66 0 447 0 0
T67 0 44 0 0
T69 0 136 0 0
T90 0 3 0 0
T99 0 150 0 0
T163 0 263 0 0
T209 0 39 0 0
T235 0 40 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7198689 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 30 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T65 0 1 0 0
T90 0 1 0 0
T99 0 1 0 0
T183 0 1 0 0
T186 0 1 0 0
T187 0 1 0 0
T203 0 1 0 0
T209 0 1 0 0
T210 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464597.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323196.88
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT44,T103,T91
1CoveredT42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT44,T103,T91
10CoveredT42,T43,T44
11CoveredT42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT24,T25,T63

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT42,T43,T44 VC_COV_UNR
1CoveredT24,T25,T63

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT24,T25,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT24,T25,T64
10CoveredT42,T44,T103
11CoveredT24,T25,T63

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT24,T25,T63
01CoveredT186,T236,T221
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT24,T25,T63
01CoveredT24,T25,T63
10CoveredT98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT24,T25,T63
1-CoveredT24,T25,T63

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Covered T6
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T24,T25,T63
0 1 Covered T24,T25,T63
0 0 Excluded T42,T43,T44 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T63
0 Covered T42,T43,T44


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T24,T25,T63
IdleSt 0 - - - - - - Covered T42,T43,T44
DebounceSt - 1 - - - - - Covered T97
DebounceSt - 0 1 1 - - - Covered T24,T25,T63
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T24,T25,T63
DetectSt - - - - 1 - - Covered T186,T236,T221
DetectSt - - - - 0 1 - Covered T24,T25,T63
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T24,T25,T63
StableSt - - - - - - 0 Covered T24,T25,T63
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802930 99 0 0
CntIncr_A 7802930 68132 0 0
CntNoWrap_A 7802930 7196332 0 0
DetectStDropOut_A 7802930 3 0 0
DetectedOut_A 7802930 5072 0 0
DetectedPulseOut_A 7802930 46 0 0
DisabledIdleSt_A 7802930 6608908 0 0
DisabledNoDetection_A 7802930 6611102 0 0
EnterDebounceSt_A 7802930 50 0 0
EnterDetectSt_A 7802930 49 0 0
EnterStableSt_A 7802930 46 0 0
PulseIsPulse_A 7802930 46 0 0
StayInStableSt 7802930 5002 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7802930 7051 0 0
gen_low_level_sva.LowLevelEvent_A 7802930 7198689 0 0
gen_not_sticky_sva.StableStDropOut_A 7802930 21 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 99 0 0
T24 851 4 0 0
T25 27520 2 0 0
T54 21373 0 0 0
T57 0 2 0 0
T60 14493 0 0 0
T63 2939 2 0 0
T97 0 1 0 0
T99 0 2 0 0
T100 0 2 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 2 0 0
T209 0 2 0 0
T210 0 2 0 0
T259 526 0 0 0
T260 619 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 68132 0 0
T24 851 122 0 0
T25 27520 93 0 0
T54 21373 0 0 0
T57 0 1332 0 0
T60 14493 0 0 0
T63 2939 36 0 0
T97 0 20 0 0
T99 0 15 0 0
T100 0 89 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 72 0 0
T209 0 56 0 0
T210 0 2265 0 0
T259 526 0 0 0
T260 619 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7196332 0 0
T16 625 224 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 3 0 0
T186 17485 1 0 0
T221 0 1 0 0
T236 625 1 0 0
T261 419 0 0 0
T262 16365 0 0 0
T263 503 0 0 0
T264 31410 0 0 0
T265 487 0 0 0
T266 434 0 0 0
T267 23475 0 0 0
T268 10010 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 5072 0 0
T24 851 156 0 0
T25 27520 40 0 0
T54 21373 0 0 0
T57 0 1230 0 0
T60 14493 0 0 0
T63 2939 176 0 0
T99 0 10 0 0
T100 0 19 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 263 0 0
T208 0 74 0 0
T209 0 91 0 0
T210 0 320 0 0
T259 526 0 0 0
T260 619 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 46 0 0
T24 851 2 0 0
T25 27520 1 0 0
T54 21373 0 0 0
T57 0 1 0 0
T60 14493 0 0 0
T63 2939 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T210 0 1 0 0
T259 526 0 0 0
T260 619 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6608908 0 0
T16 625 224 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6611102 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 50 0 0
T24 851 2 0 0
T25 27520 1 0 0
T54 21373 0 0 0
T57 0 1 0 0
T60 14493 0 0 0
T63 2939 1 0 0
T97 0 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 1 0 0
T209 0 1 0 0
T210 0 1 0 0
T259 526 0 0 0
T260 619 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 49 0 0
T24 851 2 0 0
T25 27520 1 0 0
T54 21373 0 0 0
T57 0 1 0 0
T60 14493 0 0 0
T63 2939 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T210 0 1 0 0
T259 526 0 0 0
T260 619 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 46 0 0
T24 851 2 0 0
T25 27520 1 0 0
T54 21373 0 0 0
T57 0 1 0 0
T60 14493 0 0 0
T63 2939 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T210 0 1 0 0
T259 526 0 0 0
T260 619 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 46 0 0
T24 851 2 0 0
T25 27520 1 0 0
T54 21373 0 0 0
T57 0 1 0 0
T60 14493 0 0 0
T63 2939 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 1 0 0
T208 0 1 0 0
T209 0 1 0 0
T210 0 1 0 0
T259 526 0 0 0
T260 619 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 5002 0 0
T24 851 153 0 0
T25 27520 39 0 0
T54 21373 0 0 0
T57 0 1228 0 0
T60 14493 0 0 0
T63 2939 175 0 0
T99 0 9 0 0
T100 0 18 0 0
T131 521 0 0 0
T132 427 0 0 0
T188 422 0 0 0
T206 0 261 0 0
T208 0 72 0 0
T209 0 89 0 0
T210 0 319 0 0
T259 526 0 0 0
T260 619 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7051 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 12 0 0
T31 526 6 0 0
T32 8457 0 0 0
T33 505 4 0 0
T35 0 6 0 0
T36 0 1 0 0
T44 503 5 0 0
T91 482 12 0 0
T103 525 5 0 0
T111 522 4 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7198689 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 21 0 0
T24 851 1 0 0
T25 27520 1 0 0
T54 21373 0 0 0
T60 14493 0 0 0
T63 2939 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T127 0 1 0 0
T131 521 0 0 0
T132 427 0 0 0
T186 0 1 0 0
T188 422 0 0 0
T203 0 1 0 0
T210 0 1 0 0
T244 0 1 0 0
T259 526 0 0 0
T260 619 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT42,T43,T44
10CoveredT42,T43,T44
11CoveredT42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT19,T23,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT42,T43,T44 VC_COV_UNR
1CoveredT19,T23,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT19,T23,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT19,T23,T25
10CoveredT42,T43,T44
11CoveredT19,T23,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT19,T23,T25
01CoveredT25,T100,T127
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT19,T23,T25
01CoveredT23,T25,T63
10CoveredT98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT19,T23,T25
1-CoveredT23,T25,T63

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Covered T6
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T19,T23,T25
0 1 Covered T19,T23,T25
0 0 Excluded T42,T43,T44 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T19,T23,T25
0 Covered T42,T43,T44


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T19,T23,T25
IdleSt 0 - - - - - - Covered T42,T43,T44
DebounceSt - 1 - - - - - Covered T97
DebounceSt - 0 1 1 - - - Covered T19,T23,T25
DebounceSt - 0 1 0 - - - Covered T208,T248,T198
DebounceSt - 0 0 - - - - Covered T19,T23,T25
DetectSt - - - - 1 - - Covered T25,T100,T127
DetectSt - - - - 0 1 - Covered T19,T23,T25
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T23,T25,T63
StableSt - - - - - - 0 Covered T19,T23,T25
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802930 132 0 0
CntIncr_A 7802930 69728 0 0
CntNoWrap_A 7802930 7196299 0 0
DetectStDropOut_A 7802930 7 0 0
DetectedOut_A 7802930 109178 0 0
DetectedPulseOut_A 7802930 57 0 0
DisabledIdleSt_A 7802930 6868088 0 0
DisabledNoDetection_A 7802930 6870296 0 0
EnterDebounceSt_A 7802930 68 0 0
EnterDetectSt_A 7802930 64 0 0
EnterStableSt_A 7802930 57 0 0
PulseIsPulse_A 7802930 57 0 0
StayInStableSt 7802930 109096 0 0
gen_high_level_sva.HighLevelEvent_A 7802930 7198689 0 0
gen_not_sticky_sva.StableStDropOut_A 7802930 31 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 132 0 0
T19 3084 2 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 2 0 0
T25 0 6 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 2 0 0
T63 0 4 0 0
T67 0 2 0 0
T69 0 4 0 0
T75 4139 0 0 0
T76 506 0 0 0
T97 0 1 0 0
T112 522 0 0 0
T113 443 0 0 0
T209 0 2 0 0
T233 484 0 0 0
T235 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 69728 0 0
T19 3084 65 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 18 0 0
T25 0 189 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 1332 0 0
T63 0 72 0 0
T67 0 70 0 0
T69 0 156 0 0
T75 4139 0 0 0
T76 506 0 0 0
T97 0 20 0 0
T112 522 0 0 0
T113 443 0 0 0
T209 0 56 0 0
T233 484 0 0 0
T235 0 98 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7196299 0 0
T16 625 224 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7 0 0
T25 27520 1 0 0
T100 2725 1 0 0
T127 24866 1 0 0
T177 1478 0 0 0
T184 0 1 0 0
T188 422 0 0 0
T223 0 1 0 0
T247 0 1 0 0
T269 0 1 0 0
T270 1414 0 0 0
T271 2226 0 0 0
T272 403 0 0 0
T273 522 0 0 0
T274 406 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 109178 0 0
T19 3084 336 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 158 0 0
T25 0 146 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 40 0 0
T63 0 251 0 0
T67 0 29 0 0
T69 0 251 0 0
T75 4139 0 0 0
T76 506 0 0 0
T112 522 0 0 0
T113 443 0 0 0
T206 0 40 0 0
T209 0 40 0 0
T233 484 0 0 0
T235 0 141 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 57 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T25 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 1 0 0
T63 0 2 0 0
T67 0 1 0 0
T69 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T112 522 0 0 0
T113 443 0 0 0
T206 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0
T235 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6868088 0 0
T16 625 224 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6870296 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 68 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T25 0 3 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 1 0 0
T63 0 2 0 0
T67 0 1 0 0
T69 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T97 0 1 0 0
T112 522 0 0 0
T113 443 0 0 0
T209 0 1 0 0
T233 484 0 0 0
T235 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 64 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T25 0 3 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 1 0 0
T63 0 2 0 0
T67 0 1 0 0
T69 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T112 522 0 0 0
T113 443 0 0 0
T206 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0
T235 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 57 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T25 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 1 0 0
T63 0 2 0 0
T67 0 1 0 0
T69 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T112 522 0 0 0
T113 443 0 0 0
T206 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0
T235 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 57 0 0
T19 3084 1 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 1 0 0
T25 0 2 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 1 0 0
T63 0 2 0 0
T67 0 1 0 0
T69 0 2 0 0
T75 4139 0 0 0
T76 506 0 0 0
T112 522 0 0 0
T113 443 0 0 0
T206 0 1 0 0
T209 0 1 0 0
T233 484 0 0 0
T235 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 109096 0 0
T19 3084 334 0 0
T20 6103 0 0 0
T21 17977 0 0 0
T23 0 157 0 0
T25 0 144 0 0
T50 6967 0 0 0
T52 469 0 0 0
T57 0 39 0 0
T63 0 248 0 0
T67 0 28 0 0
T69 0 248 0 0
T75 4139 0 0 0
T76 506 0 0 0
T112 522 0 0 0
T113 443 0 0 0
T206 0 38 0 0
T209 0 39 0 0
T233 484 0 0 0
T235 0 139 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7198689 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 31 0 0
T23 677 1 0 0
T24 851 0 0 0
T25 27520 2 0 0
T54 21373 0 0 0
T57 0 1 0 0
T60 14493 0 0 0
T63 2939 1 0 0
T67 0 1 0 0
T69 0 1 0 0
T131 521 0 0 0
T186 0 1 0 0
T187 0 1 0 0
T188 422 0 0 0
T208 0 1 0 0
T209 0 1 0 0
T259 526 0 0 0
T260 619 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT42,T43,T44
10CoveredT42,T43,T44
11CoveredT42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT16,T23,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT42,T43,T44 VC_COV_UNR
1CoveredT16,T23,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT42,T43,T44
1CoveredT16,T23,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T23,T25
10CoveredT42,T43,T44
11CoveredT16,T23,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T23,T25
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT16,T23,T25
01CoveredT100,T256,T203
10CoveredT98

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT16,T23,T25
1-CoveredT100,T256,T203

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T6
DetectSt 168 Covered T6
IdleSt 163 Covered T6
StableSt 191 Covered T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T6
DebounceSt->IdleSt 163 Covered T6
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T6
IdleSt->DebounceSt 148 Covered T6
StableSt->IdleSt 206 Covered T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T16,T23,T25
0 1 Covered T16,T23,T25
0 0 Excluded T42,T43,T44 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T23,T25
0 Covered T42,T43,T44


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T16,T23,T25
IdleSt 0 - - - - - - Covered T42,T43,T44
DebounceSt - 1 - - - - - Covered T97
DebounceSt - 0 1 1 - - - Covered T16,T23,T25
DebounceSt - 0 1 0 - - - Covered T63
DebounceSt - 0 0 - - - - Covered T16,T23,T25
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T16,T23,T25
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T100,T256,T203
StableSt - - - - - - 0 Covered T16,T23,T25
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T42,T43,T44


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7802930 66 0 0
CntIncr_A 7802930 3169 0 0
CntNoWrap_A 7802930 7196365 0 0
DetectStDropOut_A 7802930 0 0 0
DetectedOut_A 7802930 2334 0 0
DetectedPulseOut_A 7802930 32 0 0
DisabledIdleSt_A 7802930 6906223 0 0
DisabledNoDetection_A 7802930 6908435 0 0
EnterDebounceSt_A 7802930 35 0 0
EnterDetectSt_A 7802930 32 0 0
EnterStableSt_A 7802930 32 0 0
PulseIsPulse_A 7802930 32 0 0
StayInStableSt 7802930 2286 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7802930 7688 0 0
gen_low_level_sva.LowLevelEvent_A 7802930 7198689 0 0
gen_not_sticky_sva.StableStDropOut_A 7802930 15 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 66 0 0
T16 625 2 0 0
T23 0 2 0 0
T25 0 2 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T63 0 1 0 0
T69 0 2 0 0
T97 0 1 0 0
T99 0 2 0 0
T100 0 2 0 0
T163 0 2 0 0
T256 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 3169 0 0
T16 625 25 0 0
T23 0 18 0 0
T25 0 25 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T57 0 1189 0 0
T63 0 36 0 0
T69 0 89 0 0
T97 0 20 0 0
T99 0 15 0 0
T100 0 89 0 0
T163 0 90 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7196365 0 0
T16 625 222 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 2334 0 0
T16 625 158 0 0
T23 0 75 0 0
T25 0 47 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T69 0 42 0 0
T99 0 57 0 0
T100 0 40 0 0
T163 0 134 0 0
T203 0 143 0 0
T207 0 40 0 0
T256 0 25 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 32 0 0
T16 625 1 0 0
T23 0 1 0 0
T25 0 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T69 0 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T163 0 1 0 0
T203 0 2 0 0
T207 0 1 0 0
T256 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6906223 0 0
T16 625 3 0 0
T29 500 99 0 0
T30 2227 624 0 0
T31 526 125 0 0
T42 1536 334 0 0
T43 681 280 0 0
T44 503 102 0 0
T91 482 81 0 0
T103 525 124 0 0
T111 522 121 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 6908435 0 0
T16 625 3 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 35 0 0
T16 625 1 0 0
T23 0 1 0 0
T25 0 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T57 0 1 0 0
T63 0 1 0 0
T69 0 1 0 0
T97 0 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T163 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 32 0 0
T16 625 1 0 0
T23 0 1 0 0
T25 0 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T69 0 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T163 0 1 0 0
T203 0 2 0 0
T207 0 1 0 0
T256 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 32 0 0
T16 625 1 0 0
T23 0 1 0 0
T25 0 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T69 0 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T163 0 1 0 0
T203 0 2 0 0
T207 0 1 0 0
T256 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 32 0 0
T16 625 1 0 0
T23 0 1 0 0
T25 0 1 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T69 0 1 0 0
T99 0 1 0 0
T100 0 1 0 0
T163 0 1 0 0
T203 0 2 0 0
T207 0 1 0 0
T256 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 2286 0 0
T16 625 156 0 0
T23 0 73 0 0
T25 0 45 0 0
T29 500 0 0 0
T30 2227 0 0 0
T31 526 0 0 0
T32 8457 0 0 0
T33 505 0 0 0
T34 402 0 0 0
T35 440 0 0 0
T36 409 0 0 0
T37 503 0 0 0
T69 0 40 0 0
T99 0 55 0 0
T100 0 39 0 0
T163 0 132 0 0
T203 0 140 0 0
T207 0 38 0 0
T256 0 24 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7688 0 0
T16 625 1 0 0
T29 500 0 0 0
T30 2227 12 0 0
T31 526 5 0 0
T33 0 3 0 0
T42 1536 3 0 0
T43 681 3 0 0
T44 503 4 0 0
T91 482 15 0 0
T103 525 7 0 0
T111 522 5 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 7198689 0 0
T16 625 225 0 0
T29 500 100 0 0
T30 2227 627 0 0
T31 526 126 0 0
T42 1536 336 0 0
T43 681 281 0 0
T44 503 103 0 0
T91 482 82 0 0
T103 525 125 0 0
T111 522 122 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7802930 15 0 0
T100 2725 1 0 0
T194 0 1 0 0
T198 0 1 0 0
T203 0 1 0 0
T222 0 2 0 0
T245 0 2 0 0
T249 0 1 0 0
T256 986 1 0 0
T270 1414 0 0 0
T271 2226 0 0 0
T272 403 0 0 0
T273 522 0 0 0
T274 406 0 0 0
T275 0 1 0 0
T276 0 1 0 0
T277 10746 0 0 0
T278 17460 0 0 0
T279 430 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%