Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T11 T21 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T11 T21 T30 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T7 T29 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T7 T29 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T7 T29 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T7 T29 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T7 T29 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T7 T29 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T7 T29 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T7 T29 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T7 T29 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T7 T29 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T7 T29 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T7 T29 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T7 T29 
163        1/1                    state_d = IdleSt;
           Tests:       T21 T56 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T7 T29 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T7 T29 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T7 T29 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T7 T29 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T21 T56 T120 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T7 T29 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T7 T29 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T7 T29 
186        1/1                    state_d = IdleSt;
           Tests:       T11 T21 T56 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T56 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T7 T29 
191        1/1                      state_d = StableSt;
           Tests:       T1 T7 T29 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T7 T29 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T7 T29 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T7 T29 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T7 T29 
206        1/1                    state_d = IdleSt;
           Tests:       T21 T30 T40 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T7 T29 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T21,T30
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T21,T30
1	0	Covered	T11,T21,T30
1	1	Covered	T1,T7,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T29
0	1	Covered	T11,T21,T56
1	0	Covered	T11,T21,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T29
0	1	Covered	T21,T30,T40
1	0	Covered	T21,T322,T323

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T29
1	-	Covered	T21,T30,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T29
DetectSt	168	Covered	T1,T7,T29
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T7,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T29
DebounceSt->IdleSt	163	Covered	T21,T56,T120
DetectSt->IdleSt	186	Covered	T11,T21,T56
DetectSt->StableSt	191	Covered	T1,T7,T29
IdleSt->DebounceSt	148	Covered	T1,T7,T29
StableSt->IdleSt	206	Covered	T21,T30,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T29
0	1	Covered	T1,T7,T29
0	0	Covered	T1,T2,T4

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T29
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T29
IdleSt	0	-	-	-	-	-	-	Covered	T11,T21,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T56,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T29
DetectSt	-	-	-	-	1	-	-	Covered	T11,T21,T56
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T29
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T29
StableSt	-	-	-	-	-	-	1	Covered	T21,T30,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T29
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	3433	0	0
CntIncr_A	7014086	112408	0	0
CntNoWrap_A	7014086	6361417	0	0
DetectStDropOut_A	7014086	490	0	0
DetectedOut_A	7014086	79352	0	0
DetectedPulseOut_A	7014086	979	0	0
DisabledIdleSt_A	7014086	5902790	0	0
DisabledNoDetection_A	7014086	5904955	0	0
EnterDebounceSt_A	7014086	1726	0	0
EnterDetectSt_A	7014086	1709	0	0
EnterStableSt_A	7014086	979	0	0
PulseIsPulse_A	7014086	979	0	0
StayInStableSt	7014086	78239	0	0
gen_high_event_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	827	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	3433	0	0
T1	509	2	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	2	0	0
T11	0	10	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	16	0	0
T29	0	2	0	0
T30	0	42	0	0
T40	0	54	0	0
T56	0	16	0	0
T59	0	2	0	0
T87	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	112408	0	0
T1	509	21	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	21	0	0
T11	0	210	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	485	0	0
T29	0	21	0	0
T30	0	1071	0	0
T40	0	1944	0	0
T56	0	647	0	0
T59	0	21	0	0
T87	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6361417	0	0
T1	509	106	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	490	0	0
T11	30017	3	0	0
T21	0	1	0	0
T51	1595	0	0	0
T56	0	1	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T89	0	12	0	0
T90	0	28	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	14	0	0
T265	0	15	0	0
T324	0	23	0	0
T325	0	30	0	0
T326	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	79352	0	0
T1	509	83	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	81	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	356	0	0
T29	0	31	0	0
T30	0	154	0	0
T40	0	2982	0	0
T56	0	476	0	0
T59	0	83	0	0
T87	0	78	0	0
T88	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	979	0	0
T1	509	1	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	5	0	0
T29	0	1	0	0
T30	0	21	0	0
T40	0	27	0	0
T56	0	5	0	0
T59	0	1	0	0
T87	0	1	0	0
T88	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5902790	0	0
T1	509	4	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5904955	0	0
T1	509	4	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	1726	0	0
T1	509	1	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T11	0	5	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	9	0	0
T29	0	1	0	0
T30	0	21	0	0
T40	0	27	0	0
T56	0	9	0	0
T59	0	1	0	0
T87	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	1709	0	0
T1	509	1	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T11	0	5	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	7	0	0
T29	0	1	0	0
T30	0	21	0	0
T40	0	27	0	0
T56	0	7	0	0
T59	0	1	0	0
T87	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	979	0	0
T1	509	1	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	5	0	0
T29	0	1	0	0
T30	0	21	0	0
T40	0	27	0	0
T56	0	5	0	0
T59	0	1	0	0
T87	0	1	0	0
T88	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	979	0	0
T1	509	1	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	5	0	0
T29	0	1	0	0
T30	0	21	0	0
T40	0	27	0	0
T56	0	5	0	0
T59	0	1	0	0
T87	0	1	0	0
T88	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	78239	0	0
T1	509	81	0	0
T2	486	0	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	79	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	351	0	0
T29	0	29	0	0
T30	0	133	0	0
T40	0	2949	0	0
T56	0	471	0	0
T59	0	81	0	0
T87	0	76	0	0
T88	0	51	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	827	0	0
T21	7856	4	0	0
T30	0	21	0	0
T32	20109	0	0	0
T40	0	21	0	0
T56	0	5	0	0
T72	1746	0	0	0
T77	524	0	0	0
T88	0	3	0	0
T91	0	7	0	0
T92	0	21	0	0
T124	0	19	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T199	0	1	0	0
T248	834	0	0	0
T327	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T2 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T4 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T2 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T4 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T4 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T4 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T4 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T4 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T4 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T4 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T4 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T2 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T2 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T2 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T21 T56 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T2 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T2 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T2 T7 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T31 T29 T57 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T2 T7 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T7 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T2 T7 
186        1/1                    state_d = IdleSt;
           Tests:       T21 T42 T56 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T42 T56 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T2 T7 
191        1/1                      state_d = StableSt;
           Tests:       T1 T2 T7 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T2 T7 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T2 T7 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T2 T7 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T2 T7 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T7 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T2 T7 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T31
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T31
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T2,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T31
1	0	Covered	T28,T11,T51
1	1	Covered	T1,T2,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T42,T121,T136
1	0	Covered	T21,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T31
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T31,T29,T57
DetectSt->IdleSt	186	Covered	T21,T42,T56
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T31
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T31
0	1	Covered	T1,T2,T31
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T29,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T31
DetectSt	-	-	-	-	1	-	-	Covered	T21,T42,T56
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	940	0	0
CntIncr_A	7014086	47914	0	0
CntNoWrap_A	7014086	6363910	0	0
DetectStDropOut_A	7014086	57	0	0
DetectedOut_A	7014086	15166	0	0
DetectedPulseOut_A	7014086	379	0	0
DisabledIdleSt_A	7014086	5997376	0	0
DisabledNoDetection_A	7014086	5999041	0	0
EnterDebounceSt_A	7014086	503	0	0
EnterDetectSt_A	7014086	440	0	0
EnterStableSt_A	7014086	379	0	0
PulseIsPulse_A	7014086	379	0	0
StayInStableSt	7014086	14739	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	940	0	0
T1	509	2	0	0
T2	486	2	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	2	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T57	0	1	0	0
T59	0	2	0	0
T87	0	2	0	0
T132	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	47914	0	0
T1	509	25	0	0
T2	486	25	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	25	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T28	0	20	0	0
T29	0	20	0	0
T31	0	20	0	0
T57	0	20	0	0
T59	0	25	0	0
T87	0	25	0	0
T132	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6363910	0	0
T1	509	106	0	0
T2	486	83	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	57	0	0
T41	33129	0	0	0
T42	10965	8	0	0
T54	8961	0	0	0
T56	7997	0	0	0
T73	148631	0	0	0
T80	497	0	0	0
T121	0	4	0	0
T136	0	4	0	0
T137	0	1	0	0
T138	0	6	0	0
T139	0	4	0	0
T140	0	3	0	0
T142	0	1	0	0
T143	0	6	0	0
T144	0	8	0	0
T152	4402	0	0	0
T153	403	0	0	0
T154	424	0	0	0
T155	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	15166	0	0
T1	509	3	0	0
T2	486	3	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	3	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	92	0	0
T32	0	36	0	0
T40	0	278	0	0
T56	0	99	0	0
T59	0	3	0	0
T87	0	4	0	0
T132	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	379	0	0
T1	509	1	0	0
T2	486	1	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	1	0	0
T32	0	5	0	0
T40	0	5	0	0
T56	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5997376	0	0
T1	509	26	0	0
T2	486	4	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5999041	0	0
T1	509	26	0	0
T2	486	4	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	503	0	0
T1	509	1	0	0
T2	486	1	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T132	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	440	0	0
T1	509	1	0	0
T2	486	1	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	2	0	0
T32	0	5	0	0
T40	0	5	0	0
T42	0	8	0	0
T59	0	1	0	0
T87	0	1	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	379	0	0
T1	509	1	0	0
T2	486	1	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	1	0	0
T32	0	5	0	0
T40	0	5	0	0
T56	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	379	0	0
T1	509	1	0	0
T2	486	1	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	1	0	0
T32	0	5	0	0
T40	0	5	0	0
T56	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	14739	0	0
T1	509	2	0	0
T2	486	2	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	2	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	91	0	0
T32	0	31	0	0
T40	0	273	0	0
T56	0	98	0	0
T59	0	2	0	0
T87	0	3	0	0
T132	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	329	0	0
T1	509	1	0	0
T2	486	1	0	0
T3	481	0	0	0
T4	666	0	0	0
T7	0	1	0	0
T12	747	0	0	0
T13	523	0	0	0
T14	412	0	0	0
T15	423	0	0	0
T16	1038	0	0	0
T17	426	0	0	0
T21	0	1	0	0
T32	0	5	0	0
T40	0	5	0	0
T56	0	1	0	0
T59	0	1	0	0
T87	0	1	0	0
T132	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T11 T21 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T11 T21 T30 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T21 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T11 T21 T30 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T11 T21 T30 
129        1/1              cnt_en = 1'b0;
           Tests:       T11 T21 T30 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T11 T21 T30 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T11 T21 T30 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T11 T21 T30 
139                     
140        1/1              unique case (state_q)
           Tests:       T11 T21 T30 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T11 T21 T30 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T21 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T21 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T21 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T21 T56 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T21 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T21 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T21 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T21 T56 T120 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T21 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T21 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T11 T21 T30 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T30 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T21 T30 
191        1/1                      state_d = StableSt;
           Tests:       T21 T40 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T21 T40 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T21 T40 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T21 T40 T56 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T21 T40 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T21 T40 T56 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T21 T40 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T21,T30
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T21,T30
1	0	Covered	T11,T21,T30
1	1	Covered	T11,T21,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T30
0	1	Covered	T11,T21,T56
1	0	Covered	T11,T21,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T40,T56
0	1	Covered	T21,T40,T56
1	0	Covered	T21

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T40,T56
1	-	Covered	T21,T40,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T21,T30
DetectSt	168	Covered	T11,T21,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T21,T40,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T21,T30
DebounceSt->IdleSt	163	Covered	T21,T56,T120
DetectSt->IdleSt	186	Covered	T11,T21,T30
DetectSt->StableSt	191	Covered	T21,T40,T56
IdleSt->DebounceSt	148	Covered	T11,T21,T30
StableSt->IdleSt	206	Covered	T21,T40,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T21,T30
0	1	Covered	T11,T21,T30
0	0	Covered	T1,T2,T4

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T30
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T11,T21,T30
IdleSt	0	-	-	-	-	-	-	Covered	T11,T21,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T21,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T56,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T21,T30
DetectSt	-	-	-	-	1	-	-	Covered	T11,T21,T30
DetectSt	-	-	-	-	0	1	-	Covered	T21,T40,T56
DetectSt	-	-	-	-	0	0	-	Covered	T11,T21,T30
StableSt	-	-	-	-	-	-	1	Covered	T21,T40,T56
StableSt	-	-	-	-	-	-	0	Covered	T21,T40,T56
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	3164	0	0
CntIncr_A	7014086	101864	0	0
CntNoWrap_A	7014086	6361686	0	0
DetectStDropOut_A	7014086	480	0	0
DetectedOut_A	7014086	69205	0	0
DetectedPulseOut_A	7014086	860	0	0
DisabledIdleSt_A	7014086	5910107	0	0
DisabledNoDetection_A	7014086	5912262	0	0
EnterDebounceSt_A	7014086	1593	0	0
EnterDetectSt_A	7014086	1573	0	0
EnterStableSt_A	7014086	860	0	0
PulseIsPulse_A	7014086	860	0	0
StayInStableSt	7014086	68201	0	0
gen_high_event_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	715	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	3164	0	0
T11	30017	24	0	0
T21	0	16	0	0
T30	0	16	0	0
T40	0	48	0	0
T51	1595	0	0	0
T56	0	16	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	44	0	0
T89	0	4	0	0
T90	0	56	0	0
T91	0	16	0	0
T92	0	28	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	101864	0	0
T11	30017	507	0	0
T21	0	639	0	0
T30	0	447	0	0
T40	0	1656	0	0
T51	1595	0	0	0
T56	0	675	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	814	0	0
T89	0	146	0	0
T90	0	1228	0	0
T91	0	360	0	0
T92	0	882	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6361686	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	480	0	0
T11	30017	10	0	0
T21	0	1	0	0
T44	0	10	0	0
T51	1595	0	0	0
T56	0	1	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T89	0	2	0	0
T90	0	28	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	2	0	0
T324	0	27	0	0
T325	0	23	0	0
T327	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	69205	0	0
T21	7856	432	0	0
T32	20109	0	0	0
T40	0	2301	0	0
T56	0	386	0	0
T72	1746	0	0	0
T77	524	0	0	0
T88	0	2141	0	0
T91	0	950	0	0
T92	0	679	0	0
T124	0	513	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T199	0	2656	0	0
T248	834	0	0	0
T328	0	693	0	0
T329	0	1707	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	860	0	0
T21	7856	5	0	0
T32	20109	0	0	0
T40	0	24	0	0
T56	0	5	0	0
T72	1746	0	0	0
T77	524	0	0	0
T88	0	22	0	0
T91	0	8	0	0
T92	0	14	0	0
T124	0	26	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T199	0	30	0	0
T248	834	0	0	0
T328	0	12	0	0
T329	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5910107	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5912262	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	1593	0	0
T11	30017	12	0	0
T21	0	9	0	0
T30	0	8	0	0
T40	0	24	0	0
T51	1595	0	0	0
T56	0	9	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	22	0	0
T89	0	2	0	0
T90	0	28	0	0
T91	0	8	0	0
T92	0	14	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	1573	0	0
T11	30017	12	0	0
T21	0	7	0	0
T30	0	8	0	0
T40	0	24	0	0
T51	1595	0	0	0
T56	0	7	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	22	0	0
T89	0	2	0	0
T90	0	28	0	0
T91	0	8	0	0
T92	0	14	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	860	0	0
T21	7856	5	0	0
T32	20109	0	0	0
T40	0	24	0	0
T56	0	5	0	0
T72	1746	0	0	0
T77	524	0	0	0
T88	0	22	0	0
T91	0	8	0	0
T92	0	14	0	0
T124	0	26	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T199	0	30	0	0
T248	834	0	0	0
T328	0	12	0	0
T329	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	860	0	0
T21	7856	5	0	0
T32	20109	0	0	0
T40	0	24	0	0
T56	0	5	0	0
T72	1746	0	0	0
T77	524	0	0	0
T88	0	22	0	0
T91	0	8	0	0
T92	0	14	0	0
T124	0	26	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T199	0	30	0	0
T248	834	0	0	0
T328	0	12	0	0
T329	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	68201	0	0
T21	7856	427	0	0
T32	20109	0	0	0
T40	0	2273	0	0
T56	0	381	0	0
T72	1746	0	0	0
T77	524	0	0	0
T88	0	2113	0	0
T91	0	940	0	0
T92	0	664	0	0
T124	0	486	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T199	0	2625	0	0
T248	834	0	0	0
T328	0	681	0	0
T329	0	1699	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	715	0	0
T21	7856	4	0	0
T32	20109	0	0	0
T40	0	20	0	0
T56	0	5	0	0
T72	1746	0	0	0
T77	524	0	0	0
T88	0	16	0	0
T91	0	6	0	0
T92	0	13	0	0
T124	0	25	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T199	0	29	0	0
T248	834	0	0	0
T328	0	12	0	0
T329	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T6 T11 T21 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T4 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T21 T32 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T4 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T4 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T4 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T4 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T4 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T4 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T4 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T4 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T21 T32 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T21 T32 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T21 T32 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T21 T32 
163        1/1                    state_d = IdleSt;
           Tests:       T21 T56 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T21 T32 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T21 T32 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T21 T32 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T21 T32 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T6 T42 T178 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T21 T32 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T21 T32 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T21 T32 
186        1/1                    state_d = IdleSt;
           Tests:       T21 T56 T137 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 T137 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T21 T32 
191        1/1                      state_d = StableSt;
           Tests:       T6 T21 T32 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T21 T32 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T21 T32 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T21 T32 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T21 T32 
206        1/1                    state_d = IdleSt;
           Tests:       T6 T21 T32 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T21 T32 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T11,T21
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T21
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T21,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T21,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T21,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T21
1	0	Covered	T28,T11,T51
1	1	Covered	T6,T21,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T32
0	1	Covered	T137,T139,T330
1	0	Covered	T21,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T32
0	1	Covered	T6,T32,T40
1	0	Covered	T21,T56,T122

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T21,T32
1	-	Covered	T6,T32,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T21,T32
DetectSt	168	Covered	T6,T21,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T21,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T21,T32
DebounceSt->IdleSt	163	Covered	T6,T21,T42
DetectSt->IdleSt	186	Covered	T21,T56,T137
DetectSt->StableSt	191	Covered	T6,T21,T32
IdleSt->DebounceSt	148	Covered	T6,T21,T32
StableSt->IdleSt	206	Covered	T6,T21,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T21,T32
0	1	Covered	T6,T21,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T21,T32
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T21,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T21,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T42,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T21,T32
DetectSt	-	-	-	-	1	-	-	Covered	T21,T56,T137
DetectSt	-	-	-	-	0	1	-	Covered	T6,T21,T32
DetectSt	-	-	-	-	0	0	-	Covered	T6,T21,T32
StableSt	-	-	-	-	-	-	1	Covered	T6,T21,T32
StableSt	-	-	-	-	-	-	0	Covered	T6,T21,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	964	0	0
CntIncr_A	7014086	54789	0	0
CntNoWrap_A	7014086	6363886	0	0
DetectStDropOut_A	7014086	70	0	0
DetectedOut_A	7014086	17885	0	0
DetectedPulseOut_A	7014086	384	0	0
DisabledIdleSt_A	7014086	5997997	0	0
DisabledNoDetection_A	7014086	5999704	0	0
EnterDebounceSt_A	7014086	506	0	0
EnterDetectSt_A	7014086	459	0	0
EnterStableSt_A	7014086	384	0	0
PulseIsPulse_A	7014086	384	0	0
StayInStableSt	7014086	17448	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	327	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	964	0	0
T6	7579	19	0	0
T8	627	0	0	0
T21	0	8	0	0
T29	456	0	0	0
T32	0	4	0	0
T40	0	6	0	0
T41	0	8	0	0
T42	0	19	0	0
T56	0	8	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	12	0	0
T174	0	28	0	0
T178	0	17	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	54789	0	0
T6	7579	1576	0	0
T8	627	0	0	0
T21	0	267	0	0
T29	456	0	0	0
T32	0	264	0	0
T40	0	294	0	0
T41	0	628	0	0
T42	0	687	0	0
T56	0	219	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	378	0	0
T174	0	1764	0	0
T178	0	1330	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6363886	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	70	0	0
T137	17913	1	0	0
T139	0	8	0	0
T140	0	8	0	0
T143	0	2	0	0
T144	0	4	0	0
T330	0	3	0	0
T331	0	11	0	0
T332	0	10	0	0
T333	0	6	0	0
T334	0	5	0	0
T335	445	0	0	0
T336	855	0	0	0
T337	74986	0	0	0
T338	522	0	0	0
T339	2080	0	0	0
T340	29631	0	0	0
T341	530	0	0	0
T342	431	0	0	0
T343	490	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	17885	0	0
T6	7579	197	0	0
T8	627	0	0	0
T21	0	94	0	0
T29	456	0	0	0
T32	0	32	0	0
T40	0	160	0	0
T41	0	87	0	0
T42	0	63	0	0
T56	0	99	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	257	0	0
T174	0	519	0	0
T178	0	252	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	384	0	0
T6	7579	8	0	0
T8	627	0	0	0
T21	0	1	0	0
T29	456	0	0	0
T32	0	2	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	9	0	0
T56	0	1	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	6	0	0
T174	0	14	0	0
T178	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5997997	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5999704	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	506	0	0
T6	7579	11	0	0
T8	627	0	0	0
T21	0	5	0	0
T29	456	0	0	0
T32	0	2	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	10	0	0
T56	0	5	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	6	0	0
T174	0	14	0	0
T178	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	459	0	0
T6	7579	8	0	0
T8	627	0	0	0
T21	0	3	0	0
T29	456	0	0	0
T32	0	2	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	9	0	0
T56	0	3	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	6	0	0
T174	0	14	0	0
T178	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	384	0	0
T6	7579	8	0	0
T8	627	0	0	0
T21	0	1	0	0
T29	456	0	0	0
T32	0	2	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	9	0	0
T56	0	1	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	6	0	0
T174	0	14	0	0
T178	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	384	0	0
T6	7579	8	0	0
T8	627	0	0	0
T21	0	1	0	0
T29	456	0	0	0
T32	0	2	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	9	0	0
T56	0	1	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	6	0	0
T174	0	14	0	0
T178	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	17448	0	0
T6	7579	189	0	0
T8	627	0	0	0
T21	0	93	0	0
T29	456	0	0	0
T32	0	30	0	0
T40	0	157	0	0
T41	0	83	0	0
T42	0	54	0	0
T56	0	98	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	251	0	0
T174	0	505	0	0
T178	0	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	327	0	0
T6	7579	8	0	0
T8	627	0	0	0
T29	456	0	0	0
T32	0	2	0	0
T40	0	3	0	0
T41	0	4	0	0
T42	0	9	0	0
T57	443	0	0	0
T65	522	0	0	0
T66	406	0	0	0
T67	424	0	0	0
T68	818	0	0	0
T69	615	0	0	0
T82	527	0	0	0
T88	0	6	0	0
T121	0	5	0	0
T174	0	14	0	0
T178	0	8	0	0
T251	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T11 T21 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T11 T21 T30 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T21 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T11 T21 T30 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T11 T21 T30 
129        1/1              cnt_en = 1'b0;
           Tests:       T11 T21 T30 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T11 T21 T30 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T11 T21 T30 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T11 T21 T30 
139                     
140        1/1              unique case (state_q)
           Tests:       T11 T21 T30 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T11 T21 T30 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T21 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T21 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T21 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T21 T56 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T21 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T21 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T21 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T21 T56 T120 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T21 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T21 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T21 T56 T89 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 T89 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T21 T30 
191        1/1                      state_d = StableSt;
           Tests:       T11 T21 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T21 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T21 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T21 T30 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T21 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T21 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T21 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T21,T30
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T21,T30
1	0	Covered	T11,T21,T30
1	1	Covered	T11,T21,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T30
0	1	Covered	T21,T56,T89
1	0	Covered	T21,T56,T91

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T30
0	1	Covered	T11,T21,T30
1	0	Covered	T21,T344

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T21,T30
1	-	Covered	T11,T21,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T21,T30
DetectSt	168	Covered	T11,T21,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T11,T21,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T21,T30
DebounceSt->IdleSt	163	Covered	T21,T56,T120
DetectSt->IdleSt	186	Covered	T21,T56,T89
DetectSt->StableSt	191	Covered	T11,T21,T30
IdleSt->DebounceSt	148	Covered	T11,T21,T30
StableSt->IdleSt	206	Covered	T11,T21,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T21,T30
0	1	Covered	T11,T21,T30
0	0	Covered	T1,T2,T4

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T30
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T11,T21,T30
IdleSt	0	-	-	-	-	-	-	Covered	T11,T21,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T21,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T56,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T21,T30
DetectSt	-	-	-	-	1	-	-	Covered	T21,T56,T89
DetectSt	-	-	-	-	0	1	-	Covered	T11,T21,T30
DetectSt	-	-	-	-	0	0	-	Covered	T11,T21,T30
StableSt	-	-	-	-	-	-	1	Covered	T11,T21,T30
StableSt	-	-	-	-	-	-	0	Covered	T11,T21,T30
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	3356	0	0
CntIncr_A	7014086	110365	0	0
CntNoWrap_A	7014086	6361494	0	0
DetectStDropOut_A	7014086	441	0	0
DetectedOut_A	7014086	81063	0	0
DetectedPulseOut_A	7014086	963	0	0
DisabledIdleSt_A	7014086	5898870	0	0
DisabledNoDetection_A	7014086	5901037	0	0
EnterDebounceSt_A	7014086	1697	0	0
EnterDetectSt_A	7014086	1660	0	0
EnterStableSt_A	7014086	963	0	0
PulseIsPulse_A	7014086	963	0	0
StayInStableSt	7014086	79968	0	0
gen_high_event_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	829	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	3356	0	0
T11	30017	36	0	0
T21	0	17	0	0
T30	0	54	0	0
T40	0	54	0	0
T51	1595	0	0	0
T56	0	16	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	20	0	0
T89	0	12	0	0
T90	0	14	0	0
T91	0	28	0	0
T92	0	50	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	110365	0	0
T11	30017	684	0	0
T21	0	536	0	0
T30	0	1431	0	0
T40	0	1620	0	0
T51	1595	0	0	0
T56	0	534	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	480	0	0
T89	0	439	0	0
T90	0	302	0	0
T91	0	1041	0	0
T92	0	1475	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6361494	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	441	0	0
T21	7856	1	0	0
T32	20109	0	0	0
T44	0	15	0	0
T56	0	1	0	0
T72	1746	0	0	0
T77	524	0	0	0
T89	0	6	0	0
T90	0	7	0	0
T91	0	4	0	0
T124	0	3	0	0
T138	0	11	0	0
T157	427	0	0	0
T158	403	0	0	0
T159	507	0	0	0
T160	524	0	0	0
T161	422	0	0	0
T248	834	0	0	0
T324	0	13	0	0
T329	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	81063	0	0
T11	30017	2968	0	0
T21	0	450	0	0
T30	0	1501	0	0
T40	0	3307	0	0
T51	1595	0	0	0
T56	0	391	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	161	0	0
T92	0	2443	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	2334	0	0
T199	0	728	0	0
T328	0	2129	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	963	0	0
T11	30017	18	0	0
T21	0	5	0	0
T30	0	27	0	0
T40	0	27	0	0
T51	1595	0	0	0
T56	0	5	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	10	0	0
T92	0	25	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	11	0	0
T199	0	13	0	0
T328	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5898870	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5901037	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	1697	0	0
T11	30017	18	0	0
T21	0	10	0	0
T30	0	27	0	0
T40	0	27	0	0
T51	1595	0	0	0
T56	0	9	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	10	0	0
T89	0	6	0	0
T90	0	7	0	0
T91	0	14	0	0
T92	0	25	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	1660	0	0
T11	30017	18	0	0
T21	0	7	0	0
T30	0	27	0	0
T40	0	27	0	0
T51	1595	0	0	0
T56	0	7	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	10	0	0
T89	0	6	0	0
T90	0	7	0	0
T91	0	14	0	0
T92	0	25	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	963	0	0
T11	30017	18	0	0
T21	0	5	0	0
T30	0	27	0	0
T40	0	27	0	0
T51	1595	0	0	0
T56	0	5	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	10	0	0
T92	0	25	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	11	0	0
T199	0	13	0	0
T328	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	963	0	0
T11	30017	18	0	0
T21	0	5	0	0
T30	0	27	0	0
T40	0	27	0	0
T51	1595	0	0	0
T56	0	5	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	10	0	0
T92	0	25	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	11	0	0
T199	0	13	0	0
T328	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	79968	0	0
T11	30017	2939	0	0
T21	0	445	0	0
T30	0	1473	0	0
T40	0	3274	0	0
T51	1595	0	0	0
T56	0	386	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	150	0	0
T92	0	2415	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	2317	0	0
T199	0	714	0	0
T328	0	2093	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	829	0	0
T11	30017	7	0	0
T21	0	4	0	0
T30	0	26	0	0
T40	0	21	0	0
T51	1595	0	0	0
T56	0	5	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	9	0	0
T92	0	22	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T134	0	5	0	0
T199	0	12	0	0
T328	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T6 T11 T21 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T4 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T2 T4 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T2 T4 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T2 T4 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T21 T32 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
105        1/1                cnt_q <= '0;
           Tests:       T1 T2 T4 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T2 T4 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T2 T4 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T2 T4 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T2 T4 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T2 T4 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T2 T4 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T2 T4 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T2 T4 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T2 T4 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T21 T32 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T21 T32 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T32 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T21 T32 
163        1/1                    state_d = IdleSt;
           Tests:       T21 T56 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T21 T32 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T32 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T21 T32 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T21 T32 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T121 T43 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T21 T32 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T32 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T21 T32 
186        1/1                    state_d = IdleSt;
           Tests:       T21 T56 T43 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T21 T56 T43 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T21 T32 
191        1/1                      state_d = StableSt;
           Tests:       T11 T21 T32 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T21 T32 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T21 T32 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T21 T32 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T21 T32 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T21 T32 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T21 T32 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T4 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T2 T4 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T2 T4 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T11,T21
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T21
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T11,T21,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T21,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T21
1	0	Covered	T28,T11,T51
1	1	Covered	T11,T21,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T32
0	1	Covered	T56,T43,T345
1	0	Covered	T21,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T32
0	1	Covered	T11,T21,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T21,T32
1	-	Covered	T11,T21,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T21,T32
DetectSt	168	Covered	T11,T21,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T11,T21,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T21,T32
DebounceSt->IdleSt	163	Covered	T11,T21,T56
DetectSt->IdleSt	186	Covered	T21,T56,T43
DetectSt->StableSt	191	Covered	T11,T21,T32
IdleSt->DebounceSt	148	Covered	T11,T21,T32
StableSt->IdleSt	206	Covered	T11,T21,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T21,T32
0	1	Covered	T11,T21,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T32
0	Covered	T1,T2,T4

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T21,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T21,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T21,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T121,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T21,T32
DetectSt	-	-	-	-	1	-	-	Covered	T21,T56,T43
DetectSt	-	-	-	-	0	1	-	Covered	T11,T21,T32
DetectSt	-	-	-	-	0	0	-	Covered	T11,T21,T32
StableSt	-	-	-	-	-	-	1	Covered	T11,T21,T32
StableSt	-	-	-	-	-	-	0	Covered	T11,T21,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7014086	935	0	0
CntIncr_A	7014086	50345	0	0
CntNoWrap_A	7014086	6363915	0	0
DetectStDropOut_A	7014086	78	0	0
DetectedOut_A	7014086	19556	0	0
DetectedPulseOut_A	7014086	368	0	0
DisabledIdleSt_A	7014086	5990414	0	0
DisabledNoDetection_A	7014086	5992126	0	0
EnterDebounceSt_A	7014086	486	0	0
EnterDetectSt_A	7014086	449	0	0
EnterStableSt_A	7014086	368	0	0
PulseIsPulse_A	7014086	368	0	0
StayInStableSt	7014086	19143	0	0
gen_high_level_sva.HighLevelEvent_A	7014086	6367248	0	0
gen_not_sticky_sva.StableStDropOut_A	7014086	323	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	935	0	0
T11	30017	23	0	0
T21	0	8	0	0
T30	0	2	0	0
T32	0	8	0	0
T40	0	2	0	0
T41	0	12	0	0
T42	0	6	0	0
T51	1595	0	0	0
T56	0	8	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	2	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	50345	0	0
T11	30017	673	0	0
T21	0	284	0	0
T30	0	66	0	0
T32	0	312	0	0
T40	0	70	0	0
T41	0	720	0	0
T42	0	180	0	0
T51	1595	0	0	0
T56	0	221	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	54	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	935	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6363915	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	78	0	0
T41	33129	0	0	0
T43	0	7	0	0
T54	8961	0	0	0
T56	7997	1	0	0
T73	148631	0	0	0
T80	497	0	0	0
T88	19114	0	0	0
T140	0	5	0	0
T142	0	1	0	0
T152	4402	0	0	0
T153	403	0	0	0
T154	424	0	0	0
T155	525	0	0	0
T333	0	6	0	0
T345	0	3	0	0
T346	0	5	0	0
T347	0	6	0	0
T348	0	9	0	0
T349	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	19556	0	0
T11	30017	674	0	0
T21	0	92	0	0
T30	0	55	0	0
T32	0	281	0	0
T40	0	79	0	0
T41	0	350	0	0
T42	0	54	0	0
T51	1595	0	0	0
T56	0	99	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	52	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	858	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	368	0	0
T11	30017	11	0	0
T21	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T40	0	1	0	0
T41	0	6	0	0
T42	0	3	0	0
T51	1595	0	0	0
T56	0	1	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	1	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5990414	0	0
T1	509	108	0	0
T2	486	85	0	0
T3	481	80	0	0
T4	666	265	0	0
T12	747	346	0	0
T13	523	122	0	0
T14	412	11	0	0
T15	423	22	0	0
T16	1038	637	0	0
T17	426	25	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	5992126	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	486	0	0
T11	30017	12	0	0
T21	0	5	0	0
T30	0	1	0	0
T32	0	4	0	0
T40	0	1	0	0
T41	0	6	0	0
T42	0	3	0	0
T51	1595	0	0	0
T56	0	5	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	1	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	449	0	0
T11	30017	11	0	0
T21	0	3	0	0
T30	0	1	0	0
T32	0	4	0	0
T40	0	1	0	0
T41	0	6	0	0
T42	0	3	0	0
T51	1595	0	0	0
T56	0	3	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	1	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	368	0	0
T11	30017	11	0	0
T21	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T40	0	1	0	0
T41	0	6	0	0
T42	0	3	0	0
T51	1595	0	0	0
T56	0	1	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	1	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	368	0	0
T11	30017	11	0	0
T21	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T40	0	1	0	0
T41	0	6	0	0
T42	0	3	0	0
T51	1595	0	0	0
T56	0	1	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	1	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	19143	0	0
T11	30017	663	0	0
T21	0	91	0	0
T30	0	54	0	0
T32	0	277	0	0
T40	0	77	0	0
T41	0	344	0	0
T42	0	51	0	0
T51	1595	0	0	0
T56	0	98	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	51	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	847	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	6367248	0	0
T1	509	109	0	0
T2	486	86	0	0
T3	481	81	0	0
T4	666	266	0	0
T12	747	347	0	0
T13	523	123	0	0
T14	412	12	0	0
T15	423	23	0	0
T16	1038	638	0	0
T17	426	26	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7014086	323	0	0
T11	30017	11	0	0
T21	0	1	0	0
T30	0	1	0	0
T32	0	4	0	0
T41	0	6	0	0
T42	0	3	0	0
T51	1595	0	0	0
T56	0	1	0	0
T58	692	0	0	0
T59	509	0	0	0
T60	773	0	0	0
T75	492	0	0	0
T84	507	0	0	0
T88	0	1	0	0
T93	425	0	0	0
T94	8443	0	0	0
T95	448	0	0	0
T174	0	11	0	0
T178	0	1	0	0