Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T12 T20 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T12 T20 T30 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T8 T29 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T8 T29 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T8 T29 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T8 T29 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T8 T29 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T8 T29 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T8 T29 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T8 T29 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T8 T29 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T8 T29 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T8 T29 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T29 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T8 T29 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T8 T29 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T8 T29 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T8 T29 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T8 T29 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T12 T55 T102 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T8 T29 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T29 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T8 T29 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T20 T30 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T20 T30 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T8 T29 
191        1/1                      state_d = StableSt;
           Tests:       T1 T8 T29 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T8 T29 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T8 T29 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T8 T29 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T8 T29 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T42 T55 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T8 T29 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T20,T30
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T30
1	0	Covered	T12,T20,T42
1	1	Covered	T1,T8,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T29
0	1	Covered	T12,T20,T30
1	0	Covered	T12,T20,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T29
0	1	Covered	T12,T42,T55
1	0	Covered	T12

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T29
1	-	Covered	T12,T42,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T29
DetectSt	168	Covered	T1,T8,T29
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T29
DebounceSt->IdleSt	163	Covered	T12,T55,T102
DetectSt->IdleSt	186	Covered	T12,T20,T30
DetectSt->StableSt	191	Covered	T1,T8,T29
IdleSt->DebounceSt	148	Covered	T1,T8,T29
StableSt->IdleSt	206	Covered	T12,T42,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T29
0	1	Covered	T1,T8,T29
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T29
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T29
IdleSt	0	-	-	-	-	-	-	Covered	T12,T20,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T12,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T55,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T29
DetectSt	-	-	-	-	1	-	-	Covered	T12,T20,T30
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T29
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T29
StableSt	-	-	-	-	-	-	1	Covered	T12,T42,T55
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	3021	0	0
CntIncr_A	7365022	98505	0	0
CntNoWrap_A	7365022	6890623	0	0
DetectStDropOut_A	7365022	331	0	0
DetectedOut_A	7365022	66452	0	0
DetectedPulseOut_A	7365022	876	0	0
DisabledIdleSt_A	7365022	6475910	0	0
DisabledNoDetection_A	7365022	6477591	0	0
EnterDebounceSt_A	7365022	1529	0	0
EnterDetectSt_A	7365022	1492	0	0
EnterStableSt_A	7365022	876	0	0
PulseIsPulse_A	7365022	876	0	0
StayInStableSt	7365022	65488	0	0
gen_high_event_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	787	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	3021	0	0
T1	505	2	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	2	0	0
T12	0	16	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T20	0	52	0	0
T29	0	2	0	0
T30	0	24	0	0
T31	0	16	0	0
T42	0	10	0	0
T56	0	2	0	0
T91	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	98505	0	0
T1	505	21	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	21	0	0
T12	0	436	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T20	0	1234	0	0
T29	0	21	0	0
T30	0	605	0	0
T31	0	453	0	0
T42	0	340	0	0
T56	0	21	0	0
T91	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6890623	0	0
T1	505	102	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	331	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	4	0	0
T30	0	12	0	0
T31	0	8	0	0
T38	454044	0	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T93	0	12	0	0
T94	0	9	0	0
T102	0	20	0	0
T221	0	7	0	0
T222	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	66452	0	0
T1	505	80	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	81	0	0
T12	0	379	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	45	0	0
T42	0	268	0	0
T55	0	351	0	0
T56	0	28	0	0
T91	0	35	0	0
T92	0	1187	0	0
T95	0	349	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	876	0	0
T1	505	1	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T12	0	5	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	1	0	0
T42	0	5	0	0
T55	0	5	0	0
T56	0	1	0	0
T91	0	1	0	0
T92	0	18	0	0
T95	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6475910	0	0
T1	505	3	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6477591	0	0
T1	505	3	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1529	0	0
T1	505	1	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T12	0	9	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T20	0	26	0	0
T29	0	1	0	0
T30	0	12	0	0
T31	0	8	0	0
T42	0	5	0	0
T56	0	1	0	0
T91	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1492	0	0
T1	505	1	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T12	0	7	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T20	0	26	0	0
T29	0	1	0	0
T30	0	12	0	0
T31	0	8	0	0
T42	0	5	0	0
T56	0	1	0	0
T91	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	876	0	0
T1	505	1	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T12	0	5	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	1	0	0
T42	0	5	0	0
T55	0	5	0	0
T56	0	1	0	0
T91	0	1	0	0
T92	0	18	0	0
T95	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	876	0	0
T1	505	1	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T12	0	5	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	1	0	0
T42	0	5	0	0
T55	0	5	0	0
T56	0	1	0	0
T91	0	1	0	0
T92	0	18	0	0
T95	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	65488	0	0
T1	505	78	0	0
T2	483	0	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	79	0	0
T12	0	374	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	43	0	0
T42	0	263	0	0
T55	0	346	0	0
T56	0	26	0	0
T91	0	33	0	0
T92	0	1169	0	0
T95	0	337	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	787	0	0
T12	7268	4	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T41	0	22	0	0
T42	0	5	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	18	0	0
T95	0	12	0	0
T129	0	13	0	0
T223	0	22	0	0
T224	0	8	0	0
T225	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T2 T8 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T2 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T2 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T2 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T2 T8 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T2 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T8 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T2 T8 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T2 T8 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T29 T56 T57 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T2 T8 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T8 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T2 T8 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T55 T111 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 T111 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T2 T8 
191        1/1                      state_d = StableSt;
           Tests:       T1 T2 T8 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T2 T8 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T2 T8 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T2 T8 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T2 T8 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T8 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T2 T8 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T17,T87,T103
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T111,T112,T113
1	0	Covered	T12,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T226

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T29,T56,T12
DetectSt->IdleSt	186	Covered	T12,T55,T111
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T12,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T56,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T12,T55,T111
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	818	0	0
CntIncr_A	7365022	42622	0	0
CntNoWrap_A	7365022	6892826	0	0
DetectStDropOut_A	7365022	46	0	0
DetectedOut_A	7365022	14336	0	0
DetectedPulseOut_A	7365022	336	0	0
DisabledIdleSt_A	7365022	6544257	0	0
DisabledNoDetection_A	7365022	6545454	0	0
EnterDebounceSt_A	7365022	432	0	0
EnterDetectSt_A	7365022	386	0	0
EnterStableSt_A	7365022	336	0	0
PulseIsPulse_A	7365022	336	0	0
StayInStableSt	7365022	13966	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	818	0	0
T1	505	2	0	0
T2	483	2	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	8	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T109	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	42622	0	0
T1	505	25	0	0
T2	483	25	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	25	0	0
T9	0	25	0	0
T10	0	25	0	0
T12	0	221	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	20	0	0
T56	0	20	0	0
T57	0	20	0	0
T109	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6892826	0	0
T1	505	102	0	0
T2	483	80	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	46	0	0
T111	14718	3	0	0
T112	0	4	0	0
T113	0	3	0	0
T114	0	5	0	0
T115	0	7	0	0
T116	0	2	0	0
T117	0	5	0	0
T118	0	4	0	0
T119	0	3	0	0
T120	0	10	0	0
T129	13390	0	0	0
T130	425	0	0	0
T131	507	0	0	0
T132	3178	0	0	0
T133	31189	0	0	0
T134	490	0	0	0
T135	39063	0	0	0
T136	1871	0	0	0
T137	413	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	14336	0	0
T1	505	3	0	0
T2	483	3	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	3	0	0
T9	0	3	0	0
T10	0	3	0	0
T12	0	88	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T40	0	11	0	0
T55	0	112	0	0
T92	0	172	0	0
T109	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	336	0	0
T1	505	1	0	0
T2	483	1	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T40	0	1	0	0
T55	0	1	0	0
T92	0	2	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6544257	0	0
T1	505	25	0	0
T2	483	4	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6545454	0	0
T1	505	25	0	0
T2	483	4	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	432	0	0
T1	505	1	0	0
T2	483	1	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	5	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T29	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	386	0	0
T1	505	1	0	0
T2	483	1	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	3	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T40	0	1	0	0
T55	0	3	0	0
T92	0	2	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	336	0	0
T1	505	1	0	0
T2	483	1	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T40	0	1	0	0
T55	0	1	0	0
T92	0	2	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	336	0	0
T1	505	1	0	0
T2	483	1	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T40	0	1	0	0
T55	0	1	0	0
T92	0	2	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	13966	0	0
T1	505	2	0	0
T2	483	2	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	87	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T40	0	10	0	0
T55	0	111	0	0
T92	0	170	0	0
T109	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	299	0	0
T1	505	1	0	0
T2	483	1	0	0
T4	447	0	0	0
T5	496	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	523	0	0	0
T15	708	0	0	0
T16	674	0	0	0
T17	1522	0	0	0
T18	497	0	0	0
T40	0	1	0	0
T43	0	10	0	0
T92	0	2	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T12 T20 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T12 T20 T30 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T12 T20 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T12 T20 T30 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T12 T20 T30 
129        1/1              cnt_en = 1'b0;
           Tests:       T12 T20 T30 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T12 T20 T30 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T12 T20 T30 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T12 T20 T30 
139                     
140        1/1              unique case (state_q)
           Tests:       T12 T20 T30 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T12 T20 T30 
148        1/1                    state_d = DebounceSt;
           Tests:       T12 T20 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T12 T20 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T12 T20 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T12 T20 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T12 T20 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T20 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T12 T20 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T20 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T12 T55 T102 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T20 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T20 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T20 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T30 T31 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T30 T31 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T20 T30 
191        1/1                      state_d = StableSt;
           Tests:       T12 T20 T42 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T20 T42 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T20 T42 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T20 T42 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T20 T42 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T20 T42 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T20 T42 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T20,T30
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T30
1	0	Covered	T12,T20,T42
1	1	Covered	T12,T20,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T30
0	1	Covered	T12,T30,T31
1	0	Covered	T12,T55,T227

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T42
0	1	Covered	T12,T20,T42
1	0	Covered	T12,T55,T228

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T20,T42
1	-	Covered	T12,T20,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T20,T30
DetectSt	168	Covered	T12,T20,T30
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T20,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T20,T30
DebounceSt->IdleSt	163	Covered	T12,T55,T102
DetectSt->IdleSt	186	Covered	T12,T30,T31
DetectSt->StableSt	191	Covered	T12,T20,T42
IdleSt->DebounceSt	148	Covered	T12,T20,T30
StableSt->IdleSt	206	Covered	T12,T20,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T20,T30
0	1	Covered	T12,T20,T30
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T20,T30
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T20,T30
IdleSt	0	-	-	-	-	-	-	Covered	T12,T20,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T12,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T20,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T55,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T20,T30
DetectSt	-	-	-	-	1	-	-	Covered	T12,T30,T31
DetectSt	-	-	-	-	0	1	-	Covered	T12,T20,T42
DetectSt	-	-	-	-	0	0	-	Covered	T12,T20,T30
StableSt	-	-	-	-	-	-	1	Covered	T12,T20,T42
StableSt	-	-	-	-	-	-	0	Covered	T12,T20,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	3088	0	0
CntIncr_A	7365022	100245	0	0
CntNoWrap_A	7365022	6890556	0	0
DetectStDropOut_A	7365022	330	0	0
DetectedOut_A	7365022	66890	0	0
DetectedPulseOut_A	7365022	957	0	0
DisabledIdleSt_A	7365022	6476093	0	0
DisabledNoDetection_A	7365022	6477771	0	0
EnterDebounceSt_A	7365022	1561	0	0
EnterDetectSt_A	7365022	1527	0	0
EnterStableSt_A	7365022	957	0	0
PulseIsPulse_A	7365022	957	0	0
StayInStableSt	7365022	65842	0	0
gen_high_event_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	852	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	3088	0	0
T12	7268	16	0	0
T19	1687	0	0	0
T20	8546	28	0	0
T30	0	26	0	0
T31	0	56	0	0
T38	454044	0	0	0
T42	0	10	0	0
T55	0	16	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	12	0	0
T93	0	10	0	0
T94	0	28	0	0
T95	0	60	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	100245	0	0
T12	7268	394	0	0
T19	1687	0	0	0
T20	8546	546	0	0
T30	0	656	0	0
T31	0	1602	0	0
T38	454044	0	0	0
T42	0	330	0	0
T55	0	419	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	366	0	0
T93	0	266	0	0
T94	0	719	0	0
T95	0	900	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6890556	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	330	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T30	0	13	0	0
T31	0	28	0	0
T38	454044	0	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T93	0	5	0	0
T94	0	14	0	0
T102	0	3	0	0
T229	0	24	0	0
T230	0	15	0	0
T231	0	31	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	66890	0	0
T12	7268	387	0	0
T19	1687	0	0	0
T20	8546	281	0	0
T38	454044	0	0	0
T41	0	1025	0	0
T42	0	278	0	0
T55	0	363	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	389	0	0
T95	0	884	0	0
T223	0	744	0	0
T232	0	1308	0	0
T233	0	2398	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	957	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	14	0	0
T38	454044	0	0	0
T41	0	14	0	0
T42	0	5	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	6	0	0
T95	0	30	0	0
T223	0	22	0	0
T232	0	28	0	0
T233	0	19	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6476093	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6477771	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1561	0	0
T12	7268	9	0	0
T19	1687	0	0	0
T20	8546	14	0	0
T30	0	13	0	0
T31	0	28	0	0
T38	454044	0	0	0
T42	0	5	0	0
T55	0	9	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	6	0	0
T93	0	5	0	0
T94	0	14	0	0
T95	0	30	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1527	0	0
T12	7268	7	0	0
T19	1687	0	0	0
T20	8546	14	0	0
T30	0	13	0	0
T31	0	28	0	0
T38	454044	0	0	0
T42	0	5	0	0
T55	0	7	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	6	0	0
T93	0	5	0	0
T94	0	14	0	0
T95	0	30	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	957	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	14	0	0
T38	454044	0	0	0
T41	0	14	0	0
T42	0	5	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	6	0	0
T95	0	30	0	0
T223	0	22	0	0
T232	0	28	0	0
T233	0	19	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	957	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	14	0	0
T38	454044	0	0	0
T41	0	14	0	0
T42	0	5	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	6	0	0
T95	0	30	0	0
T223	0	22	0	0
T232	0	28	0	0
T233	0	19	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	65842	0	0
T12	7268	382	0	0
T19	1687	0	0	0
T20	8546	266	0	0
T38	454044	0	0	0
T41	0	1009	0	0
T42	0	273	0	0
T55	0	358	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	383	0	0
T95	0	854	0	0
T223	0	722	0	0
T232	0	1280	0	0
T233	0	2373	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	852	0	0
T12	7268	4	0	0
T19	1687	0	0	0
T20	8546	13	0	0
T38	454044	0	0	0
T41	0	12	0	0
T42	0	5	0	0
T55	0	4	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	6	0	0
T95	0	30	0	0
T223	0	22	0	0
T232	0	28	0	0
T233	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T12 T20 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T12 T20 T32 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T12 T20 T32 
149        1/1                    cnt_en = 1'b1;
           Tests:       T12 T20 T32 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T12 T20 T32 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T12 T20 T32 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T12 T20 T32 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T20 T32 
167        1/1                    if (trigger_active) begin
           Tests:       T12 T20 T32 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T20 T32 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T39 T234 T129 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T20 T32 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T20 T32 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T20 T32 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T55 T40 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 T40 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T20 T32 
191        1/1                      state_d = StableSt;
           Tests:       T12 T20 T32 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T20 T32 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T20 T32 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T20 T32 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T20 T32 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T20 T32 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T20 T32 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T20,T30
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T30
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T32
1	0	Covered	T17,T87,T103
1	1	Covered	T12,T20,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T32
0	1	Covered	T40,T104,T234
1	0	Covered	T12,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T32
0	1	Covered	T12,T20,T32
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T20,T32
1	-	Covered	T12,T20,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T20,T32
DetectSt	168	Covered	T12,T20,T32
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T20,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T20,T32
DebounceSt->IdleSt	163	Covered	T12,T55,T39
DetectSt->IdleSt	186	Covered	T12,T55,T40
DetectSt->StableSt	191	Covered	T12,T20,T32
IdleSt->DebounceSt	148	Covered	T12,T20,T32
StableSt->IdleSt	206	Covered	T12,T20,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T20,T32
0	1	Covered	T12,T20,T32
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T20,T32
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T20,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T12,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T20,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T234,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T20,T32
DetectSt	-	-	-	-	1	-	-	Covered	T12,T55,T40
DetectSt	-	-	-	-	0	1	-	Covered	T12,T20,T32
DetectSt	-	-	-	-	0	0	-	Covered	T12,T20,T32
StableSt	-	-	-	-	-	-	1	Covered	T12,T20,T32
StableSt	-	-	-	-	-	-	0	Covered	T12,T20,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	657	0	0
CntIncr_A	7365022	34120	0	0
CntNoWrap_A	7365022	6892987	0	0
DetectStDropOut_A	7365022	46	0	0
DetectedOut_A	7365022	13825	0	0
DetectedPulseOut_A	7365022	260	0	0
DisabledIdleSt_A	7365022	6537523	0	0
DisabledNoDetection_A	7365022	6538717	0	0
EnterDebounceSt_A	7365022	347	0	0
EnterDetectSt_A	7365022	310	0	0
EnterStableSt_A	7365022	260	0	0
PulseIsPulse_A	7365022	260	0	0
StayInStableSt	7365022	13545	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	239	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	657	0	0
T12	7268	8	0	0
T19	1687	0	0	0
T20	8546	2	0	0
T32	0	6	0	0
T38	454044	0	0	0
T39	0	22	0	0
T40	0	2	0	0
T41	0	2	0	0
T44	0	4	0	0
T55	0	8	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T104	0	2	0	0
T235	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	34120	0	0
T12	7268	230	0	0
T19	1687	0	0	0
T20	8546	77	0	0
T32	0	501	0	0
T38	454044	0	0	0
T39	0	1150	0	0
T40	0	179	0	0
T41	0	47	0	0
T44	0	146	0	0
T55	0	185	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T104	0	120	0	0
T235	0	1300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6892987	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	46	0	0
T40	9212	1	0	0
T104	0	1	0	0
T114	0	8	0	0
T210	647	0	0	0
T234	0	2	0	0
T236	0	3	0	0
T237	0	7	0	0
T238	0	3	0	0
T239	0	2	0	0
T240	0	1	0	0
T241	0	2	0	0
T242	1579	0	0	0
T243	743	0	0	0
T244	418	0	0	0
T245	1657	0	0	0
T246	493	0	0	0
T247	558	0	0	0
T248	426	0	0	0
T249	2980	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	13825	0	0
T12	7268	88	0	0
T19	1687	0	0	0
T20	8546	50	0	0
T32	0	14	0	0
T38	454044	0	0	0
T39	0	226	0	0
T41	0	90	0	0
T44	0	106	0	0
T55	0	113	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T232	0	65	0	0
T233	0	439	0	0
T235	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	260	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	1	0	0
T32	0	3	0	0
T38	454044	0	0	0
T39	0	10	0	0
T41	0	1	0	0
T44	0	2	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T232	0	1	0	0
T233	0	6	0	0
T235	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6537523	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6538717	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	347	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	1	0	0
T32	0	3	0	0
T38	454044	0	0	0
T39	0	12	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T104	0	1	0	0
T235	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	310	0	0
T12	7268	3	0	0
T19	1687	0	0	0
T20	8546	1	0	0
T32	0	3	0	0
T38	454044	0	0	0
T39	0	10	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T55	0	3	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T104	0	1	0	0
T235	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	260	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	1	0	0
T32	0	3	0	0
T38	454044	0	0	0
T39	0	10	0	0
T41	0	1	0	0
T44	0	2	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T232	0	1	0	0
T233	0	6	0	0
T235	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	260	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	1	0	0
T32	0	3	0	0
T38	454044	0	0	0
T39	0	10	0	0
T41	0	1	0	0
T44	0	2	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T232	0	1	0	0
T233	0	6	0	0
T235	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	13545	0	0
T12	7268	87	0	0
T19	1687	0	0	0
T20	8546	49	0	0
T32	0	11	0	0
T38	454044	0	0	0
T39	0	216	0	0
T41	0	88	0	0
T44	0	104	0	0
T55	0	112	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T232	0	64	0	0
T233	0	433	0	0
T235	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	239	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	1	0	0
T32	0	3	0	0
T38	454044	0	0	0
T39	0	10	0	0
T44	0	2	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T133	0	3	0	0
T221	0	2	0	0
T232	0	1	0	0
T233	0	6	0	0
T235	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T12 T20 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T12 T20 T30 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T12 T20 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T12 T20 T30 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T12 T20 T30 
129        1/1              cnt_en = 1'b0;
           Tests:       T12 T20 T30 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T12 T20 T30 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T12 T20 T30 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T12 T20 T30 
139                     
140        1/1              unique case (state_q)
           Tests:       T12 T20 T30 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T12 T20 T30 
148        1/1                    state_d = DebounceSt;
           Tests:       T12 T20 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T12 T20 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T12 T20 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T12 T20 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T12 T20 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T20 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T12 T20 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T20 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T12 T55 T102 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T20 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T20 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T20 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T20 T30 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T20 T30 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T20 T31 
191        1/1                      state_d = StableSt;
           Tests:       T12 T42 T55 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T42 T55 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T42 T55 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T42 T55 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T42 T55 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T42 T55 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T42 T55 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T20,T30
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T20,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T30
1	0	Covered	T12,T20,T42
1	1	Covered	T12,T20,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T31
0	1	Covered	T12,T30,T31
1	0	Covered	T12,T20,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T42,T55
0	1	Covered	T12,T42,T55
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T42,T55
1	-	Covered	T12,T42,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T20,T30
DetectSt	168	Covered	T12,T20,T30
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T42,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T20,T30
DebounceSt->IdleSt	163	Covered	T12,T55,T102
DetectSt->IdleSt	186	Covered	T12,T20,T30
DetectSt->StableSt	191	Covered	T12,T42,T55
IdleSt->DebounceSt	148	Covered	T12,T20,T30
StableSt->IdleSt	206	Covered	T12,T42,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T20,T30
0	1	Covered	T12,T20,T30
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T20,T30
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T20,T30
IdleSt	0	-	-	-	-	-	-	Covered	T12,T20,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T12,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T20,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T55,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T20,T30
DetectSt	-	-	-	-	1	-	-	Covered	T12,T20,T30
DetectSt	-	-	-	-	0	1	-	Covered	T12,T42,T55
DetectSt	-	-	-	-	0	0	-	Covered	T12,T20,T31
StableSt	-	-	-	-	-	-	1	Covered	T12,T42,T55
StableSt	-	-	-	-	-	-	0	Covered	T12,T42,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	3353	0	0
CntIncr_A	7365022	105600	0	0
CntNoWrap_A	7365022	6890291	0	0
DetectStDropOut_A	7365022	384	0	0
DetectedOut_A	7365022	77192	0	0
DetectedPulseOut_A	7365022	1031	0	0
DisabledIdleSt_A	7365022	6470796	0	0
DisabledNoDetection_A	7365022	6472475	0	0
EnterDebounceSt_A	7365022	1693	0	0
EnterDetectSt_A	7365022	1660	0	0
EnterStableSt_A	7365022	1031	0	0
PulseIsPulse_A	7365022	1031	0	0
StayInStableSt	7365022	76071	0	0
gen_high_event_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	940	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	3353	0	0
T12	7268	16	0	0
T19	1687	0	0	0
T20	8546	52	0	0
T30	0	12	0	0
T31	0	32	0	0
T38	454044	0	0	0
T42	0	42	0	0
T55	0	16	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	22	0	0
T93	0	18	0	0
T94	0	42	0	0
T95	0	64	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	105600	0	0
T12	7268	499	0	0
T19	1687	0	0	0
T20	8546	1245	0	0
T30	0	300	0	0
T31	0	904	0	0
T38	454044	0	0	0
T42	0	1260	0	0
T55	0	566	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	825	0	0
T93	0	481	0	0
T94	0	1095	0	0
T95	0	1280	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6890291	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	384	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T30	0	6	0	0
T31	0	16	0	0
T38	454044	0	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T93	0	9	0	0
T94	0	21	0	0
T102	0	10	0	0
T129	0	2	0	0
T233	0	18	0	0
T250	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	77192	0	0
T12	7268	376	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T41	0	1832	0	0
T42	0	1418	0	0
T55	0	328	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	865	0	0
T95	0	1837	0	0
T221	0	1432	0	0
T223	0	473	0	0
T224	0	2027	0	0
T232	0	1177	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1031	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T41	0	18	0	0
T42	0	21	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	11	0	0
T95	0	32	0	0
T221	0	19	0	0
T223	0	15	0	0
T224	0	22	0	0
T232	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6470796	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6472475	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1693	0	0
T12	7268	9	0	0
T19	1687	0	0	0
T20	8546	26	0	0
T30	0	6	0	0
T31	0	16	0	0
T38	454044	0	0	0
T42	0	21	0	0
T55	0	9	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	11	0	0
T93	0	9	0	0
T94	0	21	0	0
T95	0	32	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1660	0	0
T12	7268	7	0	0
T19	1687	0	0	0
T20	8546	26	0	0
T30	0	6	0	0
T31	0	16	0	0
T38	454044	0	0	0
T42	0	21	0	0
T55	0	7	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	11	0	0
T93	0	9	0	0
T94	0	21	0	0
T95	0	32	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1031	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T41	0	18	0	0
T42	0	21	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	11	0	0
T95	0	32	0	0
T221	0	19	0	0
T223	0	15	0	0
T224	0	22	0	0
T232	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	1031	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T41	0	18	0	0
T42	0	21	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	11	0	0
T95	0	32	0	0
T221	0	19	0	0
T223	0	15	0	0
T224	0	22	0	0
T232	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	76071	0	0
T12	7268	371	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T41	0	1812	0	0
T42	0	1396	0	0
T55	0	323	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	854	0	0
T95	0	1805	0	0
T221	0	1413	0	0
T223	0	458	0	0
T224	0	2002	0	0
T232	0	1152	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	940	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T38	454044	0	0	0
T41	0	16	0	0
T42	0	20	0	0
T55	0	4	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	11	0	0
T95	0	32	0	0
T221	0	19	0	0
T223	0	15	0	0
T224	0	19	0	0
T232	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T12 T20 T30 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T12 T32 T42 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T12 T32 T55 
149        1/1                    cnt_en = 1'b1;
           Tests:       T12 T32 T55 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T12 T32 T55 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T12 T32 T55 
163        1/1                    state_d = IdleSt;
           Tests:       T12 T55 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 
165        1/1                  end else if (cnt_done) begin
           Tests:       T12 T32 T55 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T32 T55 
167        1/1                    if (trigger_active) begin
           Tests:       T12 T32 T55 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T32 T55 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T43 T39 T95 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T32 T55 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T32 T55 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T32 T55 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T55 T43 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 T43 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T32 T55 
191        1/1                      state_d = StableSt;
           Tests:       T12 T32 T55 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T32 T55 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T32 T55 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T32 T55 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T32 T55 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T32 T55 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T32 T55 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T20,T30
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T30
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T32,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T32,T55

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T32,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T32,T42
1	0	Covered	T17,T87,T103
1	1	Covered	T12,T32,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T32,T55
0	1	Covered	T43,T251,T252
1	0	Covered	T12,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T32,T55
0	1	Covered	T32,T92,T40
1	0	Covered	T12,T55,T253

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T32,T55
1	-	Covered	T32,T92,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T32,T55
DetectSt	168	Covered	T12,T32,T55
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T32,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T32,T55
DebounceSt->IdleSt	163	Covered	T12,T55,T43
DetectSt->IdleSt	186	Covered	T12,T55,T43
DetectSt->StableSt	191	Covered	T12,T32,T55
IdleSt->DebounceSt	148	Covered	T12,T32,T55
StableSt->IdleSt	206	Covered	T12,T32,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T32,T55
0	1	Covered	T12,T32,T55
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T32,T55
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T32,T55
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T12,T55
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T32,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T39,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T32,T55
DetectSt	-	-	-	-	1	-	-	Covered	T12,T55,T43
DetectSt	-	-	-	-	0	1	-	Covered	T12,T32,T55
DetectSt	-	-	-	-	0	0	-	Covered	T12,T32,T55
StableSt	-	-	-	-	-	-	1	Covered	T12,T32,T55
StableSt	-	-	-	-	-	-	0	Covered	T12,T32,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7365022	830	0	0
CntIncr_A	7365022	43150	0	0
CntNoWrap_A	7365022	6892814	0	0
DetectStDropOut_A	7365022	60	0	0
DetectedOut_A	7365022	15087	0	0
DetectedPulseOut_A	7365022	331	0	0
DisabledIdleSt_A	7365022	6541050	0	0
DisabledNoDetection_A	7365022	6542273	0	0
EnterDebounceSt_A	7365022	435	0	0
EnterDetectSt_A	7365022	396	0	0
EnterStableSt_A	7365022	331	0	0
PulseIsPulse_A	7365022	331	0	0
StayInStableSt	7365022	14716	0	0
gen_high_level_sva.HighLevelEvent_A	7365022	6895503	0	0
gen_not_sticky_sva.StableStDropOut_A	7365022	285	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	830	0	0
T12	7268	8	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	8	0	0
T38	454044	0	0	0
T39	0	22	0	0
T40	0	4	0	0
T41	0	4	0	0
T43	0	16	0	0
T55	0	8	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	4	0	0
T95	0	9	0	0
T235	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	43150	0	0
T12	7268	221	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	576	0	0
T38	454044	0	0	0
T39	0	980	0	0
T40	0	238	0	0
T41	0	100	0	0
T43	0	566	0	0
T55	0	148	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	182	0	0
T95	0	415	0	0
T235	0	354	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6892814	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	60	0	0
T43	31488	7	0	0
T93	5318	0	0	0
T96	622	0	0	0
T114	0	5	0	0
T115	0	14	0	0
T121	1467	0	0	0
T122	493	0	0	0
T123	522	0	0	0
T124	628	0	0	0
T125	8402	0	0	0
T126	412	0	0	0
T251	0	1	0	0
T252	0	4	0	0
T254	0	5	0	0
T255	0	5	0	0
T256	0	2	0	0
T257	0	5	0	0
T258	0	4	0	0
T259	655	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	15087	0	0
T12	7268	88	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	108	0	0
T38	454044	0	0	0
T39	0	396	0	0
T40	0	121	0	0
T41	0	177	0	0
T44	0	362	0	0
T55	0	112	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	244	0	0
T95	0	216	0	0
T235	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	331	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	4	0	0
T38	454044	0	0	0
T39	0	10	0	0
T40	0	2	0	0
T41	0	2	0	0
T44	0	6	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	2	0	0
T95	0	4	0	0
T235	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6541050	0	0
T1	505	104	0	0
T2	483	82	0	0
T4	447	46	0	0
T5	496	95	0	0
T13	422	21	0	0
T14	523	122	0	0
T15	708	307	0	0
T16	674	273	0	0
T17	1522	41	0	0
T18	497	96	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6542273	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	435	0	0
T12	7268	5	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	4	0	0
T38	454044	0	0	0
T39	0	12	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	9	0	0
T55	0	5	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	2	0	0
T95	0	5	0	0
T235	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	396	0	0
T12	7268	3	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	4	0	0
T38	454044	0	0	0
T39	0	10	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	7	0	0
T55	0	3	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	2	0	0
T95	0	4	0	0
T235	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	331	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	4	0	0
T38	454044	0	0	0
T39	0	10	0	0
T40	0	2	0	0
T41	0	2	0	0
T44	0	6	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	2	0	0
T95	0	4	0	0
T235	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	331	0	0
T12	7268	1	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	4	0	0
T38	454044	0	0	0
T39	0	10	0	0
T40	0	2	0	0
T41	0	2	0	0
T44	0	6	0	0
T55	0	1	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	2	0	0
T95	0	4	0	0
T235	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	14716	0	0
T12	7268	87	0	0
T19	1687	0	0	0
T20	8546	0	0	0
T32	0	104	0	0
T38	454044	0	0	0
T39	0	386	0	0
T40	0	119	0	0
T41	0	175	0	0
T44	0	356	0	0
T55	0	111	0	0
T66	448	0	0	0
T67	404	0	0	0
T68	2219	0	0	0
T80	494	0	0	0
T89	507	0	0	0
T90	525	0	0	0
T92	0	242	0	0
T95	0	212	0	0
T235	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	6895503	0	0
T1	505	105	0	0
T2	483	83	0	0
T4	447	47	0	0
T5	496	96	0	0
T13	422	22	0	0
T14	523	123	0	0
T15	708	308	0	0
T16	674	274	0	0
T17	1522	47	0	0
T18	497	97	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7365022	285	0	0
T32	15273	4	0	0
T39	0	10	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	14065	0	0	0
T44	0	6	0	0
T47	609	0	0	0
T54	608	0	0	0
T79	141205	0	0	0
T92	0	1	0	0
T95	0	3	0	0
T104	0	3	0	0
T187	521	0	0	0
T188	768	0	0	0
T189	502	0	0	0
T190	454	0	0	0
T234	0	4	0	0
T235	0	3	0	0
T260	8422	0	0	0