Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T50,T22,T51
1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T52,T50,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T52,T50,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T52,T50,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T22,T51
1	0	Covered	T22,T53,T55
1	1	Covered	T52,T50,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T52,T50,T22
0	1	Covered	T50,T51,T114
1	0	Covered	T280,T116,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T52,T22,T53
0	1	Covered	T22,T53,T55
1	0	Covered	T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T52,T22,T53
1	-	Covered	T22,T53,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T52,T50,T22
0	1	Covered	T52,T50,T22
0	0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T52,T50,T22
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T52,T50,T22
IdleSt	0	-	-	-	-	-	-	Covered	T50,T22,T51
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T52,T50,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T97,T281,T282
DebounceSt	-	0	0	-	-	-	-	Covered	T52,T50,T22
DetectSt	-	-	-	-	1	-	-	Covered	T50,T51,T114
DetectSt	-	-	-	-	0	1	-	Covered	T52,T22,T53
DetectSt	-	-	-	-	0	0	-	Covered	T52,T50,T22
StableSt	-	-	-	-	-	-	1	Covered	T22,T53,T55
StableSt	-	-	-	-	-	-	0	Covered	T52,T22,T53
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	3186	0	0
CntIncr_A	7802930	106327	0	0
CntNoWrap_A	7802930	7193245	0	0
DetectStDropOut_A	7802930	281	0	0
DetectedOut_A	7802930	98237	0	0
DetectedPulseOut_A	7802930	1146	0	0
DisabledIdleSt_A	7802930	6694512	0	0
DisabledNoDetection_A	7802930	6696548	0	0
EnterDebounceSt_A	7802930	1629	0	0
EnterDetectSt_A	7802930	1559	0	0
EnterStableSt_A	7802930	1146	0	0
PulseIsPulse_A	7802930	1146	0	0
StayInStableSt	7802930	96969	0	0
gen_high_event_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	1023	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	3186	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	60	0	0
T50	6967	20	0	0
T51	0	30	0	0
T52	469	2	0	0
T53	0	32	0	0
T54	0	52	0	0
T55	0	32	0	0
T61	0	14	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	62	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	50	0	0
T233	484	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	106327	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	2340	0	0
T50	6967	870	0	0
T51	0	960	0	0
T52	469	21	0	0
T53	0	944	0	0
T54	0	780	0	0
T55	0	1056	0	0
T61	0	525	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	744	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	1350	0	0
T233	484	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7193245	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	281	0	0
T22	24273	0	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	10	0	0
T51	5831	15	0	0
T75	4139	0	0	0
T76	506	0	0	0
T97	0	1	0	0
T107	666	0	0	0
T114	0	9	0	0
T116	0	5	0	0
T118	0	4	0	0
T119	0	26	0	0
T120	0	11	0	0
T121	0	5	0	0
T283	0	6	0	0
T284	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	98237	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	3044	0	0
T50	6967	0	0	0
T52	469	44	0	0
T53	0	1688	0	0
T54	0	2404	0	0
T55	0	1216	0	0
T61	0	147	0	0
T62	0	660	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	1814	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	4371	0	0
T233	484	0	0	0
T285	0	1234	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1146	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	30	0	0
T50	6967	0	0	0
T52	469	1	0	0
T53	0	16	0	0
T54	0	26	0	0
T55	0	16	0	0
T61	0	7	0	0
T62	0	8	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	31	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	25	0	0
T233	484	0	0	0
T285	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6694512	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6696548	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1629	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	30	0	0
T50	6967	10	0	0
T51	0	15	0	0
T52	469	1	0	0
T53	0	16	0	0
T54	0	26	0	0
T55	0	16	0	0
T61	0	7	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	31	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	25	0	0
T233	484	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1559	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	30	0	0
T50	6967	10	0	0
T51	0	15	0	0
T52	469	1	0	0
T53	0	16	0	0
T54	0	26	0	0
T55	0	16	0	0
T61	0	7	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	31	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	25	0	0
T233	484	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1146	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	30	0	0
T50	6967	0	0	0
T52	469	1	0	0
T53	0	16	0	0
T54	0	26	0	0
T55	0	16	0	0
T61	0	7	0	0
T62	0	8	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	31	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	25	0	0
T233	484	0	0	0
T285	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1146	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	30	0	0
T50	6967	0	0	0
T52	469	1	0	0
T53	0	16	0	0
T54	0	26	0	0
T55	0	16	0	0
T61	0	7	0	0
T62	0	8	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	31	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	25	0	0
T233	484	0	0	0
T285	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	96969	0	0
T20	6103	0	0	0
T21	17977	0	0	0
T22	24273	3008	0	0
T50	6967	0	0	0
T52	469	42	0	0
T53	0	1672	0	0
T54	0	2372	0	0
T55	0	1198	0	0
T61	0	140	0	0
T62	0	650	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	1779	0	0
T112	522	0	0	0
T113	443	0	0	0
T145	0	4344	0	0
T233	484	0	0	0
T285	0	1220	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1023	0	0
T22	24273	24	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	16	0	0
T54	0	20	0	0
T55	0	14	0	0
T61	0	7	0	0
T62	0	6	0	0
T101	0	27	0	0
T107	666	0	0	0
T145	0	23	0	0
T188	422	0	0	0
T284	427	0	0	0
T285	0	12	0	0
T286	0	19	0	0
T287	505	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T30,T17,T18
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T17,T18
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T30,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T30,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T17,T18,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T17,T18
1	0	Covered	T42,T30,T32
1	1	Covered	T30,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T20
0	1	Covered	T60,T115,T117
1	0	Covered	T97,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T20
0	1	Covered	T17,T18,T20
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T18,T20
1	-	Covered	T17,T18,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T17,T18
0	1	Covered	T30,T17,T18
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T20
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T17,T18
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T18,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T17,T18
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T17,T18
DetectSt	-	-	-	-	1	-	-	Covered	T60,T115,T97
DetectSt	-	-	-	-	0	1	-	Covered	T17,T18,T20
DetectSt	-	-	-	-	0	0	-	Covered	T17,T18,T20
StableSt	-	-	-	-	-	-	1	Covered	T17,T18,T20
StableSt	-	-	-	-	-	-	0	Covered	T17,T18,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	1130	0	0
CntIncr_A	7802930	59722	0	0
CntNoWrap_A	7802930	7195301	0	0
DetectStDropOut_A	7802930	96	0	0
DetectedOut_A	7802930	17534	0	0
DetectedPulseOut_A	7802930	395	0	0
DisabledIdleSt_A	7802930	6777286	0	0
DisabledNoDetection_A	7802930	6778766	0	0
EnterDebounceSt_A	7802930	639	0	0
EnterDetectSt_A	7802930	495	0	0
EnterStableSt_A	7802930	395	0	0
PulseIsPulse_A	7802930	395	0	0
StayInStableSt	7802930	17105	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	359	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1130	0	0
T17	23351	15	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	12	0	0
T21	0	10	0	0
T22	0	12	0	0
T25	0	10	0	0
T30	2227	1	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T52	0	1	0	0
T53	0	6	0	0
T73	523	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	59722	0	0
T17	23351	727	0	0
T18	0	269	0	0
T19	0	20	0	0
T20	0	672	0	0
T21	0	1172	0	0
T22	0	360	0	0
T25	0	660	0	0
T30	2227	20	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T52	0	20	0	0
T53	0	246	0	0
T73	523	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7195301	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	623	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	96	0	0
T54	21373	0	0	0
T60	14493	3	0	0
T101	14148	0	0	0
T110	662	0	0	0
T115	0	3	0	0
T117	0	4	0	0
T122	0	13	0	0
T123	0	1	0	0
T124	0	14	0	0
T126	0	4	0	0
T127	0	2	0	0
T128	0	3	0	0
T129	0	4	0	0
T131	521	0	0	0
T132	427	0	0	0
T133	481	0	0	0
T134	523	0	0	0
T135	424	0	0	0
T136	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	17534	0	0
T17	23351	491	0	0
T18	21291	37	0	0
T20	6103	73	0	0
T21	17977	15	0	0
T22	24273	504	0	0
T25	0	70	0	0
T50	6967	0	0	0
T53	0	132	0	0
T55	0	126	0	0
T70	0	4	0	0
T71	0	40	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	395	0	0
T17	23351	7	0	0
T18	21291	1	0	0
T20	6103	6	0	0
T21	17977	3	0	0
T22	24273	6	0	0
T25	0	4	0	0
T50	6967	0	0	0
T53	0	3	0	0
T55	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6777286	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	559	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6778766	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	561	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	639	0	0
T17	23351	8	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	0	6	0	0
T21	0	7	0	0
T22	0	6	0	0
T25	0	6	0	0
T30	2227	1	0	0
T31	526	0	0	0
T32	8457	0	0	0
T33	505	0	0	0
T34	402	0	0	0
T35	440	0	0	0
T36	409	0	0	0
T37	503	0	0	0
T52	0	1	0	0
T53	0	3	0	0
T73	523	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	495	0	0
T17	23351	7	0	0
T18	21291	1	0	0
T20	6103	6	0	0
T21	17977	3	0	0
T22	24273	6	0	0
T25	0	4	0	0
T50	6967	0	0	0
T53	0	3	0	0
T55	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	395	0	0
T17	23351	7	0	0
T18	21291	1	0	0
T20	6103	6	0	0
T21	17977	3	0	0
T22	24273	6	0	0
T25	0	4	0	0
T50	6967	0	0	0
T53	0	3	0	0
T55	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	395	0	0
T17	23351	7	0	0
T18	21291	1	0	0
T20	6103	6	0	0
T21	17977	3	0	0
T22	24273	6	0	0
T25	0	4	0	0
T50	6967	0	0	0
T53	0	3	0	0
T55	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	17105	0	0
T17	23351	484	0	0
T18	21291	36	0	0
T20	6103	67	0	0
T21	17977	12	0	0
T22	24273	498	0	0
T25	0	66	0	0
T50	6967	0	0	0
T53	0	129	0	0
T55	0	122	0	0
T70	0	3	0	0
T71	0	38	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	359	0	0
T17	23351	7	0	0
T18	21291	1	0	0
T20	6103	6	0	0
T21	17977	3	0	0
T22	24273	6	0	0
T25	0	4	0	0
T50	6967	0	0	0
T53	0	3	0	0
T54	0	6	0	0
T70	0	1	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T50,T22,T51
1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T50,T22,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T50,T22,T51

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T50,T22,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T22,T51
1	0	Covered	T22,T53,T55
1	1	Covered	T50,T22,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T22,T51
0	1	Covered	T50,T51,T55
1	0	Covered	T55,T101,T145

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T53,T54
0	1	Covered	T22,T53,T54
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T53,T54
1	-	Covered	T22,T53,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T50,T22,T51
0	1	Covered	T50,T22,T51
0	0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T22,T51
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T50,T22,T51
IdleSt	0	-	-	-	-	-	-	Covered	T50,T22,T51
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T22,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T97,T281,T282
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T22,T51
DetectSt	-	-	-	-	1	-	-	Covered	T50,T51,T55
DetectSt	-	-	-	-	0	1	-	Covered	T22,T53,T54
DetectSt	-	-	-	-	0	0	-	Covered	T50,T22,T51
StableSt	-	-	-	-	-	-	1	Covered	T22,T53,T54
StableSt	-	-	-	-	-	-	0	Covered	T22,T53,T54
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	3455	0	0
CntIncr_A	7802930	119873	0	0
CntNoWrap_A	7802930	7192976	0	0
DetectStDropOut_A	7802930	282	0	0
DetectedOut_A	7802930	105812	0	0
DetectedPulseOut_A	7802930	1186	0	0
DisabledIdleSt_A	7802930	6690030	0	0
DisabledNoDetection_A	7802930	6692062	0	0
EnterDebounceSt_A	7802930	1770	0	0
EnterDetectSt_A	7802930	1688	0	0
EnterStableSt_A	7802930	1186	0	0
PulseIsPulse_A	7802930	1186	0	0
StayInStableSt	7802930	104500	0	0
gen_high_event_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	1060	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	3455	0	0
T22	24273	54	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	48	0	0
T51	5831	42	0	0
T53	0	54	0	0
T54	0	62	0	0
T55	0	48	0	0
T61	0	20	0	0
T62	0	40	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	26	0	0
T107	666	0	0	0
T145	0	20	0	0
T284	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	119873	0	0
T22	24273	1485	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	2088	0	0
T51	5831	1344	0	0
T53	0	1593	0	0
T54	0	1457	0	0
T55	0	1889	0	0
T61	0	650	0	0
T62	0	1240	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	557	0	0
T107	666	0	0	0
T145	0	710	0	0
T284	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7192976	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	282	0	0
T22	24273	0	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	24	0	0
T51	5831	21	0	0
T55	0	7	0	0
T75	4139	0	0	0
T76	506	0	0	0
T97	0	1	0	0
T101	0	2	0	0
T107	666	0	0	0
T114	0	7	0	0
T116	0	13	0	0
T118	0	17	0	0
T119	0	9	0	0
T284	427	0	0	0
T286	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	105812	0	0
T22	24273	1659	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	2167	0	0
T54	0	1367	0	0
T61	0	447	0	0
T62	0	1480	0	0
T97	0	327	0	0
T107	666	0	0	0
T188	422	0	0	0
T280	0	915	0	0
T284	427	0	0	0
T285	0	1602	0	0
T287	505	0	0	0
T288	0	2512	0	0
T289	0	1383	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1186	0	0
T22	24273	27	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	27	0	0
T54	0	31	0	0
T61	0	10	0	0
T62	0	20	0	0
T97	0	5	0	0
T107	666	0	0	0
T188	422	0	0	0
T280	0	22	0	0
T284	427	0	0	0
T285	0	9	0	0
T287	505	0	0	0
T288	0	13	0	0
T289	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6690030	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6692062	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1770	0	0
T22	24273	27	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	24	0	0
T51	5831	21	0	0
T53	0	27	0	0
T54	0	31	0	0
T55	0	24	0	0
T61	0	10	0	0
T62	0	20	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	13	0	0
T107	666	0	0	0
T145	0	10	0	0
T284	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1688	0	0
T22	24273	27	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	24	0	0
T51	5831	21	0	0
T53	0	27	0	0
T54	0	31	0	0
T55	0	24	0	0
T61	0	10	0	0
T62	0	20	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	13	0	0
T107	666	0	0	0
T145	0	10	0	0
T284	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1186	0	0
T22	24273	27	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	27	0	0
T54	0	31	0	0
T61	0	10	0	0
T62	0	20	0	0
T97	0	5	0	0
T107	666	0	0	0
T188	422	0	0	0
T280	0	22	0	0
T284	427	0	0	0
T285	0	9	0	0
T287	505	0	0	0
T288	0	13	0	0
T289	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1186	0	0
T22	24273	27	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	27	0	0
T54	0	31	0	0
T61	0	10	0	0
T62	0	20	0	0
T97	0	5	0	0
T107	666	0	0	0
T188	422	0	0	0
T280	0	22	0	0
T284	427	0	0	0
T285	0	9	0	0
T287	505	0	0	0
T288	0	13	0	0
T289	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	104500	0	0
T22	24273	1630	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	2140	0	0
T54	0	1330	0	0
T61	0	436	0	0
T62	0	1459	0	0
T97	0	322	0	0
T107	666	0	0	0
T188	422	0	0	0
T280	0	893	0	0
T284	427	0	0	0
T285	0	1590	0	0
T287	505	0	0	0
T288	0	2496	0	0
T289	0	1369	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1060	0	0
T22	24273	25	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	27	0	0
T54	0	25	0	0
T61	0	9	0	0
T62	0	19	0	0
T97	0	5	0	0
T107	666	0	0	0
T188	422	0	0	0
T280	0	22	0	0
T284	427	0	0	0
T285	0	6	0	0
T287	505	0	0	0
T288	0	10	0	0
T289	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T18,T20
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T20
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T17,T18,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T17,T18,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T17,T18,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T20
1	0	Covered	T42,T30,T32
1	1	Covered	T17,T18,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T21
0	1	Covered	T60,T117,T82
1	0	Covered	T97,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T21
0	1	Covered	T17,T18,T21
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T18,T21
1	-	Covered	T17,T18,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T18,T21
0	1	Covered	T17,T18,T21
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T21
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T18,T21
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T18,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T25,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T18,T21
DetectSt	-	-	-	-	1	-	-	Covered	T60,T97,T117
DetectSt	-	-	-	-	0	1	-	Covered	T17,T18,T21
DetectSt	-	-	-	-	0	0	-	Covered	T17,T18,T21
StableSt	-	-	-	-	-	-	1	Covered	T17,T18,T21
StableSt	-	-	-	-	-	-	0	Covered	T17,T18,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	955	0	0
CntIncr_A	7802930	51624	0	0
CntNoWrap_A	7802930	7195476	0	0
DetectStDropOut_A	7802930	35	0	0
DetectedOut_A	7802930	18225	0	0
DetectedPulseOut_A	7802930	382	0	0
DisabledIdleSt_A	7802930	6790505	0	0
DisabledNoDetection_A	7802930	6792041	0	0
EnterDebounceSt_A	7802930	537	0	0
EnterDetectSt_A	7802930	422	0	0
EnterStableSt_A	7802930	382	0	0
PulseIsPulse_A	7802930	382	0	0
StayInStableSt	7802930	17808	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	344	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	955	0	0
T17	23351	2	0	0
T18	21291	4	0	0
T21	17977	6	0	0
T22	24273	2	0	0
T25	0	5	0	0
T50	6967	0	0	0
T53	0	10	0	0
T54	0	12	0	0
T60	0	4	0	0
T62	0	4	0	0
T71	0	4	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	51624	0	0
T17	23351	86	0	0
T18	21291	281	0	0
T21	17977	591	0	0
T22	24273	84	0	0
T25	0	375	0	0
T50	6967	0	0	0
T53	0	310	0	0
T54	0	312	0	0
T60	0	305	0	0
T62	0	104	0	0
T71	0	320	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7195476	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	35	0	0
T54	21373	0	0	0
T60	14493	1	0	0
T82	0	7	0	0
T101	14148	0	0	0
T110	662	0	0	0
T117	0	2	0	0
T129	0	3	0	0
T131	521	0	0	0
T132	427	0	0	0
T133	481	0	0	0
T134	523	0	0	0
T135	424	0	0	0
T136	525	0	0	0
T179	0	5	0	0
T247	0	1	0	0
T264	0	3	0	0
T290	0	7	0	0
T291	0	2	0	0
T292	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	18225	0	0
T17	23351	77	0	0
T18	21291	25	0	0
T21	17977	84	0	0
T22	24273	59	0	0
T25	0	62	0	0
T50	6967	0	0	0
T53	0	320	0	0
T54	0	305	0	0
T62	0	108	0	0
T71	0	48	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0
T168	0	142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	382	0	0
T17	23351	1	0	0
T18	21291	1	0	0
T21	17977	3	0	0
T22	24273	1	0	0
T25	0	2	0	0
T50	6967	0	0	0
T53	0	5	0	0
T54	0	6	0	0
T62	0	2	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0
T168	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6790505	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6792041	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	537	0	0
T17	23351	1	0	0
T18	21291	3	0	0
T21	17977	3	0	0
T22	24273	1	0	0
T25	0	3	0	0
T50	6967	0	0	0
T53	0	5	0	0
T54	0	6	0	0
T60	0	3	0	0
T62	0	2	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	422	0	0
T17	23351	1	0	0
T18	21291	1	0	0
T21	17977	3	0	0
T22	24273	1	0	0
T25	0	2	0	0
T50	6967	0	0	0
T53	0	5	0	0
T54	0	6	0	0
T60	0	1	0	0
T62	0	2	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	382	0	0
T17	23351	1	0	0
T18	21291	1	0	0
T21	17977	3	0	0
T22	24273	1	0	0
T25	0	2	0	0
T50	6967	0	0	0
T53	0	5	0	0
T54	0	6	0	0
T62	0	2	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0
T168	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	382	0	0
T17	23351	1	0	0
T18	21291	1	0	0
T21	17977	3	0	0
T22	24273	1	0	0
T25	0	2	0	0
T50	6967	0	0	0
T53	0	5	0	0
T54	0	6	0	0
T62	0	2	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0
T168	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	17808	0	0
T17	23351	76	0	0
T18	21291	24	0	0
T21	17977	81	0	0
T22	24273	57	0	0
T25	0	60	0	0
T50	6967	0	0	0
T53	0	315	0	0
T54	0	298	0	0
T62	0	106	0	0
T71	0	46	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T107	666	0	0	0
T168	0	140	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	344	0	0
T17	23351	1	0	0
T18	21291	1	0	0
T21	17977	3	0	0
T22	24273	0	0	0
T25	0	2	0	0
T50	6967	0	0	0
T53	0	5	0	0
T54	0	5	0	0
T62	0	2	0	0
T71	0	2	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T96	0	10	0	0
T107	666	0	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T50,T22,T51
1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T50,T22,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T50,T22,T51

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T50,T22,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T22,T51
1	0	Covered	T22,T53,T55
1	1	Covered	T50,T22,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T22,T51
0	1	Covered	T50,T51,T114
1	0	Covered	T54,T61,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T53,T55
0	1	Covered	T22,T53,T55
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T53,T55
1	-	Covered	T22,T53,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T50,T22,T51
0	1	Covered	T50,T22,T51
0	0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T22,T51
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T50,T22,T51
IdleSt	0	-	-	-	-	-	-	Covered	T50,T22,T51
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T22,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T97,T281,T282
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T22,T51
DetectSt	-	-	-	-	1	-	-	Covered	T50,T51,T54
DetectSt	-	-	-	-	0	1	-	Covered	T22,T53,T55
DetectSt	-	-	-	-	0	0	-	Covered	T50,T22,T51
StableSt	-	-	-	-	-	-	1	Covered	T22,T53,T55
StableSt	-	-	-	-	-	-	0	Covered	T22,T53,T55
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	3163	0	0
CntIncr_A	7802930	109265	0	0
CntNoWrap_A	7802930	7193268	0	0
DetectStDropOut_A	7802930	316	0	0
DetectedOut_A	7802930	89026	0	0
DetectedPulseOut_A	7802930	995	0	0
DisabledIdleSt_A	7802930	6698554	0	0
DisabledNoDetection_A	7802930	6700605	0	0
EnterDebounceSt_A	7802930	1619	0	0
EnterDetectSt_A	7802930	1547	0	0
EnterStableSt_A	7802930	995	0	0
PulseIsPulse_A	7802930	995	0	0
StayInStableSt	7802930	87924	0	0
gen_high_event_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	888	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	3163	0	0
T22	24273	26	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	26	0	0
T51	5831	10	0	0
T53	0	20	0	0
T54	0	26	0	0
T55	0	48	0	0
T61	0	64	0	0
T62	0	40	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	22	0	0
T107	666	0	0	0
T145	0	20	0	0
T284	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	109265	0	0
T22	24273	936	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	1131	0	0
T51	5831	320	0	0
T53	0	760	0	0
T54	0	702	0	0
T55	0	1344	0	0
T61	0	3008	0	0
T62	0	860	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	242	0	0
T107	666	0	0	0
T145	0	620	0	0
T284	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7193268	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	316	0	0
T22	24273	0	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	13	0	0
T51	5831	5	0	0
T75	4139	0	0	0
T76	506	0	0	0
T97	0	1	0	0
T102	0	2	0	0
T107	666	0	0	0
T114	0	12	0	0
T119	0	21	0	0
T120	0	3	0	0
T283	0	18	0	0
T284	427	0	0	0
T293	0	21	0	0
T294	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	89026	0	0
T22	24273	656	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	1332	0	0
T55	0	2690	0	0
T62	0	1860	0	0
T101	0	609	0	0
T107	666	0	0	0
T145	0	3228	0	0
T188	422	0	0	0
T280	0	1051	0	0
T284	427	0	0	0
T285	0	152	0	0
T286	0	3177	0	0
T287	505	0	0	0
T288	0	1381	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	995	0	0
T22	24273	13	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	10	0	0
T55	0	24	0	0
T62	0	20	0	0
T101	0	11	0	0
T107	666	0	0	0
T145	0	10	0	0
T188	422	0	0	0
T280	0	13	0	0
T284	427	0	0	0
T285	0	4	0	0
T286	0	25	0	0
T287	505	0	0	0
T288	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6698554	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6700605	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1619	0	0
T22	24273	13	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	13	0	0
T51	5831	5	0	0
T53	0	10	0	0
T54	0	13	0	0
T55	0	24	0	0
T61	0	32	0	0
T62	0	20	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	11	0	0
T107	666	0	0	0
T145	0	10	0	0
T284	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	1547	0	0
T22	24273	13	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T50	6967	13	0	0
T51	5831	5	0	0
T53	0	10	0	0
T54	0	13	0	0
T55	0	24	0	0
T61	0	32	0	0
T62	0	20	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	11	0	0
T107	666	0	0	0
T145	0	10	0	0
T284	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	995	0	0
T22	24273	13	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	10	0	0
T55	0	24	0	0
T62	0	20	0	0
T101	0	11	0	0
T107	666	0	0	0
T145	0	10	0	0
T188	422	0	0	0
T280	0	13	0	0
T284	427	0	0	0
T285	0	4	0	0
T286	0	25	0	0
T287	505	0	0	0
T288	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	995	0	0
T22	24273	13	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	10	0	0
T55	0	24	0	0
T62	0	20	0	0
T101	0	11	0	0
T107	666	0	0	0
T145	0	10	0	0
T188	422	0	0	0
T280	0	13	0	0
T284	427	0	0	0
T285	0	4	0	0
T286	0	25	0	0
T287	505	0	0	0
T288	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	87924	0	0
T22	24273	643	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	1322	0	0
T55	0	2661	0	0
T62	0	1839	0	0
T101	0	597	0	0
T107	666	0	0	0
T145	0	3217	0	0
T188	422	0	0	0
T280	0	1038	0	0
T284	427	0	0	0
T285	0	148	0	0
T286	0	3146	0	0
T287	505	0	0	0
T288	0	1362	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	888	0	0
T22	24273	13	0	0
T23	677	0	0	0
T24	851	0	0	0
T25	27520	0	0	0
T51	5831	0	0	0
T53	8423	10	0	0
T55	0	19	0	0
T62	0	19	0	0
T101	0	10	0	0
T107	666	0	0	0
T145	0	9	0	0
T188	422	0	0	0
T280	0	13	0	0
T284	427	0	0	0
T285	0	4	0	0
T286	0	19	0	0
T287	505	0	0	0
T288	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T18,T20
1	Covered	T42,T43,T44

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T20
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T17,T18,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T42,T43,T44	VC_COV_UNR
1	Covered	T17,T18,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T17,T18,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T20
1	0	Covered	T42,T30,T32
1	1	Covered	T17,T18,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T20
0	1	Covered	T20,T96,T115
1	0	Covered	T97,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T21
0	1	Covered	T17,T18,T21
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T18,T21
1	-	Covered	T17,T18,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T18,T20
0	1	Covered	T17,T18,T20
0	0	Excluded	T42,T43,T44	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T20
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T18,T20
IdleSt	0	-	-	-	-	-	-	Covered	T42,T43,T44
DebounceSt	-	1	-	-	-	-	-	Covered	T97,T98
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T18,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T20,T25
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T18,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20,T96,T115
DetectSt	-	-	-	-	0	1	-	Covered	T17,T18,T21
DetectSt	-	-	-	-	0	0	-	Covered	T17,T18,T20
StableSt	-	-	-	-	-	-	1	Covered	T17,T18,T21
StableSt	-	-	-	-	-	-	0	Covered	T17,T18,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T42,T43,T44

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7802930	917	0	0
CntIncr_A	7802930	54532	0	0
CntNoWrap_A	7802930	7195514	0	0
DetectStDropOut_A	7802930	86	0	0
DetectedOut_A	7802930	15543	0	0
DetectedPulseOut_A	7802930	312	0	0
DisabledIdleSt_A	7802930	6791080	0	0
DisabledNoDetection_A	7802930	6792635	0	0
EnterDebounceSt_A	7802930	517	0	0
EnterDetectSt_A	7802930	403	0	0
EnterStableSt_A	7802930	312	0	0
PulseIsPulse_A	7802930	312	0	0
StayInStableSt	7802930	15191	0	0
gen_high_level_sva.HighLevelEvent_A	7802930	7198689	0	0
gen_not_sticky_sva.StableStDropOut_A	7802930	270	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	917	0	0
T17	23351	17	0	0
T18	21291	12	0	0
T20	6103	3	0	0
T21	17977	8	0	0
T22	24273	0	0	0
T25	0	12	0	0
T50	6967	0	0	0
T55	0	10	0	0
T60	0	6	0	0
T71	0	6	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	4	0	0
T145	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	54532	0	0
T17	23351	1340	0	0
T18	21291	738	0	0
T20	6103	165	0	0
T21	17977	696	0	0
T22	24273	0	0	0
T25	0	747	0	0
T50	6967	0	0	0
T55	0	230	0	0
T60	0	387	0	0
T71	0	534	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	80	0	0
T145	0	264	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7195514	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	86	0	0
T20	6103	1	0	0
T21	17977	0	0	0
T22	24273	0	0	0
T23	677	0	0	0
T50	6967	0	0	0
T51	5831	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T96	0	15	0	0
T107	666	0	0	0
T115	0	11	0	0
T124	0	3	0	0
T230	0	5	0	0
T278	0	3	0	0
T284	427	0	0	0
T295	0	3	0	0
T296	0	7	0	0
T297	0	1	0	0
T298	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	15543	0	0
T17	23351	40	0	0
T18	21291	295	0	0
T21	17977	205	0	0
T22	24273	0	0	0
T25	0	300	0	0
T50	6967	0	0	0
T55	0	455	0	0
T60	0	37	0	0
T62	0	300	0	0
T71	0	18	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	90	0	0
T107	666	0	0	0
T145	0	1268	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	312	0	0
T17	23351	8	0	0
T18	21291	6	0	0
T21	17977	4	0	0
T22	24273	0	0	0
T25	0	5	0	0
T50	6967	0	0	0
T55	0	5	0	0
T60	0	3	0	0
T62	0	5	0	0
T71	0	3	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	2	0	0
T107	666	0	0	0
T145	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6791080	0	0
T16	625	224	0	0
T29	500	99	0	0
T30	2227	624	0	0
T31	526	125	0	0
T42	1536	334	0	0
T43	681	280	0	0
T44	503	102	0	0
T91	482	81	0	0
T103	525	124	0	0
T111	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	6792635	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	517	0	0
T17	23351	9	0	0
T18	21291	6	0	0
T20	6103	2	0	0
T21	17977	4	0	0
T22	24273	0	0	0
T25	0	7	0	0
T50	6967	0	0	0
T55	0	5	0	0
T60	0	3	0	0
T71	0	3	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	2	0	0
T145	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	403	0	0
T17	23351	8	0	0
T18	21291	6	0	0
T20	6103	1	0	0
T21	17977	4	0	0
T22	24273	0	0	0
T25	0	5	0	0
T50	6967	0	0	0
T55	0	5	0	0
T60	0	3	0	0
T71	0	3	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	2	0	0
T145	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	312	0	0
T17	23351	8	0	0
T18	21291	6	0	0
T21	17977	4	0	0
T22	24273	0	0	0
T25	0	5	0	0
T50	6967	0	0	0
T55	0	5	0	0
T60	0	3	0	0
T62	0	5	0	0
T71	0	3	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	2	0	0
T107	666	0	0	0
T145	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	312	0	0
T17	23351	8	0	0
T18	21291	6	0	0
T21	17977	4	0	0
T22	24273	0	0	0
T25	0	5	0	0
T50	6967	0	0	0
T55	0	5	0	0
T60	0	3	0	0
T62	0	5	0	0
T71	0	3	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	2	0	0
T107	666	0	0	0
T145	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	15191	0	0
T17	23351	32	0	0
T18	21291	289	0	0
T21	17977	201	0	0
T22	24273	0	0	0
T25	0	295	0	0
T50	6967	0	0	0
T55	0	445	0	0
T60	0	34	0	0
T62	0	295	0	0
T71	0	15	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T101	0	88	0	0
T107	666	0	0	0
T145	0	1264	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	7198689	0	0
T16	625	225	0	0
T29	500	100	0	0
T30	2227	627	0	0
T31	526	126	0	0
T42	1536	336	0	0
T43	681	281	0	0
T44	503	103	0	0
T91	482	82	0	0
T103	525	125	0	0
T111	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7802930	270	0	0
T17	23351	8	0	0
T18	21291	6	0	0
T21	17977	4	0	0
T22	24273	0	0	0
T25	0	5	0	0
T50	6967	0	0	0
T60	0	3	0	0
T62	0	5	0	0
T71	0	3	0	0
T73	523	0	0	0
T74	522	0	0	0
T75	4139	0	0	0
T76	506	0	0	0
T90	0	2	0	0
T101	0	2	0	0
T107	666	0	0	0
T145	0	4	0	0