Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Total | Covered | Percent |
Conditions | 19 | 19 | 100.00 |
Logical | 19 | 19 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T50,T22,T51 |
1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T50,T22,T51 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T50,T22,T51 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T50,T22,T51 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T50,T22,T51 |
1 | 0 | Covered | T22,T53,T55 |
1 | 1 | Covered | T50,T22,T51 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T50,T22,T51 |
0 | 1 | Covered | T50,T51,T101 |
1 | 0 | Covered | T54,T101,T280 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T22,T53,T55 |
0 | 1 | Covered | T22,T53,T55 |
1 | 0 | Covered | T102 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T22,T53,T55 |
1 | - | Covered | T22,T53,T55 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T6 |
DetectSt |
168 |
Covered |
T6 |
IdleSt |
163 |
Covered |
T6 |
StableSt |
191 |
Covered |
T6 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T6 |
DebounceSt->IdleSt |
163 |
Covered |
T6 |
DetectSt->IdleSt |
186 |
Covered |
T6 |
DetectSt->StableSt |
191 |
Covered |
T6 |
IdleSt->DebounceSt |
148 |
Covered |
T6 |
StableSt->IdleSt |
206 |
Covered |
T6 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T50,T22,T51 |
0 |
1 |
Covered |
T50,T22,T51 |
0 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T50,T22,T51 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T50,T22,T51 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T50,T22,T51 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T97,T98 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T50,T22,T51 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T97,T281,T282 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T50,T22,T51 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T50,T51,T54 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T22,T53,T55 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T50,T22,T51 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T22,T53,T55 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T22,T53,T55 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T42,T43,T44 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
3188 |
0 |
0 |
T22 |
24273 |
34 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T50 |
6967 |
20 |
0 |
0 |
T51 |
5831 |
20 |
0 |
0 |
T53 |
0 |
48 |
0 |
0 |
T54 |
0 |
52 |
0 |
0 |
T55 |
0 |
32 |
0 |
0 |
T61 |
0 |
64 |
0 |
0 |
T62 |
0 |
26 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T101 |
0 |
52 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
28 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
107385 |
0 |
0 |
T22 |
24273 |
1156 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T50 |
6967 |
870 |
0 |
0 |
T51 |
5831 |
640 |
0 |
0 |
T53 |
0 |
1560 |
0 |
0 |
T54 |
0 |
1404 |
0 |
0 |
T55 |
0 |
848 |
0 |
0 |
T61 |
0 |
2176 |
0 |
0 |
T62 |
0 |
741 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T101 |
0 |
1112 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
840 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
7193243 |
0 |
0 |
T16 |
625 |
224 |
0 |
0 |
T29 |
500 |
99 |
0 |
0 |
T30 |
2227 |
624 |
0 |
0 |
T31 |
526 |
125 |
0 |
0 |
T42 |
1536 |
334 |
0 |
0 |
T43 |
681 |
280 |
0 |
0 |
T44 |
503 |
102 |
0 |
0 |
T91 |
482 |
81 |
0 |
0 |
T103 |
525 |
124 |
0 |
0 |
T111 |
522 |
121 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
326 |
0 |
0 |
T22 |
24273 |
0 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T50 |
6967 |
10 |
0 |
0 |
T51 |
5831 |
10 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T97 |
0 |
1 |
0 |
0 |
T101 |
0 |
6 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T114 |
0 |
30 |
0 |
0 |
T116 |
0 |
5 |
0 |
0 |
T118 |
0 |
15 |
0 |
0 |
T119 |
0 |
12 |
0 |
0 |
T120 |
0 |
19 |
0 |
0 |
T280 |
0 |
5 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
91749 |
0 |
0 |
T22 |
24273 |
2036 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T53 |
8423 |
600 |
0 |
0 |
T55 |
0 |
1146 |
0 |
0 |
T61 |
0 |
2745 |
0 |
0 |
T62 |
0 |
928 |
0 |
0 |
T97 |
0 |
270 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
2101 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T285 |
0 |
3603 |
0 |
0 |
T286 |
0 |
446 |
0 |
0 |
T287 |
505 |
0 |
0 |
0 |
T288 |
0 |
1381 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
992 |
0 |
0 |
T22 |
24273 |
17 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T53 |
8423 |
24 |
0 |
0 |
T55 |
0 |
16 |
0 |
0 |
T61 |
0 |
32 |
0 |
0 |
T62 |
0 |
13 |
0 |
0 |
T97 |
0 |
5 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
14 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T285 |
0 |
27 |
0 |
0 |
T286 |
0 |
1 |
0 |
0 |
T287 |
505 |
0 |
0 |
0 |
T288 |
0 |
17 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
6697056 |
0 |
0 |
T16 |
625 |
224 |
0 |
0 |
T29 |
500 |
99 |
0 |
0 |
T30 |
2227 |
624 |
0 |
0 |
T31 |
526 |
125 |
0 |
0 |
T42 |
1536 |
334 |
0 |
0 |
T43 |
681 |
280 |
0 |
0 |
T44 |
503 |
102 |
0 |
0 |
T91 |
482 |
81 |
0 |
0 |
T103 |
525 |
124 |
0 |
0 |
T111 |
522 |
121 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
6699108 |
0 |
0 |
T16 |
625 |
225 |
0 |
0 |
T29 |
500 |
100 |
0 |
0 |
T30 |
2227 |
627 |
0 |
0 |
T31 |
526 |
126 |
0 |
0 |
T42 |
1536 |
336 |
0 |
0 |
T43 |
681 |
281 |
0 |
0 |
T44 |
503 |
103 |
0 |
0 |
T91 |
482 |
82 |
0 |
0 |
T103 |
525 |
125 |
0 |
0 |
T111 |
522 |
122 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
1630 |
0 |
0 |
T22 |
24273 |
17 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T50 |
6967 |
10 |
0 |
0 |
T51 |
5831 |
10 |
0 |
0 |
T53 |
0 |
24 |
0 |
0 |
T54 |
0 |
26 |
0 |
0 |
T55 |
0 |
16 |
0 |
0 |
T61 |
0 |
32 |
0 |
0 |
T62 |
0 |
13 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T101 |
0 |
26 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
14 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
1561 |
0 |
0 |
T22 |
24273 |
17 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T50 |
6967 |
10 |
0 |
0 |
T51 |
5831 |
10 |
0 |
0 |
T53 |
0 |
24 |
0 |
0 |
T54 |
0 |
26 |
0 |
0 |
T55 |
0 |
16 |
0 |
0 |
T61 |
0 |
32 |
0 |
0 |
T62 |
0 |
13 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T101 |
0 |
26 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
14 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
992 |
0 |
0 |
T22 |
24273 |
17 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T53 |
8423 |
24 |
0 |
0 |
T55 |
0 |
16 |
0 |
0 |
T61 |
0 |
32 |
0 |
0 |
T62 |
0 |
13 |
0 |
0 |
T97 |
0 |
5 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
14 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T285 |
0 |
27 |
0 |
0 |
T286 |
0 |
1 |
0 |
0 |
T287 |
505 |
0 |
0 |
0 |
T288 |
0 |
17 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
992 |
0 |
0 |
T22 |
24273 |
17 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T53 |
8423 |
24 |
0 |
0 |
T55 |
0 |
16 |
0 |
0 |
T61 |
0 |
32 |
0 |
0 |
T62 |
0 |
13 |
0 |
0 |
T97 |
0 |
5 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
14 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T285 |
0 |
27 |
0 |
0 |
T286 |
0 |
1 |
0 |
0 |
T287 |
505 |
0 |
0 |
0 |
T288 |
0 |
17 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
90651 |
0 |
0 |
T22 |
24273 |
2015 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T53 |
8423 |
576 |
0 |
0 |
T55 |
0 |
1129 |
0 |
0 |
T61 |
0 |
2709 |
0 |
0 |
T62 |
0 |
912 |
0 |
0 |
T97 |
0 |
265 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
2084 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T285 |
0 |
3570 |
0 |
0 |
T286 |
0 |
444 |
0 |
0 |
T287 |
505 |
0 |
0 |
0 |
T288 |
0 |
1362 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
7198689 |
0 |
0 |
T16 |
625 |
225 |
0 |
0 |
T29 |
500 |
100 |
0 |
0 |
T30 |
2227 |
627 |
0 |
0 |
T31 |
526 |
126 |
0 |
0 |
T42 |
1536 |
336 |
0 |
0 |
T43 |
681 |
281 |
0 |
0 |
T44 |
503 |
103 |
0 |
0 |
T91 |
482 |
82 |
0 |
0 |
T103 |
525 |
125 |
0 |
0 |
T111 |
522 |
122 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
7198689 |
0 |
0 |
T16 |
625 |
225 |
0 |
0 |
T29 |
500 |
100 |
0 |
0 |
T30 |
2227 |
627 |
0 |
0 |
T31 |
526 |
126 |
0 |
0 |
T42 |
1536 |
336 |
0 |
0 |
T43 |
681 |
281 |
0 |
0 |
T44 |
503 |
103 |
0 |
0 |
T91 |
482 |
82 |
0 |
0 |
T103 |
525 |
125 |
0 |
0 |
T111 |
522 |
122 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
877 |
0 |
0 |
T22 |
24273 |
13 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T25 |
27520 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T53 |
8423 |
24 |
0 |
0 |
T55 |
0 |
15 |
0 |
0 |
T61 |
0 |
28 |
0 |
0 |
T62 |
0 |
10 |
0 |
0 |
T97 |
0 |
5 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
11 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T285 |
0 |
21 |
0 |
0 |
T287 |
505 |
0 |
0 |
0 |
T288 |
0 |
15 |
0 |
0 |
T289 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Total | Covered | Percent |
Conditions | 21 | 20 | 95.24 |
Logical | 21 | 20 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T17,T18,T21 |
1 | Covered | T42,T43,T44 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T17,T18,T21 |
1 | 0 | Covered | T42,T43,T44 |
1 | 1 | Covered | T42,T43,T44 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T17,T18,T21 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T42,T43,T44 |
VC_COV_UNR |
1 | Covered | T17,T18,T21 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T42,T43,T44 |
1 | Covered | T17,T21,T22 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T17,T18,T21 |
1 | 0 | Covered | T42,T30,T32 |
1 | 1 | Covered | T17,T18,T21 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T17,T21,T22 |
0 | 1 | Covered | T17,T25,T299 |
1 | 0 | Covered | T97,T98 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T21,T22,T71 |
0 | 1 | Covered | T21,T22,T71 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T21,T22,T71 |
1 | - | Covered | T21,T22,T71 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T6 |
DetectSt |
168 |
Covered |
T6 |
IdleSt |
163 |
Covered |
T6 |
StableSt |
191 |
Covered |
T6 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T6 |
DebounceSt->IdleSt |
163 |
Covered |
T6 |
DetectSt->IdleSt |
186 |
Covered |
T6 |
DetectSt->StableSt |
191 |
Covered |
T6 |
IdleSt->DebounceSt |
148 |
Covered |
T6 |
StableSt->IdleSt |
206 |
Covered |
T6 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
21 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
11 |
11 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T17,T18,T21 |
|
0 |
1 |
Covered |
T17,T18,T21 |
|
0 |
0 |
Excluded |
T42,T43,T44 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T17,T21,T22 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T17,T18,T21 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T42,T43,T44 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T97,T98 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T17,T21,T22 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T18,T21,T25 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T17,T18,T21 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T17,T25,T299 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T21,T22,T71 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T17,T21,T22 |
|
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T21,T22,T71 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T21,T22,T71 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T42,T43,T44 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T42,T43,T44 |
0 |
Covered |
T42,T43,T44 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
933 |
0 |
0 |
T17 |
23351 |
2 |
0 |
0 |
T18 |
21291 |
1 |
0 |
0 |
T21 |
17977 |
9 |
0 |
0 |
T22 |
24273 |
8 |
0 |
0 |
T25 |
0 |
11 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T60 |
0 |
12 |
0 |
0 |
T61 |
0 |
8 |
0 |
0 |
T62 |
0 |
6 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T73 |
523 |
0 |
0 |
0 |
T74 |
522 |
0 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
6 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
53790 |
0 |
0 |
T17 |
23351 |
163 |
0 |
0 |
T18 |
21291 |
67 |
0 |
0 |
T21 |
17977 |
992 |
0 |
0 |
T22 |
24273 |
216 |
0 |
0 |
T25 |
0 |
965 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T60 |
0 |
732 |
0 |
0 |
T61 |
0 |
300 |
0 |
0 |
T62 |
0 |
123 |
0 |
0 |
T71 |
0 |
137 |
0 |
0 |
T73 |
523 |
0 |
0 |
0 |
T74 |
522 |
0 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
276 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
7195498 |
0 |
0 |
T16 |
625 |
224 |
0 |
0 |
T29 |
500 |
99 |
0 |
0 |
T30 |
2227 |
624 |
0 |
0 |
T31 |
526 |
125 |
0 |
0 |
T42 |
1536 |
334 |
0 |
0 |
T43 |
681 |
280 |
0 |
0 |
T44 |
503 |
102 |
0 |
0 |
T91 |
482 |
81 |
0 |
0 |
T103 |
525 |
124 |
0 |
0 |
T111 |
522 |
121 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
97 |
0 |
0 |
T17 |
23351 |
1 |
0 |
0 |
T18 |
21291 |
0 |
0 |
0 |
T25 |
27520 |
4 |
0 |
0 |
T57 |
14272 |
0 |
0 |
0 |
T73 |
523 |
0 |
0 |
0 |
T74 |
522 |
0 |
0 |
0 |
T82 |
0 |
4 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T295 |
0 |
7 |
0 |
0 |
T297 |
0 |
3 |
0 |
0 |
T299 |
13503 |
1 |
0 |
0 |
T300 |
0 |
14 |
0 |
0 |
T301 |
0 |
13 |
0 |
0 |
T302 |
0 |
10 |
0 |
0 |
T303 |
404 |
0 |
0 |
0 |
T304 |
415 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
15246 |
0 |
0 |
T21 |
17977 |
36 |
0 |
0 |
T22 |
24273 |
360 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T60 |
0 |
160 |
0 |
0 |
T61 |
0 |
204 |
0 |
0 |
T62 |
0 |
195 |
0 |
0 |
T71 |
0 |
47 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T96 |
0 |
168 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T115 |
0 |
78 |
0 |
0 |
T145 |
0 |
870 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T299 |
0 |
108 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
309 |
0 |
0 |
T21 |
17977 |
4 |
0 |
0 |
T22 |
24273 |
4 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T60 |
0 |
4 |
0 |
0 |
T61 |
0 |
4 |
0 |
0 |
T62 |
0 |
3 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T96 |
0 |
6 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T115 |
0 |
11 |
0 |
0 |
T145 |
0 |
3 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T299 |
0 |
2 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
6802625 |
0 |
0 |
T16 |
625 |
224 |
0 |
0 |
T29 |
500 |
99 |
0 |
0 |
T30 |
2227 |
624 |
0 |
0 |
T31 |
526 |
125 |
0 |
0 |
T42 |
1536 |
334 |
0 |
0 |
T43 |
681 |
280 |
0 |
0 |
T44 |
503 |
102 |
0 |
0 |
T91 |
482 |
81 |
0 |
0 |
T103 |
525 |
124 |
0 |
0 |
T111 |
522 |
121 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
6804192 |
0 |
0 |
T16 |
625 |
225 |
0 |
0 |
T29 |
500 |
100 |
0 |
0 |
T30 |
2227 |
627 |
0 |
0 |
T31 |
526 |
126 |
0 |
0 |
T42 |
1536 |
336 |
0 |
0 |
T43 |
681 |
281 |
0 |
0 |
T44 |
503 |
103 |
0 |
0 |
T91 |
482 |
82 |
0 |
0 |
T103 |
525 |
125 |
0 |
0 |
T111 |
522 |
122 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
524 |
0 |
0 |
T17 |
23351 |
1 |
0 |
0 |
T18 |
21291 |
1 |
0 |
0 |
T21 |
17977 |
5 |
0 |
0 |
T22 |
24273 |
4 |
0 |
0 |
T25 |
0 |
7 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T60 |
0 |
8 |
0 |
0 |
T61 |
0 |
4 |
0 |
0 |
T62 |
0 |
3 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T73 |
523 |
0 |
0 |
0 |
T74 |
522 |
0 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
3 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
409 |
0 |
0 |
T17 |
23351 |
1 |
0 |
0 |
T18 |
21291 |
0 |
0 |
0 |
T21 |
17977 |
4 |
0 |
0 |
T22 |
24273 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T60 |
0 |
4 |
0 |
0 |
T61 |
0 |
4 |
0 |
0 |
T62 |
0 |
3 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T73 |
523 |
0 |
0 |
0 |
T74 |
522 |
0 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T96 |
0 |
6 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T145 |
0 |
3 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
309 |
0 |
0 |
T21 |
17977 |
4 |
0 |
0 |
T22 |
24273 |
4 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T60 |
0 |
4 |
0 |
0 |
T61 |
0 |
4 |
0 |
0 |
T62 |
0 |
3 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T96 |
0 |
6 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T115 |
0 |
11 |
0 |
0 |
T145 |
0 |
3 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T299 |
0 |
2 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
309 |
0 |
0 |
T21 |
17977 |
4 |
0 |
0 |
T22 |
24273 |
4 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T60 |
0 |
4 |
0 |
0 |
T61 |
0 |
4 |
0 |
0 |
T62 |
0 |
3 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T96 |
0 |
6 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T115 |
0 |
11 |
0 |
0 |
T145 |
0 |
3 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T299 |
0 |
2 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
14901 |
0 |
0 |
T21 |
17977 |
32 |
0 |
0 |
T22 |
24273 |
356 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T60 |
0 |
156 |
0 |
0 |
T61 |
0 |
200 |
0 |
0 |
T62 |
0 |
192 |
0 |
0 |
T71 |
0 |
46 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T96 |
0 |
162 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T115 |
0 |
67 |
0 |
0 |
T145 |
0 |
864 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T299 |
0 |
106 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
7198689 |
0 |
0 |
T16 |
625 |
225 |
0 |
0 |
T29 |
500 |
100 |
0 |
0 |
T30 |
2227 |
627 |
0 |
0 |
T31 |
526 |
126 |
0 |
0 |
T42 |
1536 |
336 |
0 |
0 |
T43 |
681 |
281 |
0 |
0 |
T44 |
503 |
103 |
0 |
0 |
T91 |
482 |
82 |
0 |
0 |
T103 |
525 |
125 |
0 |
0 |
T111 |
522 |
122 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7802930 |
271 |
0 |
0 |
T21 |
17977 |
4 |
0 |
0 |
T22 |
24273 |
4 |
0 |
0 |
T23 |
677 |
0 |
0 |
0 |
T24 |
851 |
0 |
0 |
0 |
T50 |
6967 |
0 |
0 |
0 |
T51 |
5831 |
0 |
0 |
0 |
T60 |
0 |
4 |
0 |
0 |
T61 |
0 |
4 |
0 |
0 |
T62 |
0 |
3 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T75 |
4139 |
0 |
0 |
0 |
T76 |
506 |
0 |
0 |
0 |
T83 |
0 |
2 |
0 |
0 |
T96 |
0 |
6 |
0 |
0 |
T107 |
666 |
0 |
0 |
0 |
T115 |
0 |
11 |
0 |
0 |
T284 |
427 |
0 |
0 |
0 |
T299 |
0 |
2 |
0 |
0 |