Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T11 T21 T30
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T11 T21 T30
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T11 T21 T30
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
105 1/1 cnt_q <= '0;
Tests: T1 T2 T4
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T4
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T11 T21 T30
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T11 T21 T30
129 1/1 cnt_en = 1'b0;
Tests: T11 T21 T30
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T11 T21 T30
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T11 T21 T30
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T11 T21 T30
139
140 1/1 unique case (state_q)
Tests: T11 T21 T30
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T11 T21 T30
148 1/1 state_d = DebounceSt;
Tests: T11 T21 T30
149 1/1 cnt_en = 1'b1;
Tests: T11 T21 T30
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T11 T21 T30
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T11 T21 T30
163 1/1 state_d = IdleSt;
Tests: T21 T56
164 1/1 cnt_clr = 1'b1;
Tests: T21 T56
165 1/1 end else if (cnt_done) begin
Tests: T11 T21 T30
166 1/1 cnt_clr = 1'b1;
Tests: T11 T21 T30
167 1/1 if (trigger_active) begin
Tests: T11 T21 T30
168 1/1 state_d = DetectSt;
Tests: T11 T21 T30
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T21 T56 T120
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T11 T21 T30
182 1/1 cnt_en = 1'b1;
Tests: T11 T21 T30
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T11 T21 T30
186 1/1 state_d = IdleSt;
Tests: T11 T21 T30
187 1/1 cnt_clr = 1'b1;
Tests: T11 T21 T30
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T11 T21 T30
191 1/1 state_d = StableSt;
Tests: T11 T21 T40
192 1/1 cnt_clr = 1'b1;
Tests: T11 T21 T40
193 1/1 event_detected_o = 1'b1;
Tests: T11 T21 T40
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T11 T21 T40
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T11 T21 T40
206 1/1 state_d = IdleSt;
Tests: T11 T21 T40
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T11 T21 T40
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
220 1/1 state_q <= IdleSt;
Tests: T1 T2 T4
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T2 T4
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Total | Covered | Percent |
Conditions | 19 | 19 | 100.00 |
Logical | 19 | 19 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T11,T21,T30 |
1 | Covered | T1,T2,T4 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T11,T21,T30 |
1 | 0 | Covered | T11,T21,T30 |
1 | 1 | Covered | T11,T21,T30 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T11,T21,T30 |
0 | 1 | Covered | T11,T21,T56 |
1 | 0 | Covered | T11,T21,T30 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T11,T21,T40 |
0 | 1 | Covered | T21,T40,T56 |
1 | 0 | Covered | T11,T21,T124 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T11,T21,T40 |
1 | - | Covered | T21,T40,T56 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| | | |
DebounceSt |
148 |
Covered |
T11,T21,T30 |
DetectSt |
168 |
Covered |
T11,T21,T30 |
IdleSt |
163 |
Covered |
T1,T2,T4 |
StableSt |
191 |
Covered |
T11,T21,T40 |
| | | |
DebounceSt->DetectSt |
168 |
Covered |
T11,T21,T30 |
DebounceSt->IdleSt |
163 |
Covered |
T21,T56,T120 |
DetectSt->IdleSt |
186 |
Covered |
T11,T21,T30 |
DetectSt->StableSt |
191 |
Covered |
T11,T21,T40 |
IdleSt->DebounceSt |
148 |
Covered |
T11,T21,T30 |
StableSt->IdleSt |
206 |
Covered |
T11,T21,T40 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T11,T21,T30 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T11,T21,T30 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T11,T21,T30 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T21,T56 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T11,T21,T30 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T21,T56,T120 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T11,T21,T30 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T11,T21,T30 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T11,T21,T40 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T11,T21,T30 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T11,T21,T40 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T11,T21,T40 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
3343 |
0 |
0 |
T11 |
30017 |
22 |
0 |
0 |
T21 |
0 |
16 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T40 |
0 |
18 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
16 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T88 |
0 |
52 |
0 |
0 |
T89 |
0 |
14 |
0 |
0 |
T90 |
0 |
28 |
0 |
0 |
T91 |
0 |
26 |
0 |
0 |
T92 |
0 |
50 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
106208 |
0 |
0 |
T11 |
30017 |
468 |
0 |
0 |
T21 |
0 |
588 |
0 |
0 |
T30 |
0 |
447 |
0 |
0 |
T40 |
0 |
882 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
541 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T88 |
0 |
1319 |
0 |
0 |
T89 |
0 |
512 |
0 |
0 |
T90 |
0 |
607 |
0 |
0 |
T91 |
0 |
966 |
0 |
0 |
T92 |
0 |
1400 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
6361507 |
0 |
0 |
T1 |
509 |
108 |
0 |
0 |
T2 |
486 |
85 |
0 |
0 |
T3 |
481 |
80 |
0 |
0 |
T4 |
666 |
265 |
0 |
0 |
T12 |
747 |
346 |
0 |
0 |
T13 |
523 |
122 |
0 |
0 |
T14 |
412 |
11 |
0 |
0 |
T15 |
423 |
22 |
0 |
0 |
T16 |
1038 |
637 |
0 |
0 |
T17 |
426 |
25 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
439 |
0 |
0 |
T11 |
30017 |
6 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T88 |
0 |
9 |
0 |
0 |
T89 |
0 |
7 |
0 |
0 |
T90 |
0 |
14 |
0 |
0 |
T91 |
0 |
5 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
T134 |
0 |
16 |
0 |
0 |
T324 |
0 |
25 |
0 |
0 |
T327 |
0 |
9 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
73157 |
0 |
0 |
T11 |
30017 |
4 |
0 |
0 |
T21 |
0 |
459 |
0 |
0 |
T40 |
0 |
131 |
0 |
0 |
T44 |
0 |
1377 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
403 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T92 |
0 |
2518 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
T124 |
0 |
1 |
0 |
0 |
T199 |
0 |
903 |
0 |
0 |
T328 |
0 |
360 |
0 |
0 |
T329 |
0 |
246 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
923 |
0 |
0 |
T11 |
30017 |
3 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T44 |
0 |
22 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
5 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T92 |
0 |
25 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
T124 |
0 |
1 |
0 |
0 |
T199 |
0 |
11 |
0 |
0 |
T328 |
0 |
14 |
0 |
0 |
T329 |
0 |
2 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
5906657 |
0 |
0 |
T1 |
509 |
108 |
0 |
0 |
T2 |
486 |
85 |
0 |
0 |
T3 |
481 |
80 |
0 |
0 |
T4 |
666 |
265 |
0 |
0 |
T12 |
747 |
346 |
0 |
0 |
T13 |
523 |
122 |
0 |
0 |
T14 |
412 |
11 |
0 |
0 |
T15 |
423 |
22 |
0 |
0 |
T16 |
1038 |
637 |
0 |
0 |
T17 |
426 |
25 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
5908836 |
0 |
0 |
T1 |
509 |
109 |
0 |
0 |
T2 |
486 |
86 |
0 |
0 |
T3 |
481 |
81 |
0 |
0 |
T4 |
666 |
266 |
0 |
0 |
T12 |
747 |
347 |
0 |
0 |
T13 |
523 |
123 |
0 |
0 |
T14 |
412 |
12 |
0 |
0 |
T15 |
423 |
23 |
0 |
0 |
T16 |
1038 |
638 |
0 |
0 |
T17 |
426 |
26 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
1688 |
0 |
0 |
T11 |
30017 |
11 |
0 |
0 |
T21 |
0 |
9 |
0 |
0 |
T30 |
0 |
8 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
9 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T88 |
0 |
26 |
0 |
0 |
T89 |
0 |
7 |
0 |
0 |
T90 |
0 |
14 |
0 |
0 |
T91 |
0 |
13 |
0 |
0 |
T92 |
0 |
25 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
1657 |
0 |
0 |
T11 |
30017 |
11 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T30 |
0 |
8 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
7 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T88 |
0 |
26 |
0 |
0 |
T89 |
0 |
7 |
0 |
0 |
T90 |
0 |
14 |
0 |
0 |
T91 |
0 |
13 |
0 |
0 |
T92 |
0 |
25 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
923 |
0 |
0 |
T11 |
30017 |
3 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T44 |
0 |
22 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
5 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T92 |
0 |
25 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
T124 |
0 |
1 |
0 |
0 |
T199 |
0 |
11 |
0 |
0 |
T328 |
0 |
14 |
0 |
0 |
T329 |
0 |
2 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
923 |
0 |
0 |
T11 |
30017 |
3 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T44 |
0 |
22 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
5 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T92 |
0 |
25 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
T124 |
0 |
1 |
0 |
0 |
T199 |
0 |
11 |
0 |
0 |
T328 |
0 |
14 |
0 |
0 |
T329 |
0 |
2 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
72114 |
0 |
0 |
T11 |
30017 |
1 |
0 |
0 |
T21 |
0 |
454 |
0 |
0 |
T40 |
0 |
122 |
0 |
0 |
T44 |
0 |
1355 |
0 |
0 |
T51 |
1595 |
0 |
0 |
0 |
T56 |
0 |
398 |
0 |
0 |
T58 |
692 |
0 |
0 |
0 |
T59 |
509 |
0 |
0 |
0 |
T60 |
773 |
0 |
0 |
0 |
T75 |
492 |
0 |
0 |
0 |
T84 |
507 |
0 |
0 |
0 |
T92 |
0 |
2490 |
0 |
0 |
T93 |
425 |
0 |
0 |
0 |
T94 |
8443 |
0 |
0 |
0 |
T95 |
448 |
0 |
0 |
0 |
T199 |
0 |
889 |
0 |
0 |
T328 |
0 |
345 |
0 |
0 |
T329 |
0 |
244 |
0 |
0 |
T350 |
0 |
944 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
6367248 |
0 |
0 |
T1 |
509 |
109 |
0 |
0 |
T2 |
486 |
86 |
0 |
0 |
T3 |
481 |
81 |
0 |
0 |
T4 |
666 |
266 |
0 |
0 |
T12 |
747 |
347 |
0 |
0 |
T13 |
523 |
123 |
0 |
0 |
T14 |
412 |
12 |
0 |
0 |
T15 |
423 |
23 |
0 |
0 |
T16 |
1038 |
638 |
0 |
0 |
T17 |
426 |
26 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
6367248 |
0 |
0 |
T1 |
509 |
109 |
0 |
0 |
T2 |
486 |
86 |
0 |
0 |
T3 |
481 |
81 |
0 |
0 |
T4 |
666 |
266 |
0 |
0 |
T12 |
747 |
347 |
0 |
0 |
T13 |
523 |
123 |
0 |
0 |
T14 |
412 |
12 |
0 |
0 |
T15 |
423 |
23 |
0 |
0 |
T16 |
1038 |
638 |
0 |
0 |
T17 |
426 |
26 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
778 |
0 |
0 |
T21 |
7856 |
4 |
0 |
0 |
T32 |
20109 |
0 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
T44 |
0 |
22 |
0 |
0 |
T56 |
0 |
5 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T92 |
0 |
22 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T199 |
0 |
8 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T328 |
0 |
13 |
0 |
0 |
T329 |
0 |
2 |
0 |
0 |
T350 |
0 |
13 |
0 |
0 |
T351 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T11 T21 T32
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T2 T4
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T2 T4
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T2 T4
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T21 T32 T42
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
105 1/1 cnt_q <= '0;
Tests: T1 T2 T4
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T2 T4
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T2 T4
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T4
129 1/1 cnt_en = 1'b0;
Tests: T1 T2 T4
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T2 T4
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T2 T4
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T2 T4
139
140 1/1 unique case (state_q)
Tests: T1 T2 T4
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T2 T4
148 1/1 state_d = DebounceSt;
Tests: T21 T32 T42
149 1/1 cnt_en = 1'b1;
Tests: T21 T32 T42
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T21 T32 T42
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T21 T32 T42
163 1/1 state_d = IdleSt;
Tests: T21 T56
164 1/1 cnt_clr = 1'b1;
Tests: T21 T56
165 1/1 end else if (cnt_done) begin
Tests: T21 T32 T42
166 1/1 cnt_clr = 1'b1;
Tests: T21 T32 T42
167 1/1 if (trigger_active) begin
Tests: T21 T32 T42
168 1/1 state_d = DetectSt;
Tests: T21 T32 T42
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T41 T178 T121
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T21 T32 T42
182 1/1 cnt_en = 1'b1;
Tests: T21 T32 T42
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T21 T32 T42
186 1/1 state_d = IdleSt;
Tests: T21 T56 T121
187 1/1 cnt_clr = 1'b1;
Tests: T21 T56 T121
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T21 T32 T42
191 1/1 state_d = StableSt;
Tests: T21 T32 T42
192 1/1 cnt_clr = 1'b1;
Tests: T21 T32 T42
193 1/1 event_detected_o = 1'b1;
Tests: T21 T32 T42
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T21 T32 T42
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T21 T32 T42
206 1/1 state_d = IdleSt;
Tests: T21 T32 T42
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T21 T32 T42
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
Exclude Annotation: VC_COV_UNR
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
220 1/1 state_q <= IdleSt;
Tests: T1 T2 T4
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T2 T4
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Total | Covered | Percent |
Conditions | 21 | 20 | 95.24 |
Logical | 21 | 20 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T11,T21,T32 |
1 | Covered | T1,T2,T4 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T11,T21,T32 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T21,T32,T42 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T1,T2,T4 |
VC_COV_UNR |
1 | Covered | T21,T32,T42 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T21,T32,T42 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T11,T21,T32 |
1 | 0 | Covered | T28,T11,T51 |
1 | 1 | Covered | T21,T32,T42 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T21,T32,T42 |
0 | 1 | Covered | T121,T185,T352 |
1 | 0 | Covered | T21,T56 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T21,T32,T42 |
0 | 1 | Covered | T21,T32,T42 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T21,T32,T42 |
1 | - | Covered | T21,T32,T42 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| | | |
DebounceSt |
148 |
Covered |
T21,T32,T42 |
DetectSt |
168 |
Covered |
T21,T32,T42 |
IdleSt |
163 |
Covered |
T1,T2,T4 |
StableSt |
191 |
Covered |
T21,T32,T42 |
| | | |
DebounceSt->DetectSt |
168 |
Covered |
T21,T32,T42 |
DebounceSt->IdleSt |
163 |
Covered |
T21,T56,T41 |
DetectSt->IdleSt |
186 |
Covered |
T21,T56,T121 |
DetectSt->StableSt |
191 |
Covered |
T21,T32,T42 |
IdleSt->DebounceSt |
148 |
Covered |
T21,T32,T42 |
StableSt->IdleSt |
206 |
Covered |
T21,T32,T42 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
21 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
11 |
11 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==> (Excluded)
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T21,T32,T42 |
|
0 |
1 |
Covered |
T21,T32,T42 |
|
0 |
0 |
Excluded |
T1,T2,T4 |
VC_COV_UNR |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T21,T32,T42 |
0 |
Covered |
T1,T2,T4 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T21,T32,T42 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T21,T56 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T21,T32,T42 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T41,T178,T121 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T21,T32,T42 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T21,T56,T121 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T21,T32,T42 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T21,T32,T42 |
|
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T21,T32,T42 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T21,T32,T42 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
908 |
0 |
0 |
T21 |
7856 |
8 |
0 |
0 |
T32 |
20109 |
10 |
0 |
0 |
T41 |
0 |
17 |
0 |
0 |
T42 |
0 |
6 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T56 |
0 |
8 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T121 |
0 |
13 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
14 |
0 |
0 |
T178 |
0 |
17 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
49161 |
0 |
0 |
T21 |
7856 |
295 |
0 |
0 |
T32 |
20109 |
405 |
0 |
0 |
T41 |
0 |
867 |
0 |
0 |
T42 |
0 |
207 |
0 |
0 |
T43 |
0 |
482 |
0 |
0 |
T56 |
0 |
235 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T121 |
0 |
811 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
1092 |
0 |
0 |
T178 |
0 |
842 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
127 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
6363942 |
0 |
0 |
T1 |
509 |
108 |
0 |
0 |
T2 |
486 |
85 |
0 |
0 |
T3 |
481 |
80 |
0 |
0 |
T4 |
666 |
265 |
0 |
0 |
T12 |
747 |
346 |
0 |
0 |
T13 |
523 |
122 |
0 |
0 |
T14 |
412 |
11 |
0 |
0 |
T15 |
423 |
22 |
0 |
0 |
T16 |
1038 |
637 |
0 |
0 |
T17 |
426 |
25 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
60 |
0 |
0 |
T100 |
7630 |
0 |
0 |
0 |
T121 |
23409 |
6 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T185 |
0 |
5 |
0 |
0 |
T251 |
12908 |
0 |
0 |
0 |
T252 |
503 |
0 |
0 |
0 |
T253 |
637 |
0 |
0 |
0 |
T254 |
591 |
0 |
0 |
0 |
T255 |
514 |
0 |
0 |
0 |
T256 |
496 |
0 |
0 |
0 |
T257 |
404 |
0 |
0 |
0 |
T258 |
522 |
0 |
0 |
0 |
T330 |
0 |
4 |
0 |
0 |
T346 |
0 |
5 |
0 |
0 |
T349 |
0 |
1 |
0 |
0 |
T352 |
0 |
3 |
0 |
0 |
T353 |
0 |
3 |
0 |
0 |
T354 |
0 |
7 |
0 |
0 |
T355 |
0 |
5 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
16841 |
0 |
0 |
T21 |
7856 |
92 |
0 |
0 |
T32 |
20109 |
339 |
0 |
0 |
T41 |
0 |
624 |
0 |
0 |
T42 |
0 |
27 |
0 |
0 |
T43 |
0 |
49 |
0 |
0 |
T56 |
0 |
99 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
45 |
0 |
0 |
T178 |
0 |
737 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
87 |
0 |
0 |
T318 |
0 |
46 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
362 |
0 |
0 |
T21 |
7856 |
1 |
0 |
0 |
T32 |
20109 |
5 |
0 |
0 |
T41 |
0 |
8 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T178 |
0 |
8 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
1 |
0 |
0 |
T318 |
0 |
5 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
6000952 |
0 |
0 |
T1 |
509 |
108 |
0 |
0 |
T2 |
486 |
85 |
0 |
0 |
T3 |
481 |
80 |
0 |
0 |
T4 |
666 |
265 |
0 |
0 |
T12 |
747 |
346 |
0 |
0 |
T13 |
523 |
122 |
0 |
0 |
T14 |
412 |
11 |
0 |
0 |
T15 |
423 |
22 |
0 |
0 |
T16 |
1038 |
637 |
0 |
0 |
T17 |
426 |
25 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
6002672 |
0 |
0 |
T1 |
509 |
109 |
0 |
0 |
T2 |
486 |
86 |
0 |
0 |
T3 |
481 |
81 |
0 |
0 |
T4 |
666 |
266 |
0 |
0 |
T12 |
747 |
347 |
0 |
0 |
T13 |
523 |
123 |
0 |
0 |
T14 |
412 |
12 |
0 |
0 |
T15 |
423 |
23 |
0 |
0 |
T16 |
1038 |
638 |
0 |
0 |
T17 |
426 |
26 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
482 |
0 |
0 |
T21 |
7856 |
5 |
0 |
0 |
T32 |
20109 |
5 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
6 |
0 |
0 |
T56 |
0 |
5 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T121 |
0 |
7 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T178 |
0 |
9 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
427 |
0 |
0 |
T21 |
7856 |
3 |
0 |
0 |
T32 |
20109 |
5 |
0 |
0 |
T41 |
0 |
8 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T121 |
0 |
6 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T178 |
0 |
8 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
362 |
0 |
0 |
T21 |
7856 |
1 |
0 |
0 |
T32 |
20109 |
5 |
0 |
0 |
T41 |
0 |
8 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T178 |
0 |
8 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
1 |
0 |
0 |
T318 |
0 |
5 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
362 |
0 |
0 |
T21 |
7856 |
1 |
0 |
0 |
T32 |
20109 |
5 |
0 |
0 |
T41 |
0 |
8 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T178 |
0 |
8 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
1 |
0 |
0 |
T318 |
0 |
5 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
16455 |
0 |
0 |
T21 |
7856 |
91 |
0 |
0 |
T32 |
20109 |
334 |
0 |
0 |
T41 |
0 |
616 |
0 |
0 |
T42 |
0 |
24 |
0 |
0 |
T43 |
0 |
45 |
0 |
0 |
T56 |
0 |
98 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
38 |
0 |
0 |
T178 |
0 |
729 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
86 |
0 |
0 |
T318 |
0 |
41 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
6367248 |
0 |
0 |
T1 |
509 |
109 |
0 |
0 |
T2 |
486 |
86 |
0 |
0 |
T3 |
481 |
81 |
0 |
0 |
T4 |
666 |
266 |
0 |
0 |
T12 |
747 |
347 |
0 |
0 |
T13 |
523 |
123 |
0 |
0 |
T14 |
412 |
12 |
0 |
0 |
T15 |
423 |
23 |
0 |
0 |
T16 |
1038 |
638 |
0 |
0 |
T17 |
426 |
26 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7014086 |
336 |
0 |
0 |
T21 |
7856 |
1 |
0 |
0 |
T32 |
20109 |
5 |
0 |
0 |
T41 |
0 |
8 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T72 |
1746 |
0 |
0 |
0 |
T77 |
524 |
0 |
0 |
0 |
T92 |
0 |
4 |
0 |
0 |
T157 |
427 |
0 |
0 |
0 |
T158 |
403 |
0 |
0 |
0 |
T159 |
507 |
0 |
0 |
0 |
T160 |
524 |
0 |
0 |
0 |
T161 |
422 |
0 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T178 |
0 |
8 |
0 |
0 |
T248 |
834 |
0 |
0 |
0 |
T251 |
0 |
1 |
0 |
0 |
T318 |
0 |
5 |
0 |
0 |