Unified Coverage Report :: Module

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00



55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
57         1/1                q <= RESVAL;
           Tests:       T1 T4 T5 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T4 T5 
59         1/1                q <= wr_data;
           Tests:       T1 T4 T5 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T4 T5 
65         1/1            assign qe = wr_en;
           Tests:       T1 T4 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T4 T5

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ec_rst_ctl

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ac_debounce_ctl

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_lid_debounce_ctl

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_debounce_ctl

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T15

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_intr_state

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_pwrb_in

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_key0_in

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_key1_in

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_key2_in

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_lid_open

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_ac_present

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_ec_rst_l

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_pin_in_value_flash_wp_l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ctl

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_in

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_in

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_in

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_in

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_ac_present

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_bat_disable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_lid_open

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_z3_wakeup

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_bat_disable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_ec_rst_l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_pwrb_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key0_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key1_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key2_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_z3_wakeup

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_flash_wp_l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_bat_disable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_ec_rst_l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_pwrb_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key0_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key1_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key2_out

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_z3_wakeup

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_flash_wp_l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_interrupt_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_rst_req_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_interrupt_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_rst_req_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_interrupt_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_rst_req_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_interrupt_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_rst_req_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_status

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_wkup_status

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo0_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo1_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo2_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo3_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_pwrb_in	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_key0_in	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_key1_in	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_key2_in	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_lid_open	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_ac_present	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_ec_rst_l	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_pin_in_value_flash_wp_l	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_intr_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ec_rst_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_status	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wkup_status	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key0_in	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key0_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key1_in	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key1_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key2_in	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key2_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_in	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_ac_present	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_bat_disable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_lid_open	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_bat_disable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_pwrb_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key0_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key1_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key2_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_bat_disable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_ec_rst_l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_pwrb_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key0_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key1_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key2_out	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_z3_wakeup	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_flash_wp_l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_debounce_ctl	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_combo_intr_status_combo0_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_combo_intr_status_combo1_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_combo_intr_status_combo2_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_combo_intr_status_combo3_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_pwrb_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_key0_in_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_key1_in_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_key2_in_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_ac_present_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_pwrb_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_key0_in_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_key1_in_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_key2_in_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_ac_present_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h	100.00	100.00	100.00			100.00