Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T4
60 end
==> MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T4
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T4
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Not Covered |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T4
60 end
==> MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T4
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T4
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Not Covered |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T4
60 end
==> MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T4
65 0/1 ==> assign qe = wr_en;
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T4
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Not Covered |
|
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T3 T51 T45
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T45 T21 T48
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T3 T10 T51
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T3 T8 T51
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T51 T49 T21
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T8 T51 T45
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T10 T51 T49
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T3 T8 T10
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T3 T8 T10
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T3 T8 T10
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T8 T10 T51
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T8 T10 T21
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T8 T45 T21
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T3 T8 T10
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T3 T8 T10
65 1/1 assign qe = wr_en;
Tests: T3 T8 T10
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T3 T10 T51
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T3
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T3
65 1/1 assign qe = wr_en;
Tests: T1 T2 T3
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T4 T27 T28
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T4 T27 T58
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T4 T27 T28
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T4 T27 T28
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T4 T27 T28
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T4 T27 T28
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T4 T27 T28
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T4 T27 T28
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T4 T27 T28
65 1/1 assign qe = wr_en;
Tests: T4 T27 T28
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T28 T58 T60
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T4,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T27,T28 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T4,T27,T28 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T7 T29
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T7 T29
65 1/1 assign qe = wr_en;
Tests: T1 T7 T29
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T89 T91 T44
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T7,T29 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T29 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T7,T29 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T7 T29
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T7 T29
65 1/1 assign qe = wr_en;
Tests: T1 T7 T29
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T56 T88
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T7,T29 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T29 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T7,T29 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T7 T29
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T7 T29
65 1/1 assign qe = wr_en;
Tests: T1 T7 T29
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T21 T40 T56
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T7,T29 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T29 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T7,T29 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T7 T29
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T7 T29
65 1/1 assign qe = wr_en;
Tests: T1 T7 T29
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T7 T29
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T7,T29 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T29 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T7,T29 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T7 T29
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T7 T29
65 1/1 assign qe = wr_en;
Tests: T1 T7 T29
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T30 T88
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T7,T29 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T29 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T7,T29 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T40 T56 T92
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T30 T56 T90
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T89 T91 T134
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T21 T56
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T30 T88
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T30 T56
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T40 T124
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T56 T88 T92
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T88 T89 T91
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T21 T89 T90
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T89 T124
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T21 T30 T56
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T40 T56 T90
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T40 T88 T89
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T21 T30
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T7 T29
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T7 T29
65 1/1 assign qe = wr_en;
Tests: T1 T7 T29
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T7 T29
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T7,T29 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T29 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T7,T29 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T21 T30
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T21 T30
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T11 T21 T30
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T11 T21 T30
65 1/1 assign qe = wr_en;
Tests: T11 T21 T30
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T21 T30
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T11,T21,T30 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T21,T30 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T11,T21,T30 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T31
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T31
65 1/1 assign qe = wr_en;
Tests: T1 T2 T31
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T31
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T31 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T31 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T31 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T31
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T31
65 1/1 assign qe = wr_en;
Tests: T1 T2 T31
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T31
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T31 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T31 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T31 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T31
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T31
65 1/1 assign qe = wr_en;
Tests: T1 T2 T31
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T1 T2 T31
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T31 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T31 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T31 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T31
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T31
65 1/1 assign qe = wr_en;
Tests: T1 T2 T31
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T32 T30 T40
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T31 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T31 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T31 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T1 T2 T31
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T1 T2 T31
65 1/1 assign qe = wr_en;
Tests: T1 T2 T31
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T21 T42 T56
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T31 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T31 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T1,T2,T31 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T6 T11 T21
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T6 T11 T21
65 1/1 assign qe = wr_en;
Tests: T6 T11 T21
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T30 T41 T88
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T6,T11,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T11,T21 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T6,T11,T21 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T6 T11 T21
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T6 T11 T21
65 1/1 assign qe = wr_en;
Tests: T6 T11 T21
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T21 T32
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T6,T11,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T11,T21 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T6,T11,T21 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T6 T11 T21
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T6 T11 T21
65 1/1 assign qe = wr_en;
Tests: T6 T11 T21
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T11 T21 T40
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T6,T11,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T11,T21 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T6,T11,T21 |
0 |
0 |
Covered |
T1,T2,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
55 always_ff @(posedge clk_i or negedge rst_ni) begin
56 1/1 if (!rst_ni) begin
Tests: T1 T2 T4
57 1/1 q <= RESVAL;
Tests: T1 T2 T4
58 1/1 end else if (wr_en) begin
Tests: T1 T2 T4
59 1/1 q <= wr_data;
Tests: T6 T11 T21
60 end
MISSING_ELSE
61 end
62
63 // feed back out for consolidation
64 1/1 assign ds = wr_en ? wr_data : qs;
Tests: T6 T11 T21
65 1/1 assign qe = wr_en;
Tests: T6 T11 T21
66
67 if (SwAccess == SwAccessRC) begin : gen_rc
68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69 // but the register is cleared to 0. See #5416 for a discussion.
70 assign qs = de && we ? d : q;
71 end else begin : gen_no_rc
72 1/1 assign qs = q;
Tests: T32 T174 T178
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T6,T11,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
64 assign ds = wr_en ? wr_data : qs;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T11,T21 |
0 |
Covered |
T1,T2,T4 |
56 if (!rst_ni) begin
-1-
57 q <= RESVAL;
==>
58 end else if (wr_en) begin
-2-
59 q <= wr_data;
==>
60 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T6,T11,T21 |
0 |
0 |
Covered |
T1,T2,T4 |