Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T14 T17 T26
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T14,T17,T26 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T14,T17,T26 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T14,T17,T26 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T14,T17,T26 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T14 T17 T26
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T14,T17,T26 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T14,T17,T26 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T14,T17,T26 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T14,T17,T26 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ac_present.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_ec_rst_l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_flash_wp_l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 1 | 50.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T4 T5
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T3 T7 T11
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T7,T11 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T3,T7,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T11 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T16 T27 T28
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T4 T5
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T16,T27,T28 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T16,T27,T28 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T16,T27,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T27,T28 |
0 |
Covered |
T1,T4,T5 |