| T234 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2623873287 |
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Oct 14 10:14:41 PM UTC 24 |
Oct 14 10:16:36 PM UTC 24 |
67664817912 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1942242555 |
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Oct 14 10:16:31 PM UTC 24 |
Oct 14 10:16:36 PM UTC 24 |
2629092993 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3399631561 |
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Oct 14 10:16:34 PM UTC 24 |
Oct 14 10:16:37 PM UTC 24 |
10322607952 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1422930800 |
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Oct 14 10:16:06 PM UTC 24 |
Oct 14 10:16:38 PM UTC 24 |
5332917723 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1472758382 |
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Oct 14 10:16:33 PM UTC 24 |
Oct 14 10:16:38 PM UTC 24 |
3694485066 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3209741852 |
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Oct 14 10:13:03 PM UTC 24 |
Oct 14 10:16:40 PM UTC 24 |
77378223291 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.441986610 |
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Oct 14 10:16:17 PM UTC 24 |
Oct 14 10:16:41 PM UTC 24 |
4043657195 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1171747483 |
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Oct 14 10:16:33 PM UTC 24 |
Oct 14 10:16:41 PM UTC 24 |
5400364512 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1945412702 |
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Oct 14 10:16:37 PM UTC 24 |
Oct 14 10:16:43 PM UTC 24 |
4890098523 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3255213688 |
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Oct 14 10:15:57 PM UTC 24 |
Oct 14 10:16:43 PM UTC 24 |
513605748306 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.4116431509 |
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Oct 14 10:16:40 PM UTC 24 |
Oct 14 10:16:43 PM UTC 24 |
2157158748 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.51694209 |
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Oct 14 10:15:53 PM UTC 24 |
Oct 14 10:16:46 PM UTC 24 |
84023230938 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3759877698 |
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Oct 14 10:16:41 PM UTC 24 |
Oct 14 10:16:46 PM UTC 24 |
2290143548 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.1308435618 |
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Oct 14 10:16:39 PM UTC 24 |
Oct 14 10:16:46 PM UTC 24 |
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| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3897905880 |
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Oct 14 10:16:44 PM UTC 24 |
Oct 14 10:16:48 PM UTC 24 |
2625262173 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1898273420 |
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Oct 14 10:15:19 PM UTC 24 |
Oct 14 10:16:51 PM UTC 24 |
61601120960 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.4117249117 |
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Oct 14 10:16:43 PM UTC 24 |
Oct 14 10:16:52 PM UTC 24 |
2515087587 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2513952187 |
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Oct 14 10:16:41 PM UTC 24 |
Oct 14 10:16:55 PM UTC 24 |
2446287192 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2999430546 |
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Oct 14 10:16:44 PM UTC 24 |
Oct 14 10:16:58 PM UTC 24 |
2734501244 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2324520492 |
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Oct 14 10:15:35 PM UTC 24 |
Oct 14 10:16:58 PM UTC 24 |
54188318299 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1940625423 |
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Oct 14 10:16:47 PM UTC 24 |
Oct 14 10:16:59 PM UTC 24 |
3367809501 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.404308091 |
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Oct 14 10:16:38 PM UTC 24 |
Oct 14 10:17:00 PM UTC 24 |
7206528905 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.90861389 |
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Oct 14 10:16:47 PM UTC 24 |
Oct 14 10:17:01 PM UTC 24 |
8535259892 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.536459287 |
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Oct 14 10:16:59 PM UTC 24 |
Oct 14 10:17:04 PM UTC 24 |
2129919779 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.272804658 |
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Oct 14 10:15:39 PM UTC 24 |
Oct 14 10:17:04 PM UTC 24 |
99951419397 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.2642343329 |
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Oct 14 10:17:00 PM UTC 24 |
Oct 14 10:17:06 PM UTC 24 |
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| T194 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2601250832 |
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Oct 14 10:16:49 PM UTC 24 |
Oct 14 10:17:06 PM UTC 24 |
2831053100 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.4141508209 |
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Oct 14 10:16:58 PM UTC 24 |
Oct 14 10:17:06 PM UTC 24 |
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| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1269785161 |
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Oct 14 10:17:02 PM UTC 24 |
Oct 14 10:17:07 PM UTC 24 |
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| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.2831242038 |
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Oct 14 10:17:01 PM UTC 24 |
Oct 14 10:17:08 PM UTC 24 |
2269525968 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1252480450 |
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Oct 14 10:17:05 PM UTC 24 |
Oct 14 10:17:09 PM UTC 24 |
3702130905 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1626736218 |
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Oct 14 10:15:01 PM UTC 24 |
Oct 14 10:17:14 PM UTC 24 |
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| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2650171213 |
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Oct 14 10:17:05 PM UTC 24 |
Oct 14 10:17:17 PM UTC 24 |
3502197716 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.936661170 |
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Oct 14 10:17:07 PM UTC 24 |
Oct 14 10:17:18 PM UTC 24 |
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| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.451722147 |
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Oct 14 10:17:03 PM UTC 24 |
Oct 14 10:17:18 PM UTC 24 |
2612186946 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3098797227 |
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Oct 14 10:17:18 PM UTC 24 |
Oct 14 10:17:21 PM UTC 24 |
2557966620 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3621452415 |
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Oct 14 10:17:09 PM UTC 24 |
Oct 14 10:17:21 PM UTC 24 |
8838007393 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1924433995 |
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Oct 14 10:17:19 PM UTC 24 |
Oct 14 10:17:24 PM UTC 24 |
2536902875 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1636543756 |
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Oct 14 10:17:15 PM UTC 24 |
Oct 14 10:17:25 PM UTC 24 |
2111597535 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.4249522773 |
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Oct 14 10:17:07 PM UTC 24 |
Oct 14 10:17:24 PM UTC 24 |
4431432050 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1036848325 |
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Oct 14 10:17:19 PM UTC 24 |
Oct 14 10:17:26 PM UTC 24 |
2094003993 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.2266608986 |
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Oct 14 10:17:13 PM UTC 24 |
Oct 14 10:17:27 PM UTC 24 |
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| T162 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1828158173 |
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Oct 14 10:17:26 PM UTC 24 |
Oct 14 10:17:30 PM UTC 24 |
3351398522 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.767074100 |
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Oct 14 10:17:22 PM UTC 24 |
Oct 14 10:17:30 PM UTC 24 |
3626693942 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.91880092 |
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Oct 14 10:17:25 PM UTC 24 |
Oct 14 10:17:30 PM UTC 24 |
3529427376 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3738461818 |
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Oct 14 10:17:25 PM UTC 24 |
Oct 14 10:17:35 PM UTC 24 |
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| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1060940961 |
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Oct 14 10:17:31 PM UTC 24 |
Oct 14 10:17:36 PM UTC 24 |
2038052514 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1315756721 |
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Oct 14 10:17:21 PM UTC 24 |
Oct 14 10:17:36 PM UTC 24 |
2608329010 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.704895277 |
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Oct 14 10:17:31 PM UTC 24 |
Oct 14 10:17:36 PM UTC 24 |
9536782286 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.3231394391 |
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Oct 14 10:16:34 PM UTC 24 |
Oct 14 10:17:37 PM UTC 24 |
73590156312 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1222775905 |
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Oct 14 10:13:04 PM UTC 24 |
Oct 14 10:17:37 PM UTC 24 |
66952119021 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2324144551 |
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Oct 14 10:17:36 PM UTC 24 |
Oct 14 10:17:41 PM UTC 24 |
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| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.1471223045 |
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Oct 14 10:17:37 PM UTC 24 |
Oct 14 10:17:43 PM UTC 24 |
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| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.2555686903 |
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Oct 14 10:16:19 PM UTC 24 |
Oct 14 10:17:45 PM UTC 24 |
15893314194 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1334716253 |
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Oct 14 10:15:58 PM UTC 24 |
Oct 14 10:17:47 PM UTC 24 |
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| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.3982115125 |
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Oct 14 10:17:37 PM UTC 24 |
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| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.781658643 |
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Oct 14 10:13:10 PM UTC 24 |
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| T136 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2689240317 |
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Oct 14 10:17:31 PM UTC 24 |
Oct 14 10:17:49 PM UTC 24 |
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| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.3934830871 |
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Oct 14 10:17:37 PM UTC 24 |
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| T222 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.186662581 |
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Oct 14 10:16:14 PM UTC 24 |
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| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.581990830 |
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Oct 14 10:17:48 PM UTC 24 |
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| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3198491772 |
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Oct 14 10:17:41 PM UTC 24 |
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| T98 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4035980084 |
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Oct 14 10:17:44 PM UTC 24 |
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| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.680453464 |
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Oct 14 10:17:38 PM UTC 24 |
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| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.1503985605 |
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Oct 14 10:17:50 PM UTC 24 |
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| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.3142655839 |
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Oct 14 10:17:50 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2040366594 |
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Oct 14 10:17:52 PM UTC 24 |
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| T490 |
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Oct 14 10:17:54 PM UTC 24 |
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| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3777067850 |
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Oct 14 10:17:51 PM UTC 24 |
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| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.602375880 |
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Oct 14 10:17:54 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3629423932 |
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Oct 14 10:17:55 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2882516856 |
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Oct 14 10:17:58 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1327671677 |
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Oct 14 10:16:56 PM UTC 24 |
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| T237 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.583564652 |
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Oct 14 10:13:39 PM UTC 24 |
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| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1847016874 |
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Oct 14 10:17:38 PM UTC 24 |
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| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.817940580 |
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Oct 14 10:17:57 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.4269582845 |
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Oct 14 10:18:02 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2135467420 |
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Oct 14 10:17:50 PM UTC 24 |
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| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.204736167 |
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Oct 14 10:18:42 PM UTC 24 |
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2481554360 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.118220849 |
|
|
Oct 14 10:18:02 PM UTC 24 |
Oct 14 10:18:08 PM UTC 24 |
2123780979 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.481438987 |
|
|
Oct 14 10:17:51 PM UTC 24 |
Oct 14 10:18:09 PM UTC 24 |
2475648754 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2906436194 |
|
|
Oct 14 10:16:37 PM UTC 24 |
Oct 14 10:18:10 PM UTC 24 |
72192291164 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.638681141 |
|
|
Oct 14 10:18:07 PM UTC 24 |
Oct 14 10:18:10 PM UTC 24 |
2178273586 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3531148787 |
|
|
Oct 14 10:18:09 PM UTC 24 |
Oct 14 10:18:15 PM UTC 24 |
3684033809 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.4287647286 |
|
|
Oct 14 10:18:04 PM UTC 24 |
Oct 14 10:18:15 PM UTC 24 |
2452166831 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1592404831 |
|
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Oct 14 10:18:00 PM UTC 24 |
Oct 14 10:18:17 PM UTC 24 |
14721453580 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.3115841911 |
|
|
Oct 14 10:18:07 PM UTC 24 |
Oct 14 10:18:19 PM UTC 24 |
2510125464 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.777766779 |
|
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Oct 14 10:18:09 PM UTC 24 |
Oct 14 10:18:20 PM UTC 24 |
3372941528 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.279249554 |
|
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Oct 14 10:18:08 PM UTC 24 |
Oct 14 10:18:20 PM UTC 24 |
2612590629 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4196742745 |
|
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Oct 14 10:18:10 PM UTC 24 |
Oct 14 10:18:22 PM UTC 24 |
7037666275 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1606650238 |
|
|
Oct 14 10:18:11 PM UTC 24 |
Oct 14 10:18:24 PM UTC 24 |
2753500901 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1599405684 |
|
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Oct 14 10:18:21 PM UTC 24 |
Oct 14 10:18:26 PM UTC 24 |
2458765656 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4285848217 |
|
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Oct 14 10:14:29 PM UTC 24 |
Oct 14 10:18:27 PM UTC 24 |
64208556189 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.2223264660 |
|
|
Oct 14 10:18:23 PM UTC 24 |
Oct 14 10:18:27 PM UTC 24 |
2141770453 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.836641904 |
|
|
Oct 14 10:18:21 PM UTC 24 |
Oct 14 10:18:28 PM UTC 24 |
2117673326 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.3990511934 |
|
|
Oct 14 10:18:20 PM UTC 24 |
Oct 14 10:18:29 PM UTC 24 |
2011904351 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.1250808202 |
|
|
Oct 14 10:18:25 PM UTC 24 |
Oct 14 10:18:31 PM UTC 24 |
2529834521 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.310071825 |
|
|
Oct 14 10:13:28 PM UTC 24 |
Oct 14 10:18:32 PM UTC 24 |
77364042703 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3768496487 |
|
|
Oct 14 10:16:52 PM UTC 24 |
Oct 14 10:18:34 PM UTC 24 |
97007166081 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1255587459 |
|
|
Oct 14 10:18:28 PM UTC 24 |
Oct 14 10:18:35 PM UTC 24 |
3317760061 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3206521197 |
|
|
Oct 14 10:18:26 PM UTC 24 |
Oct 14 10:18:36 PM UTC 24 |
2611264706 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2819490778 |
|
|
Oct 14 10:18:37 PM UTC 24 |
Oct 14 10:18:41 PM UTC 24 |
2122701557 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2055355554 |
|
|
Oct 14 10:18:37 PM UTC 24 |
Oct 14 10:18:42 PM UTC 24 |
2038104786 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1291681837 |
|
|
Oct 14 10:18:28 PM UTC 24 |
Oct 14 10:18:42 PM UTC 24 |
8073627275 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2857677027 |
|
|
Oct 14 10:18:32 PM UTC 24 |
Oct 14 10:18:42 PM UTC 24 |
4814062017 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1228650046 |
|
|
Oct 14 10:15:56 PM UTC 24 |
Oct 14 10:18:45 PM UTC 24 |
88331964939 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3857838542 |
|
|
Oct 14 10:18:15 PM UTC 24 |
Oct 14 10:18:48 PM UTC 24 |
5740203089 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1848255547 |
|
|
Oct 14 10:18:35 PM UTC 24 |
Oct 14 10:18:48 PM UTC 24 |
18834571260 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.1422526474 |
|
|
Oct 14 10:14:57 PM UTC 24 |
Oct 14 10:18:50 PM UTC 24 |
139655857877 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.1559247984 |
|
|
Oct 14 10:17:46 PM UTC 24 |
Oct 14 10:18:50 PM UTC 24 |
93958124034 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1211580419 |
|
|
Oct 14 10:18:43 PM UTC 24 |
Oct 14 10:18:51 PM UTC 24 |
2613402810 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.235926139 |
|
|
Oct 14 10:18:42 PM UTC 24 |
Oct 14 10:18:52 PM UTC 24 |
2251156124 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1563452636 |
|
|
Oct 14 10:18:43 PM UTC 24 |
Oct 14 10:18:52 PM UTC 24 |
2516297765 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.311361390 |
|
|
Oct 14 10:18:45 PM UTC 24 |
Oct 14 10:18:54 PM UTC 24 |
2436090374 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.943889211 |
|
|
Oct 14 10:18:27 PM UTC 24 |
Oct 14 10:18:54 PM UTC 24 |
4212726754 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.694141852 |
|
|
Oct 14 10:18:48 PM UTC 24 |
Oct 14 10:18:54 PM UTC 24 |
3340575932 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.2022738815 |
|
|
Oct 14 10:18:51 PM UTC 24 |
Oct 14 10:18:55 PM UTC 24 |
2722549078 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3856702171 |
|
|
Oct 14 10:18:19 PM UTC 24 |
Oct 14 10:18:56 PM UTC 24 |
372968460266 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.3198942949 |
|
|
Oct 14 10:18:53 PM UTC 24 |
Oct 14 10:18:57 PM UTC 24 |
2030096326 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1833139733 |
|
|
Oct 14 10:18:56 PM UTC 24 |
Oct 14 10:19:00 PM UTC 24 |
2536991050 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.340523457 |
|
|
Oct 14 10:14:07 PM UTC 24 |
Oct 14 10:19:02 PM UTC 24 |
97762075781 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2331570645 |
|
|
Oct 14 10:18:55 PM UTC 24 |
Oct 14 10:19:05 PM UTC 24 |
2109837054 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3062180916 |
|
|
Oct 14 10:16:11 PM UTC 24 |
Oct 14 10:19:05 PM UTC 24 |
85656065396 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.2244220536 |
|
|
Oct 14 10:18:55 PM UTC 24 |
Oct 14 10:19:06 PM UTC 24 |
2115022274 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3632171521 |
|
|
Oct 14 10:18:59 PM UTC 24 |
Oct 14 10:19:07 PM UTC 24 |
2773758306 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.749227461 |
|
|
Oct 14 10:19:04 PM UTC 24 |
Oct 14 10:19:07 PM UTC 24 |
5663241968 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.3315527119 |
|
|
Oct 14 10:18:55 PM UTC 24 |
Oct 14 10:19:09 PM UTC 24 |
2447277717 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.406120646 |
|
|
Oct 14 10:20:06 PM UTC 24 |
Oct 14 10:20:10 PM UTC 24 |
13556450527 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4292159886 |
|
|
Oct 14 10:18:57 PM UTC 24 |
Oct 14 10:19:10 PM UTC 24 |
2607439406 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.215349433 |
|
|
Oct 14 10:17:50 PM UTC 24 |
Oct 14 10:19:10 PM UTC 24 |
158820980380 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2807531094 |
|
|
Oct 14 10:18:59 PM UTC 24 |
Oct 14 10:19:10 PM UTC 24 |
3275495104 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.3451291651 |
|
|
Oct 14 10:19:08 PM UTC 24 |
Oct 14 10:19:11 PM UTC 24 |
2178003556 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3563152376 |
|
|
Oct 14 10:12:32 PM UTC 24 |
Oct 14 10:19:16 PM UTC 24 |
139203652343 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2575928101 |
|
|
Oct 14 10:19:08 PM UTC 24 |
Oct 14 10:19:16 PM UTC 24 |
2023832849 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1335321996 |
|
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Oct 14 10:19:11 PM UTC 24 |
Oct 14 10:19:18 PM UTC 24 |
2249521270 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1972700261 |
|
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Oct 14 10:18:49 PM UTC 24 |
Oct 14 10:19:19 PM UTC 24 |
430772492600 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.567611073 |
|
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Oct 14 10:19:09 PM UTC 24 |
Oct 14 10:19:19 PM UTC 24 |
2450093196 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.4281650459 |
|
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Oct 14 10:19:12 PM UTC 24 |
Oct 14 10:19:19 PM UTC 24 |
5019604378 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3312177907 |
|
|
Oct 14 10:19:12 PM UTC 24 |
Oct 14 10:19:20 PM UTC 24 |
2617778589 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3607564651 |
|
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Oct 14 10:19:06 PM UTC 24 |
Oct 14 10:19:21 PM UTC 24 |
19260505812 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.4074256030 |
|
|
Oct 14 10:19:16 PM UTC 24 |
Oct 14 10:19:22 PM UTC 24 |
3688656896 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2487265131 |
|
|
Oct 14 10:19:01 PM UTC 24 |
Oct 14 10:19:23 PM UTC 24 |
12777680646 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.932274848 |
|
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Oct 14 10:19:11 PM UTC 24 |
Oct 14 10:19:24 PM UTC 24 |
2512016291 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3845698118 |
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Oct 14 10:18:53 PM UTC 24 |
Oct 14 10:19:25 PM UTC 24 |
18367587674 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2934535082 |
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Oct 14 10:18:15 PM UTC 24 |
Oct 14 10:19:26 PM UTC 24 |
66270099013 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1790594452 |
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Oct 14 10:19:24 PM UTC 24 |
Oct 14 10:19:28 PM UTC 24 |
2124351041 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.3428724647 |
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Oct 14 10:19:25 PM UTC 24 |
Oct 14 10:19:29 PM UTC 24 |
2044871603 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1673207046 |
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Oct 14 10:18:36 PM UTC 24 |
Oct 14 10:19:29 PM UTC 24 |
74135175624 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.826296859 |
|
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Oct 14 10:19:17 PM UTC 24 |
Oct 14 10:19:31 PM UTC 24 |
4938961386 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.1267829967 |
|
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Oct 14 10:19:26 PM UTC 24 |
Oct 14 10:19:31 PM UTC 24 |
2531613541 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3782572752 |
|
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Oct 14 10:19:30 PM UTC 24 |
Oct 14 10:19:33 PM UTC 24 |
3368336432 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.3048781372 |
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Oct 14 10:19:22 PM UTC 24 |
Oct 14 10:19:35 PM UTC 24 |
2009864744 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.208891474 |
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Oct 14 10:19:27 PM UTC 24 |
Oct 14 10:19:36 PM UTC 24 |
2609530829 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1126752764 |
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Oct 14 10:19:32 PM UTC 24 |
Oct 14 10:19:37 PM UTC 24 |
3241795647 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2312724906 |
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Oct 14 10:19:20 PM UTC 24 |
Oct 14 10:19:37 PM UTC 24 |
12351747467 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.124546670 |
|
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Oct 14 10:19:24 PM UTC 24 |
Oct 14 10:19:37 PM UTC 24 |
2477844836 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2154752891 |
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Oct 14 10:19:29 PM UTC 24 |
Oct 14 10:19:38 PM UTC 24 |
3198289969 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.1821853316 |
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Oct 14 10:19:38 PM UTC 24 |
Oct 14 10:19:41 PM UTC 24 |
2172894702 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1623459347 |
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Oct 14 10:19:20 PM UTC 24 |
Oct 14 10:19:43 PM UTC 24 |
8544274871 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.3665596826 |
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Oct 14 10:19:38 PM UTC 24 |
Oct 14 10:19:43 PM UTC 24 |
2139435278 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.984694034 |
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Oct 14 10:19:20 PM UTC 24 |
Oct 14 10:19:44 PM UTC 24 |
5220753411 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3810325525 |
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Oct 14 10:19:37 PM UTC 24 |
Oct 14 10:19:44 PM UTC 24 |
2020730086 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3881628722 |
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Oct 14 10:19:43 PM UTC 24 |
Oct 14 10:19:48 PM UTC 24 |
3223334768 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1403822498 |
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Oct 14 10:19:42 PM UTC 24 |
Oct 14 10:19:50 PM UTC 24 |
2611906194 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.4278459935 |
|
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Oct 14 10:19:43 PM UTC 24 |
Oct 14 10:19:51 PM UTC 24 |
2876079036 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2062850789 |
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Oct 14 10:16:39 PM UTC 24 |
Oct 14 10:19:51 PM UTC 24 |
134971666204 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.893503880 |
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Oct 14 10:19:38 PM UTC 24 |
Oct 14 10:19:52 PM UTC 24 |
2469967947 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.2318942730 |
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Oct 14 10:19:07 PM UTC 24 |
Oct 14 10:19:53 PM UTC 24 |
514348908075 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3720802883 |
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Oct 14 10:19:49 PM UTC 24 |
Oct 14 10:19:53 PM UTC 24 |
3298333651 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.108452106 |
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Oct 14 10:19:35 PM UTC 24 |
Oct 14 10:19:54 PM UTC 24 |
4200893441 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.193193035 |
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Oct 14 10:19:39 PM UTC 24 |
Oct 14 10:19:55 PM UTC 24 |
2513457373 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3922781095 |
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Oct 14 10:17:49 PM UTC 24 |
Oct 14 10:19:55 PM UTC 24 |
25831488705 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1279870530 |
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Oct 14 10:19:53 PM UTC 24 |
Oct 14 10:19:56 PM UTC 24 |
2101916603 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.200259590 |
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Oct 14 10:19:53 PM UTC 24 |
Oct 14 10:19:58 PM UTC 24 |
2131389463 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.1180268490 |
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Oct 14 10:19:53 PM UTC 24 |
Oct 14 10:19:59 PM UTC 24 |
2467042466 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2730168644 |
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Oct 14 10:19:45 PM UTC 24 |
Oct 14 10:19:59 PM UTC 24 |
4376298561 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2528252318 |
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Oct 14 10:19:55 PM UTC 24 |
Oct 14 10:20:01 PM UTC 24 |
2531135239 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3665825079 |
|
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Oct 14 10:19:56 PM UTC 24 |
Oct 14 10:20:02 PM UTC 24 |
2624232456 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.943980570 |
|
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Oct 14 10:14:45 PM UTC 24 |
Oct 14 10:20:03 PM UTC 24 |
109206227208 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.521506684 |
|
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Oct 14 10:19:52 PM UTC 24 |
Oct 14 10:20:05 PM UTC 24 |
3647461886 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1733903518 |
|
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Oct 14 10:20:00 PM UTC 24 |
Oct 14 10:20:06 PM UTC 24 |
3740824116 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2182863228 |
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Oct 14 10:19:55 PM UTC 24 |
Oct 14 10:20:07 PM UTC 24 |
2190249756 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3343952237 |
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Oct 14 10:20:01 PM UTC 24 |
Oct 14 10:20:07 PM UTC 24 |
2882736647 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1090423210 |
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Oct 14 10:19:35 PM UTC 24 |
Oct 14 10:20:08 PM UTC 24 |
37026307118 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3827608009 |
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Oct 14 10:19:59 PM UTC 24 |
Oct 14 10:20:09 PM UTC 24 |
3514527999 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.2143237241 |
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Oct 14 10:20:06 PM UTC 24 |
Oct 14 10:20:14 PM UTC 24 |
2018546493 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3202170830 |
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Oct 14 10:20:08 PM UTC 24 |
Oct 14 10:20:18 PM UTC 24 |
2461042404 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3408155660 |
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Oct 14 10:20:10 PM UTC 24 |
Oct 14 10:20:18 PM UTC 24 |
2518682147 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.829494471 |
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Oct 14 10:20:08 PM UTC 24 |
Oct 14 10:20:18 PM UTC 24 |
2108787644 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.1825273192 |
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Oct 14 10:13:31 PM UTC 24 |
Oct 14 10:20:21 PM UTC 24 |
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| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2005802020 |
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Oct 14 10:20:09 PM UTC 24 |
Oct 14 10:20:22 PM UTC 24 |
2132524932 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3297714706 |
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Oct 14 10:20:15 PM UTC 24 |
Oct 14 10:20:22 PM UTC 24 |
4275929793 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3861220682 |
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Oct 14 10:20:11 PM UTC 24 |
Oct 14 10:20:24 PM UTC 24 |
2609141385 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1784617522 |
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Oct 14 10:19:18 PM UTC 24 |
Oct 14 10:20:24 PM UTC 24 |
68022118577 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.918759822 |
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Oct 14 10:22:15 PM UTC 24 |
Oct 14 10:23:30 PM UTC 24 |
40324633698 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3435852250 |
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Oct 14 10:20:04 PM UTC 24 |
Oct 14 10:20:25 PM UTC 24 |
6963967830 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.1752037127 |
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Oct 14 10:20:25 PM UTC 24 |
Oct 14 10:20:29 PM UTC 24 |
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| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1018659428 |
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Oct 14 10:20:18 PM UTC 24 |
Oct 14 10:20:29 PM UTC 24 |
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| T332 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3890620846 |
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Oct 14 10:17:07 PM UTC 24 |
Oct 14 10:20:30 PM UTC 24 |
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| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.220679675 |
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Oct 14 10:20:27 PM UTC 24 |
Oct 14 10:20:33 PM UTC 24 |
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| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.4077349169 |
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Oct 14 10:20:30 PM UTC 24 |
Oct 14 10:20:34 PM UTC 24 |
2267391876 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.2159337518 |
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Oct 14 10:19:03 PM UTC 24 |
Oct 14 10:20:35 PM UTC 24 |
106478821439 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1527967183 |
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Oct 14 10:20:18 PM UTC 24 |
Oct 14 10:20:35 PM UTC 24 |
3413793149 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3720349695 |
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Oct 14 10:20:31 PM UTC 24 |
Oct 14 10:20:35 PM UTC 24 |
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| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3429805798 |
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Oct 14 10:20:26 PM UTC 24 |
Oct 14 10:20:38 PM UTC 24 |
2111793216 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2516258182 |
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Oct 14 10:20:30 PM UTC 24 |
Oct 14 10:20:39 PM UTC 24 |
2511004255 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1184054727 |
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Oct 14 10:20:33 PM UTC 24 |
Oct 14 10:20:39 PM UTC 24 |
3612697826 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2497792556 |
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Oct 14 10:14:31 PM UTC 24 |
Oct 14 10:20:39 PM UTC 24 |
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| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2126784728 |
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Oct 14 10:20:34 PM UTC 24 |
Oct 14 10:20:39 PM UTC 24 |
3383255011 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.2061749107 |
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Oct 14 10:19:36 PM UTC 24 |
Oct 14 10:20:39 PM UTC 24 |
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| T208 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3667593714 |
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Oct 14 10:20:23 PM UTC 24 |
Oct 14 10:20:41 PM UTC 24 |
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| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.104480240 |
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Oct 14 10:19:30 PM UTC 24 |
Oct 14 10:20:41 PM UTC 24 |
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| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2143065523 |
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Oct 14 10:20:40 PM UTC 24 |
Oct 14 10:20:45 PM UTC 24 |
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| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.1032602835 |
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Oct 14 10:20:40 PM UTC 24 |
Oct 14 10:20:45 PM UTC 24 |
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| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.3623906994 |
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Oct 14 10:20:41 PM UTC 24 |
Oct 14 10:20:47 PM UTC 24 |
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| T149 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2964071029 |
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Oct 14 10:20:34 PM UTC 24 |
Oct 14 10:20:47 PM UTC 24 |
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| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1985411140 |
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Oct 14 10:20:42 PM UTC 24 |
Oct 14 10:20:47 PM UTC 24 |
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| T255 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.202928468 |
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Oct 14 10:20:19 PM UTC 24 |
Oct 14 10:20:49 PM UTC 24 |
118255779013 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2880503337 |
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Oct 14 10:20:44 PM UTC 24 |
Oct 14 10:20:50 PM UTC 24 |
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| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.863205913 |
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Oct 14 10:20:45 PM UTC 24 |
Oct 14 10:20:51 PM UTC 24 |
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| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.991618653 |
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Oct 14 10:16:47 PM UTC 24 |
Oct 14 10:20:51 PM UTC 24 |
168261127610 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.94584762 |
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Oct 14 10:20:40 PM UTC 24 |
Oct 14 10:20:52 PM UTC 24 |
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| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2201373341 |
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Oct 14 10:20:37 PM UTC 24 |
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| T200 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.235315573 |
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Oct 14 10:20:35 PM UTC 24 |
Oct 14 10:20:53 PM UTC 24 |
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| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2023423568 |
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Oct 14 10:20:48 PM UTC 24 |
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| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.3250073846 |
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Oct 14 10:20:40 PM UTC 24 |
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| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.4018667488 |
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Oct 14 10:20:39 PM UTC 24 |
Oct 14 10:20:56 PM UTC 24 |
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| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.2596372379 |
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Oct 14 10:20:53 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3439333975 |
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Oct 14 10:19:06 PM UTC 24 |
Oct 14 10:20:57 PM UTC 24 |
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| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3999225013 |
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Oct 14 10:20:52 PM UTC 24 |
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| T333 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2813567467 |
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Oct 14 10:20:48 PM UTC 24 |
Oct 14 10:21:00 PM UTC 24 |
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| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.4148697982 |
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Oct 14 10:20:52 PM UTC 24 |
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| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.3242166457 |
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Oct 14 10:19:52 PM UTC 24 |
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Oct 14 10:20:52 PM UTC 24 |
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Oct 14 10:20:56 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2855235422 |
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Oct 14 10:20:58 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.4090379533 |
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Oct 14 10:20:58 PM UTC 24 |
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6643079639 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2263410887 |
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Oct 14 10:21:01 PM UTC 24 |
Oct 14 10:21:05 PM UTC 24 |
2129201465 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3040264624 |
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Oct 14 10:20:54 PM UTC 24 |
Oct 14 10:21:06 PM UTC 24 |
2512016625 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.4209044724 |
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Oct 14 10:21:04 PM UTC 24 |
Oct 14 10:21:09 PM UTC 24 |
2069684509 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.61007107 |
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Oct 14 10:21:06 PM UTC 24 |
Oct 14 10:21:09 PM UTC 24 |
2888373888 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.3473062373 |
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Oct 14 10:21:05 PM UTC 24 |
Oct 14 10:21:10 PM UTC 24 |
2531647100 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.4016845484 |
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Oct 14 10:20:56 PM UTC 24 |
Oct 14 10:21:10 PM UTC 24 |
2612387503 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.1283925837 |
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Oct 14 10:21:01 PM UTC 24 |
Oct 14 10:21:10 PM UTC 24 |
2017980603 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1739901502 |
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Oct 14 10:21:03 PM UTC 24 |
Oct 14 10:21:11 PM UTC 24 |
2475929773 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1410634320 |
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Oct 14 10:21:00 PM UTC 24 |
Oct 14 10:21:11 PM UTC 24 |
5383117814 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3703328156 |
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Oct 14 10:21:00 PM UTC 24 |
Oct 14 10:21:14 PM UTC 24 |
2699001810 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.534596038 |
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Oct 14 10:21:09 PM UTC 24 |
Oct 14 10:21:14 PM UTC 24 |
3711819973 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.1938158993 |
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Oct 14 10:21:12 PM UTC 24 |
Oct 14 10:21:16 PM UTC 24 |
2042695718 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.734295545 |
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Oct 14 10:21:10 PM UTC 24 |
Oct 14 10:21:16 PM UTC 24 |
2957184173 ps |