| T117 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.2221896232 |
|
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Feb 08 10:09:01 AM UTC 25 |
Feb 08 10:09:25 AM UTC 25 |
16833016167 ps |
| T181 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2815861723 |
|
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Feb 08 10:08:31 AM UTC 25 |
Feb 08 10:09:25 AM UTC 25 |
12041877845 ps |
| T182 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3544027090 |
|
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Feb 08 10:09:12 AM UTC 25 |
Feb 08 10:09:26 AM UTC 25 |
4001689029 ps |
| T183 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2551480683 |
|
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Feb 08 10:09:10 AM UTC 25 |
Feb 08 10:09:26 AM UTC 25 |
2615473014 ps |
| T184 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2720698241 |
|
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Feb 08 10:09:21 AM UTC 25 |
Feb 08 10:09:28 AM UTC 25 |
2017078888 ps |
| T185 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3008461222 |
|
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Feb 08 10:06:45 AM UTC 25 |
Feb 08 10:09:28 AM UTC 25 |
45409374385 ps |
| T186 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.3120843443 |
|
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Feb 08 10:09:25 AM UTC 25 |
Feb 08 10:09:29 AM UTC 25 |
2127982768 ps |
| T187 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.1812546434 |
|
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Feb 08 10:09:27 AM UTC 25 |
Feb 08 10:09:30 AM UTC 25 |
2162834539 ps |
| T188 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.1061312965 |
|
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Feb 08 10:09:25 AM UTC 25 |
Feb 08 10:09:31 AM UTC 25 |
2469172253 ps |
| T189 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.3330602536 |
|
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Feb 08 10:09:14 AM UTC 25 |
Feb 08 10:09:33 AM UTC 25 |
3981934362 ps |
| T289 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.3610302612 |
|
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Feb 08 10:10:05 AM UTC 25 |
Feb 08 10:10:15 AM UTC 25 |
2514762755 ps |
| T290 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2295637282 |
|
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Feb 08 10:09:21 AM UTC 25 |
Feb 08 10:09:33 AM UTC 25 |
6839066185 ps |
| T291 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.4076279924 |
|
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Feb 08 10:09:27 AM UTC 25 |
Feb 08 10:09:33 AM UTC 25 |
2529036777 ps |
| T292 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.579021357 |
|
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Feb 08 10:09:29 AM UTC 25 |
Feb 08 10:09:34 AM UTC 25 |
2634505888 ps |
| T134 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1101561055 |
|
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Feb 08 10:08:02 AM UTC 25 |
Feb 08 10:09:35 AM UTC 25 |
98037336566 ps |
| T116 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.36737296 |
|
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Feb 08 10:09:31 AM UTC 25 |
Feb 08 10:09:37 AM UTC 25 |
5796997835 ps |
| T229 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.3900051661 |
|
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Feb 08 10:09:33 AM UTC 25 |
Feb 08 10:09:38 AM UTC 25 |
2562287531 ps |
| T293 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1724855628 |
|
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Feb 08 10:09:37 AM UTC 25 |
Feb 08 10:09:43 AM UTC 25 |
2448550894 ps |
| T294 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.924687832 |
|
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Feb 08 10:09:40 AM UTC 25 |
Feb 08 10:09:44 AM UTC 25 |
2175215433 ps |
| T523 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2612313933 |
|
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Feb 08 10:09:36 AM UTC 25 |
Feb 08 10:09:45 AM UTC 25 |
2110578574 ps |
| T524 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.4190433750 |
|
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Feb 08 10:09:34 AM UTC 25 |
Feb 08 10:09:46 AM UTC 25 |
2008543946 ps |
| T135 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2059427727 |
|
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Feb 08 10:09:30 AM UTC 25 |
Feb 08 10:09:52 AM UTC 25 |
3612458254 ps |
| T525 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.196367583 |
|
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Feb 08 10:09:46 AM UTC 25 |
Feb 08 10:09:52 AM UTC 25 |
2634483850 ps |
| T526 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2367656960 |
|
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Feb 08 10:09:44 AM UTC 25 |
Feb 08 10:09:52 AM UTC 25 |
2512517482 ps |
| T527 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1978846015 |
|
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Feb 08 10:09:47 AM UTC 25 |
Feb 08 10:09:53 AM UTC 25 |
3585409066 ps |
| T362 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1175169097 |
|
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Feb 08 10:07:13 AM UTC 25 |
Feb 08 10:09:56 AM UTC 25 |
152734587273 ps |
| T528 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2771429969 |
|
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Feb 08 10:09:46 AM UTC 25 |
Feb 08 10:09:59 AM UTC 25 |
2839375112 ps |
| T375 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.4211500534 |
|
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Feb 08 10:09:53 AM UTC 25 |
Feb 08 10:10:01 AM UTC 25 |
3667328171 ps |
| T328 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3156760497 |
|
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Feb 08 10:07:39 AM UTC 25 |
Feb 08 10:10:01 AM UTC 25 |
98489078735 ps |
| T529 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2230488820 |
|
|
Feb 08 10:09:34 AM UTC 25 |
Feb 08 10:10:02 AM UTC 25 |
9449935894 ps |
| T363 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3976745428 |
|
|
Feb 08 10:07:26 AM UTC 25 |
Feb 08 10:10:04 AM UTC 25 |
120954014035 ps |
| T305 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.579161467 |
|
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Feb 08 10:09:53 AM UTC 25 |
Feb 08 10:10:06 AM UTC 25 |
3921404631 ps |
| T345 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2439084649 |
|
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Feb 08 10:08:39 AM UTC 25 |
Feb 08 10:10:07 AM UTC 25 |
107569187777 ps |
| T191 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1944847450 |
|
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Feb 08 10:08:03 AM UTC 25 |
Feb 08 10:10:08 AM UTC 25 |
48557547476 ps |
| T195 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1092258034 |
|
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Feb 08 10:10:01 AM UTC 25 |
Feb 08 10:10:08 AM UTC 25 |
2020272598 ps |
| T196 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3080122626 |
|
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Feb 08 10:10:03 AM UTC 25 |
Feb 08 10:10:11 AM UTC 25 |
2467852869 ps |
| T197 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2618540099 |
|
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Feb 08 10:10:02 AM UTC 25 |
Feb 08 10:10:12 AM UTC 25 |
2113630552 ps |
| T198 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.751610260 |
|
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Feb 08 10:10:05 AM UTC 25 |
Feb 08 10:10:12 AM UTC 25 |
2233202097 ps |
| T199 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.681035254 |
|
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Feb 08 10:06:05 AM UTC 25 |
Feb 08 10:10:12 AM UTC 25 |
75478598978 ps |
| T200 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.577975504 |
|
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Feb 08 10:10:07 AM UTC 25 |
Feb 08 10:10:13 AM UTC 25 |
2627522990 ps |
| T127 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.751099421 |
|
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Feb 08 10:09:15 AM UTC 25 |
Feb 08 10:10:14 AM UTC 25 |
68775778271 ps |
| T201 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3898216125 |
|
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Feb 08 10:10:08 AM UTC 25 |
Feb 08 10:10:18 AM UTC 25 |
3704722955 ps |
| T202 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3411307747 |
|
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Feb 08 10:10:16 AM UTC 25 |
Feb 08 10:10:19 AM UTC 25 |
2155488893 ps |
| T327 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1166095728 |
|
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Feb 08 10:07:28 AM UTC 25 |
Feb 08 10:10:20 AM UTC 25 |
47382851701 ps |
| T530 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1126459145 |
|
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Feb 08 10:10:09 AM UTC 25 |
Feb 08 10:10:20 AM UTC 25 |
3630103973 ps |
| T531 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1566484161 |
|
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Feb 08 10:10:00 AM UTC 25 |
Feb 08 10:10:21 AM UTC 25 |
12853301100 ps |
| T203 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1220154891 |
|
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Feb 08 10:10:12 AM UTC 25 |
Feb 08 10:10:24 AM UTC 25 |
3832157123 ps |
| T329 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1863892970 |
|
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Feb 08 10:05:26 AM UTC 25 |
Feb 08 10:10:28 AM UTC 25 |
123667003487 ps |
| T136 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.1103966322 |
|
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Feb 08 10:08:56 AM UTC 25 |
Feb 08 10:10:29 AM UTC 25 |
169075699551 ps |
| T532 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1913717634 |
|
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Feb 08 10:10:14 AM UTC 25 |
Feb 08 10:10:30 AM UTC 25 |
2011009309 ps |
| T533 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.1752560615 |
|
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Feb 08 10:10:20 AM UTC 25 |
Feb 08 10:10:30 AM UTC 25 |
2515362035 ps |
| T534 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.448853713 |
|
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Feb 08 10:10:21 AM UTC 25 |
Feb 08 10:10:30 AM UTC 25 |
2618259806 ps |
| T535 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.446249850 |
|
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Feb 08 10:10:19 AM UTC 25 |
Feb 08 10:10:31 AM UTC 25 |
2211156288 ps |
| T536 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.4192676160 |
|
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Feb 08 10:10:22 AM UTC 25 |
Feb 08 10:10:32 AM UTC 25 |
3978496581 ps |
| T537 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.1212528661 |
|
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Feb 08 10:10:18 AM UTC 25 |
Feb 08 10:10:33 AM UTC 25 |
2473906940 ps |
| T376 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3822179602 |
|
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Feb 08 10:10:25 AM UTC 25 |
Feb 08 10:10:33 AM UTC 25 |
4478972431 ps |
| T538 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.3772798052 |
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Feb 08 10:10:30 AM UTC 25 |
Feb 08 10:10:34 AM UTC 25 |
4864902351 ps |
| T350 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3181496944 |
|
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Feb 08 10:08:58 AM UTC 25 |
Feb 08 10:10:34 AM UTC 25 |
62077930879 ps |
| T539 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.600890602 |
|
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Feb 08 10:10:22 AM UTC 25 |
Feb 08 10:10:38 AM UTC 25 |
2637541984 ps |
| T540 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.476523137 |
|
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Feb 08 10:10:35 AM UTC 25 |
Feb 08 10:10:39 AM UTC 25 |
2563431050 ps |
| T541 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.3702120152 |
|
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Feb 08 10:10:32 AM UTC 25 |
Feb 08 10:10:40 AM UTC 25 |
2012591807 ps |
| T542 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.489828578 |
|
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Feb 08 10:10:35 AM UTC 25 |
Feb 08 10:10:40 AM UTC 25 |
2638152731 ps |
| T543 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.879268137 |
|
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Feb 08 10:10:35 AM UTC 25 |
Feb 08 10:10:41 AM UTC 25 |
2856788577 ps |
| T544 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3237641569 |
|
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Feb 08 10:10:34 AM UTC 25 |
Feb 08 10:10:41 AM UTC 25 |
2075318580 ps |
| T545 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.704654272 |
|
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Feb 08 10:10:32 AM UTC 25 |
Feb 08 10:10:48 AM UTC 25 |
2113416221 ps |
| T546 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.2668431925 |
|
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Feb 08 10:10:33 AM UTC 25 |
Feb 08 10:10:48 AM UTC 25 |
2445915070 ps |
| T351 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2500440447 |
|
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Feb 08 10:08:30 AM UTC 25 |
Feb 08 10:10:49 AM UTC 25 |
47627777774 ps |
| T219 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.239090861 |
|
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Feb 08 10:08:31 AM UTC 25 |
Feb 08 10:10:53 AM UTC 25 |
133301636294 ps |
| T547 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.285400960 |
|
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Feb 08 10:10:49 AM UTC 25 |
Feb 08 10:10:53 AM UTC 25 |
2052149313 ps |
| T548 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3815549915 |
|
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Feb 08 10:10:51 AM UTC 25 |
Feb 08 10:10:57 AM UTC 25 |
2465821422 ps |
| T441 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1558551204 |
|
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Feb 08 10:09:34 AM UTC 25 |
Feb 08 10:10:58 AM UTC 25 |
136693612265 ps |
| T324 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2974392462 |
|
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Feb 08 10:08:43 AM UTC 25 |
Feb 08 10:11:00 AM UTC 25 |
26831879596 ps |
| T249 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2743520730 |
|
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Feb 08 10:08:58 AM UTC 25 |
Feb 08 10:11:01 AM UTC 25 |
40205671072 ps |
| T549 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1166872180 |
|
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Feb 08 10:10:49 AM UTC 25 |
Feb 08 10:11:03 AM UTC 25 |
2108884711 ps |
| T550 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4133768487 |
|
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Feb 08 10:10:54 AM UTC 25 |
Feb 08 10:11:03 AM UTC 25 |
2515422534 ps |
| T222 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.48228088 |
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Feb 08 10:10:41 AM UTC 25 |
Feb 08 10:11:04 AM UTC 25 |
3685991024 ps |
| T551 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1725379792 |
|
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Feb 08 10:10:39 AM UTC 25 |
Feb 08 10:11:05 AM UTC 25 |
65908181758 ps |
| T137 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2533086922 |
|
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Feb 08 10:07:40 AM UTC 25 |
Feb 08 10:11:08 AM UTC 25 |
89569942589 ps |
| T335 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.401134980 |
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Feb 08 10:10:54 AM UTC 25 |
Feb 08 10:11:10 AM UTC 25 |
2225104701 ps |
| T336 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3605437917 |
|
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Feb 08 10:10:59 AM UTC 25 |
Feb 08 10:11:11 AM UTC 25 |
4276061734 ps |
| T337 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3539676231 |
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Feb 08 10:11:02 AM UTC 25 |
Feb 08 10:11:11 AM UTC 25 |
374928710431 ps |
| T338 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.320294091 |
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Feb 08 10:10:58 AM UTC 25 |
Feb 08 10:11:12 AM UTC 25 |
2612832190 ps |
| T339 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.4216589438 |
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Feb 08 10:10:44 AM UTC 25 |
Feb 08 10:11:14 AM UTC 25 |
10402347323 ps |
| T340 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2413190772 |
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Feb 08 10:10:13 AM UTC 25 |
Feb 08 10:11:15 AM UTC 25 |
148157664333 ps |
| T341 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1899017962 |
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Feb 08 10:11:16 AM UTC 25 |
Feb 08 10:11:20 AM UTC 25 |
2650704324 ps |
| T342 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.20998901 |
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Feb 08 10:11:13 AM UTC 25 |
Feb 08 10:11:20 AM UTC 25 |
2159149140 ps |
| T343 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4033607239 |
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Feb 08 10:11:12 AM UTC 25 |
Feb 08 10:11:21 AM UTC 25 |
2453274641 ps |
| T552 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3940834165 |
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Feb 08 10:11:15 AM UTC 25 |
Feb 08 10:11:22 AM UTC 25 |
2519482975 ps |
| T553 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2029281016 |
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Feb 08 10:11:11 AM UTC 25 |
Feb 08 10:11:22 AM UTC 25 |
2012623632 ps |
| T369 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3748408368 |
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Feb 08 10:11:09 AM UTC 25 |
Feb 08 10:11:23 AM UTC 25 |
9061030871 ps |
| T364 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3619098464 |
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Feb 08 10:09:57 AM UTC 25 |
Feb 08 10:11:24 AM UTC 25 |
18114449297 ps |
| T554 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2266524303 |
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Feb 08 10:11:12 AM UTC 25 |
Feb 08 10:11:25 AM UTC 25 |
2109886127 ps |
| T410 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.4005860126 |
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Feb 08 10:07:01 AM UTC 25 |
Feb 08 10:11:26 AM UTC 25 |
170993337108 ps |
| T260 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1693176164 |
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Feb 08 10:11:23 AM UTC 25 |
Feb 08 10:11:27 AM UTC 25 |
3036279839 ps |
| T555 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.399610489 |
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Feb 08 10:11:22 AM UTC 25 |
Feb 08 10:11:27 AM UTC 25 |
4746344268 ps |
| T556 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1140928418 |
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Feb 08 10:07:11 AM UTC 25 |
Feb 08 10:11:28 AM UTC 25 |
306335095244 ps |
| T557 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2360403587 |
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Feb 08 10:11:21 AM UTC 25 |
Feb 08 10:11:29 AM UTC 25 |
3105380491 ps |
| T171 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.904906819 |
|
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Feb 08 10:08:43 AM UTC 25 |
Feb 08 10:11:31 AM UTC 25 |
272213803751 ps |
| T558 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.920606441 |
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Feb 08 10:11:28 AM UTC 25 |
Feb 08 10:11:33 AM UTC 25 |
2132086942 ps |
| T559 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.506863268 |
|
|
Feb 08 10:11:29 AM UTC 25 |
Feb 08 10:11:34 AM UTC 25 |
2267943380 ps |
| T560 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.585172047 |
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Feb 08 10:11:41 AM UTC 25 |
Feb 08 10:11:44 AM UTC 25 |
2162309464 ps |
| T138 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1242478689 |
|
|
Feb 08 10:10:41 AM UTC 25 |
Feb 08 10:11:34 AM UTC 25 |
55051575758 ps |
| T561 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.364966847 |
|
|
Feb 08 10:11:30 AM UTC 25 |
Feb 08 10:11:34 AM UTC 25 |
2548708767 ps |
| T352 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.533213704 |
|
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Feb 08 10:10:29 AM UTC 25 |
Feb 08 10:11:36 AM UTC 25 |
119501606258 ps |
| T139 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1488284828 |
|
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Feb 08 10:09:34 AM UTC 25 |
Feb 08 10:11:38 AM UTC 25 |
162070746147 ps |
| T562 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1090702465 |
|
|
Feb 08 10:11:32 AM UTC 25 |
Feb 08 10:11:39 AM UTC 25 |
2613748985 ps |
| T325 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1658091942 |
|
|
Feb 08 10:09:54 AM UTC 25 |
Feb 08 10:11:39 AM UTC 25 |
29081884038 ps |
| T563 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2453065608 |
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Feb 08 10:11:28 AM UTC 25 |
Feb 08 10:11:40 AM UTC 25 |
2014231162 ps |
| T564 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2116946852 |
|
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Feb 08 10:11:34 AM UTC 25 |
Feb 08 10:11:40 AM UTC 25 |
2936359789 ps |
| T230 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.2389393336 |
|
|
Feb 08 10:11:35 AM UTC 25 |
Feb 08 10:11:40 AM UTC 25 |
2439870942 ps |
| T330 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.402715522 |
|
|
Feb 08 10:11:23 AM UTC 25 |
Feb 08 10:11:41 AM UTC 25 |
33503987780 ps |
| T565 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1994672103 |
|
|
Feb 08 10:10:32 AM UTC 25 |
Feb 08 10:11:42 AM UTC 25 |
21015546088 ps |
| T140 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.4198068302 |
|
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Feb 08 10:06:33 AM UTC 25 |
Feb 08 10:11:45 AM UTC 25 |
166564203115 ps |
| T566 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.345904183 |
|
|
Feb 08 10:11:28 AM UTC 25 |
Feb 08 10:11:45 AM UTC 25 |
2445685402 ps |
| T567 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1647037214 |
|
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Feb 08 10:11:39 AM UTC 25 |
Feb 08 10:11:47 AM UTC 25 |
2021943926 ps |
| T346 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3708650072 |
|
|
Feb 08 10:05:25 AM UTC 25 |
Feb 08 10:11:47 AM UTC 25 |
99839639979 ps |
| T568 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.1526359951 |
|
|
Feb 08 10:11:42 AM UTC 25 |
Feb 08 10:11:47 AM UTC 25 |
2246374844 ps |
| T569 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.810859486 |
|
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Feb 08 10:11:41 AM UTC 25 |
Feb 08 10:11:48 AM UTC 25 |
2469686451 ps |
| T570 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3051551281 |
|
|
Feb 08 10:11:35 AM UTC 25 |
Feb 08 10:11:48 AM UTC 25 |
4940852538 ps |
| T571 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1982040996 |
|
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Feb 08 10:11:21 AM UTC 25 |
Feb 08 10:11:49 AM UTC 25 |
4381519577 ps |
| T572 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3386563513 |
|
|
Feb 08 10:11:43 AM UTC 25 |
Feb 08 10:11:49 AM UTC 25 |
2632722073 ps |
| T573 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2124718456 |
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Feb 08 10:11:35 AM UTC 25 |
Feb 08 10:11:49 AM UTC 25 |
3629145954 ps |
| T574 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2600825762 |
|
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Feb 08 10:11:45 AM UTC 25 |
Feb 08 10:11:50 AM UTC 25 |
3142042454 ps |
| T575 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3152076410 |
|
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Feb 08 10:11:43 AM UTC 25 |
Feb 08 10:11:50 AM UTC 25 |
2522162290 ps |
| T576 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2614625051 |
|
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Feb 08 10:11:49 AM UTC 25 |
Feb 08 10:11:52 AM UTC 25 |
2219032313 ps |
| T577 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.457942829 |
|
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Feb 08 10:11:46 AM UTC 25 |
Feb 08 10:11:53 AM UTC 25 |
3310172280 ps |
| T578 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.261267574 |
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Feb 08 10:11:51 AM UTC 25 |
Feb 08 10:11:54 AM UTC 25 |
2483129993 ps |
| T579 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1945416413 |
|
|
Feb 08 10:11:46 AM UTC 25 |
Feb 08 10:11:55 AM UTC 25 |
9015969974 ps |
| T580 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.2146648725 |
|
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Feb 08 10:11:51 AM UTC 25 |
Feb 08 10:11:56 AM UTC 25 |
2140692533 ps |
| T581 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.11601288 |
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Feb 08 10:11:49 AM UTC 25 |
Feb 08 10:11:56 AM UTC 25 |
2020827581 ps |
| T231 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3137151281 |
|
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Feb 08 10:11:47 AM UTC 25 |
Feb 08 10:11:56 AM UTC 25 |
2805867084 ps |
| T233 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1566268532 |
|
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Feb 08 10:11:54 AM UTC 25 |
Feb 08 10:12:01 AM UTC 25 |
2614902838 ps |
| T234 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1499996445 |
|
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Feb 08 10:11:57 AM UTC 25 |
Feb 08 10:12:02 AM UTC 25 |
3266190432 ps |
| T235 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.2398735125 |
|
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Feb 08 10:11:39 AM UTC 25 |
Feb 08 10:12:03 AM UTC 25 |
14412389462 ps |
| T236 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1358658473 |
|
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Feb 08 10:11:55 AM UTC 25 |
Feb 08 10:12:04 AM UTC 25 |
8976554890 ps |
| T237 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3238455264 |
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Feb 08 10:11:52 AM UTC 25 |
Feb 08 10:12:04 AM UTC 25 |
2510790451 ps |
| T238 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2549136417 |
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Feb 08 10:09:14 AM UTC 25 |
Feb 08 10:12:05 AM UTC 25 |
95997312840 ps |
| T239 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2006057288 |
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Feb 08 10:12:03 AM UTC 25 |
Feb 08 10:12:08 AM UTC 25 |
2037605958 ps |
| T240 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3564088267 |
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Feb 08 10:11:55 AM UTC 25 |
Feb 08 10:12:10 AM UTC 25 |
3702013968 ps |
| T241 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1166547564 |
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Feb 08 10:12:04 AM UTC 25 |
Feb 08 10:12:12 AM UTC 25 |
2469842857 ps |
| T582 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1503719203 |
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Feb 08 10:11:54 AM UTC 25 |
Feb 08 10:12:12 AM UTC 25 |
2807839231 ps |
| T583 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.2942641832 |
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Feb 08 10:12:48 AM UTC 25 |
Feb 08 10:12:54 AM UTC 25 |
2538181419 ps |
| T204 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.563978863 |
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Feb 08 10:10:13 AM UTC 25 |
Feb 08 10:12:13 AM UTC 25 |
40265017779 ps |
| T584 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.697460875 |
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Feb 08 10:12:05 AM UTC 25 |
Feb 08 10:12:13 AM UTC 25 |
2521928932 ps |
| T467 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.66087397 |
|
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Feb 08 10:09:14 AM UTC 25 |
Feb 08 10:12:15 AM UTC 25 |
38347689674 ps |
| T141 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.887546292 |
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Feb 08 10:12:10 AM UTC 25 |
Feb 08 10:12:15 AM UTC 25 |
3779234371 ps |
| T469 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.233951565 |
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Feb 08 10:10:12 AM UTC 25 |
Feb 08 10:12:16 AM UTC 25 |
55587170702 ps |
| T585 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.911191085 |
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Feb 08 10:12:00 AM UTC 25 |
Feb 08 10:12:16 AM UTC 25 |
9198228860 ps |
| T586 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.613964180 |
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Feb 08 10:12:05 AM UTC 25 |
Feb 08 10:12:16 AM UTC 25 |
2166622880 ps |
| T451 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3162261919 |
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Feb 08 10:11:05 AM UTC 25 |
Feb 08 10:12:19 AM UTC 25 |
86707689871 ps |
| T587 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.495733538 |
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Feb 08 10:12:04 AM UTC 25 |
Feb 08 10:12:19 AM UTC 25 |
2107560975 ps |
| T588 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3928001080 |
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Feb 08 10:12:17 AM UTC 25 |
Feb 08 10:12:20 AM UTC 25 |
2160238639 ps |
| T589 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3475862989 |
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Feb 08 10:12:06 AM UTC 25 |
Feb 08 10:12:21 AM UTC 25 |
2610432898 ps |
| T590 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1879462164 |
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Feb 08 10:12:17 AM UTC 25 |
Feb 08 10:12:22 AM UTC 25 |
2115696738 ps |
| T591 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1502299807 |
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Feb 08 10:12:17 AM UTC 25 |
Feb 08 10:12:23 AM UTC 25 |
2489094418 ps |
| T205 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.2943140654 |
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Feb 08 10:12:13 AM UTC 25 |
Feb 08 10:12:24 AM UTC 25 |
3597499894 ps |
| T592 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3386663835 |
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Feb 08 10:12:20 AM UTC 25 |
Feb 08 10:12:25 AM UTC 25 |
2633629901 ps |
| T223 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1731640921 |
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Feb 08 10:12:15 AM UTC 25 |
Feb 08 10:12:26 AM UTC 25 |
11700281003 ps |
| T593 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.783755480 |
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Feb 08 10:12:20 AM UTC 25 |
Feb 08 10:12:27 AM UTC 25 |
3573457638 ps |
| T407 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3661562224 |
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Feb 08 10:04:08 AM UTC 25 |
Feb 08 10:12:28 AM UTC 25 |
164590292915 ps |
| T594 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2282987385 |
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Feb 08 10:12:21 AM UTC 25 |
Feb 08 10:12:28 AM UTC 25 |
3184169210 ps |
| T595 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2902208333 |
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Feb 08 10:12:24 AM UTC 25 |
Feb 08 10:12:29 AM UTC 25 |
4582655409 ps |
| T596 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.1033120751 |
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Feb 08 10:12:55 AM UTC 25 |
Feb 08 10:13:03 AM UTC 25 |
2022995446 ps |
| T597 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.607069501 |
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Feb 08 10:12:19 AM UTC 25 |
Feb 08 10:12:31 AM UTC 25 |
2511614202 ps |
| T598 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.204748412 |
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Feb 08 10:12:17 AM UTC 25 |
Feb 08 10:12:32 AM UTC 25 |
2111328958 ps |
| T321 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4064830166 |
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Feb 08 10:11:05 AM UTC 25 |
Feb 08 10:12:36 AM UTC 25 |
29834577754 ps |
| T599 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3328585123 |
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Feb 08 10:12:29 AM UTC 25 |
Feb 08 10:12:36 AM UTC 25 |
2115329529 ps |
| T600 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2602561532 |
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Feb 08 10:12:29 AM UTC 25 |
Feb 08 10:12:38 AM UTC 25 |
2463692031 ps |
| T601 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3669551316 |
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Feb 08 10:12:29 AM UTC 25 |
Feb 08 10:12:38 AM UTC 25 |
2023292511 ps |
| T602 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3472404751 |
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Feb 08 10:12:33 AM UTC 25 |
Feb 08 10:12:39 AM UTC 25 |
2628345916 ps |
| T603 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2036055191 |
|
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Feb 08 10:12:30 AM UTC 25 |
Feb 08 10:12:39 AM UTC 25 |
2231057596 ps |
| T453 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3390703204 |
|
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Feb 08 10:09:53 AM UTC 25 |
Feb 08 10:12:39 AM UTC 25 |
112026947437 ps |
| T604 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2140799564 |
|
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Feb 08 10:12:32 AM UTC 25 |
Feb 08 10:12:41 AM UTC 25 |
2519448082 ps |
| T605 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.44251706 |
|
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Feb 08 10:12:37 AM UTC 25 |
Feb 08 10:12:41 AM UTC 25 |
3342828213 ps |
| T206 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2835689755 |
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Feb 08 10:11:38 AM UTC 25 |
Feb 08 10:12:41 AM UTC 25 |
56049164434 ps |
| T606 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1713469382 |
|
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Feb 08 10:12:36 AM UTC 25 |
Feb 08 10:12:41 AM UTC 25 |
2937560340 ps |
| T207 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.97943629 |
|
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Feb 08 10:12:38 AM UTC 25 |
Feb 08 10:12:43 AM UTC 25 |
5337779238 ps |
| T208 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.4135713105 |
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Feb 08 10:12:40 AM UTC 25 |
Feb 08 10:12:46 AM UTC 25 |
10468152049 ps |
| T272 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3612463776 |
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Feb 08 10:08:07 AM UTC 25 |
Feb 08 10:12:47 AM UTC 25 |
174590505009 ps |
| T273 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.2457983488 |
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Feb 08 10:12:42 AM UTC 25 |
Feb 08 10:12:47 AM UTC 25 |
2033714260 ps |
| T274 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.250160691 |
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Feb 08 10:11:03 AM UTC 25 |
Feb 08 10:12:47 AM UTC 25 |
86138024910 ps |
| T275 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.850087366 |
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Feb 08 10:12:42 AM UTC 25 |
Feb 08 10:12:47 AM UTC 25 |
2136802195 ps |
| T276 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.248529203 |
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Feb 08 10:12:42 AM UTC 25 |
Feb 08 10:12:47 AM UTC 25 |
2083240332 ps |
| T277 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.725160209 |
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Feb 08 10:12:44 AM UTC 25 |
Feb 08 10:12:48 AM UTC 25 |
2529038071 ps |
| T278 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.2404514861 |
|
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Feb 08 10:12:42 AM UTC 25 |
Feb 08 10:12:50 AM UTC 25 |
2453067713 ps |
| T279 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2888824102 |
|
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Feb 08 10:11:48 AM UTC 25 |
Feb 08 10:12:56 AM UTC 25 |
36111319918 ps |
| T280 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1522486849 |
|
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Feb 08 10:12:48 AM UTC 25 |
Feb 08 10:12:57 AM UTC 25 |
2988435819 ps |
| T281 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1200701670 |
|
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Feb 08 10:12:47 AM UTC 25 |
Feb 08 10:13:01 AM UTC 25 |
2598671145 ps |
| T353 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2863610799 |
|
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Feb 08 10:08:28 AM UTC 25 |
Feb 08 10:13:03 AM UTC 25 |
84109944474 ps |
| T607 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.1630706215 |
|
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Feb 08 10:12:57 AM UTC 25 |
Feb 08 10:13:03 AM UTC 25 |
2115839739 ps |
| T608 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3308044449 |
|
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Feb 08 10:13:00 AM UTC 25 |
Feb 08 10:13:04 AM UTC 25 |
2544419463 ps |
| T609 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1920201161 |
|
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Feb 08 10:12:47 AM UTC 25 |
Feb 08 10:13:04 AM UTC 25 |
2611763129 ps |
| T610 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.844637016 |
|
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Feb 08 10:13:00 AM UTC 25 |
Feb 08 10:13:05 AM UTC 25 |
2215454228 ps |
| T611 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.868750970 |
|
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Feb 08 10:12:57 AM UTC 25 |
Feb 08 10:13:05 AM UTC 25 |
2487455025 ps |
| T259 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3720636564 |
|
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Feb 08 10:11:49 AM UTC 25 |
Feb 08 10:13:05 AM UTC 25 |
29058436353 ps |
| T612 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2369061665 |
|
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Feb 08 10:12:27 AM UTC 25 |
Feb 08 10:13:07 AM UTC 25 |
12707681091 ps |
| T613 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1515795761 |
|
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Feb 08 10:13:03 AM UTC 25 |
Feb 08 10:13:09 AM UTC 25 |
3556571460 ps |
| T614 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1339908537 |
|
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Feb 08 10:13:03 AM UTC 25 |
Feb 08 10:13:10 AM UTC 25 |
8282697810 ps |
| T615 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3208632711 |
|
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Feb 08 10:13:02 AM UTC 25 |
Feb 08 10:13:11 AM UTC 25 |
2620734192 ps |
| T616 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2561158658 |
|
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Feb 08 10:13:03 AM UTC 25 |
Feb 08 10:13:11 AM UTC 25 |
4373122501 ps |
| T617 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2821443045 |
|
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Feb 08 10:13:08 AM UTC 25 |
Feb 08 10:13:13 AM UTC 25 |
2039167269 ps |
| T618 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.4234799282 |
|
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Feb 08 10:13:10 AM UTC 25 |
Feb 08 10:13:13 AM UTC 25 |
2153055225 ps |
| T619 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3358897539 |
|
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Feb 08 10:11:57 AM UTC 25 |
Feb 08 10:13:15 AM UTC 25 |
18406978640 ps |
| T620 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3192143002 |
|
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Feb 08 10:13:13 AM UTC 25 |
Feb 08 10:13:17 AM UTC 25 |
2643707863 ps |
| T224 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.4294197035 |
|
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Feb 08 10:13:06 AM UTC 25 |
Feb 08 10:13:19 AM UTC 25 |
3375345412 ps |
| T621 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.568868015 |
|
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Feb 08 10:13:10 AM UTC 25 |
Feb 08 10:13:19 AM UTC 25 |
2464871373 ps |
| T622 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1226592694 |
|
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Feb 08 10:13:15 AM UTC 25 |
Feb 08 10:13:22 AM UTC 25 |
3231654571 ps |
| T623 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.149079156 |
|
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Feb 08 10:13:18 AM UTC 25 |
Feb 08 10:13:22 AM UTC 25 |
2560699589 ps |
| T624 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3894784702 |
|
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Feb 08 10:13:14 AM UTC 25 |
Feb 08 10:13:22 AM UTC 25 |
4176496395 ps |
| T431 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.4139842874 |
|
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Feb 08 10:10:13 AM UTC 25 |
Feb 08 10:13:22 AM UTC 25 |
168983042561 ps |
| T209 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2111182076 |
|
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Feb 08 10:13:20 AM UTC 25 |
Feb 08 10:13:23 AM UTC 25 |
4879223923 ps |
| T288 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1521918057 |
|
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Feb 08 10:12:14 AM UTC 25 |
Feb 08 10:13:23 AM UTC 25 |
26823133291 ps |
| T365 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1574445950 |
|
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Feb 08 10:10:42 AM UTC 25 |
Feb 08 10:13:24 AM UTC 25 |
580809488421 ps |
| T625 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.264835964 |
|
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Feb 08 10:13:12 AM UTC 25 |
Feb 08 10:13:24 AM UTC 25 |
2212754507 ps |
| T326 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1867529180 |
|
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Feb 08 10:07:50 AM UTC 25 |
Feb 08 10:13:25 AM UTC 25 |
113808934320 ps |
| T626 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.4283195214 |
|
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Feb 08 10:13:12 AM UTC 25 |
Feb 08 10:13:27 AM UTC 25 |
2511647721 ps |
| T120 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2149022556 |
|
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Feb 08 10:11:37 AM UTC 25 |
Feb 08 10:13:27 AM UTC 25 |
25078195076 ps |
| T627 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.813546451 |
|
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Feb 08 10:13:24 AM UTC 25 |
Feb 08 10:13:28 AM UTC 25 |
7501434774 ps |
| T628 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.674546117 |
|
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Feb 08 10:13:25 AM UTC 25 |
Feb 08 10:13:28 AM UTC 25 |
2351236189 ps |
| T629 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.629242584 |
|
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Feb 08 10:13:25 AM UTC 25 |
Feb 08 10:13:30 AM UTC 25 |
2541112095 ps |
| T630 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1932246121 |
|
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Feb 08 10:13:24 AM UTC 25 |
Feb 08 10:13:31 AM UTC 25 |
2113253579 ps |
| T631 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.629858128 |
|
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Feb 08 10:13:24 AM UTC 25 |
Feb 08 10:13:31 AM UTC 25 |
2012172260 ps |
| T632 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.422460844 |
|
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Feb 08 10:10:30 AM UTC 25 |
Feb 08 10:13:31 AM UTC 25 |
56808484360 ps |
| T633 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1646412412 |
|
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Feb 08 10:13:25 AM UTC 25 |
Feb 08 10:13:33 AM UTC 25 |
2618381731 ps |
| T118 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.531026256 |
|
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Feb 08 10:12:13 AM UTC 25 |
Feb 08 10:13:34 AM UTC 25 |
216557305167 ps |
| T634 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3887101619 |
|
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Feb 08 10:13:27 AM UTC 25 |
Feb 08 10:13:34 AM UTC 25 |
3538843604 ps |
| T635 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3692627171 |
|
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Feb 08 10:13:26 AM UTC 25 |
Feb 08 10:13:34 AM UTC 25 |
4267901690 ps |
| T476 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.2495919529 |
|
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Feb 08 10:11:04 AM UTC 25 |
Feb 08 10:13:34 AM UTC 25 |
50730943721 ps |
| T261 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.264116098 |
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Feb 08 10:14:36 AM UTC 25 |
Feb 08 10:14:51 AM UTC 25 |
11630515026 ps |
| T262 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.220435998 |
|
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Feb 08 10:12:22 AM UTC 25 |
Feb 08 10:13:35 AM UTC 25 |
1129740029019 ps |
| T263 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3260968360 |
|
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Feb 08 10:13:25 AM UTC 25 |
Feb 08 10:13:36 AM UTC 25 |
2475313444 ps |
| T264 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.673937490 |
|
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Feb 08 10:13:29 AM UTC 25 |
Feb 08 10:13:36 AM UTC 25 |
4562994472 ps |
| T265 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.874853700 |
|
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Feb 08 10:11:57 AM UTC 25 |
Feb 08 10:13:37 AM UTC 25 |
46875804868 ps |
| T266 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2990027439 |
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Feb 08 10:13:33 AM UTC 25 |
Feb 08 10:13:37 AM UTC 25 |
2090792280 ps |
| T267 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1265143502 |
|
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Feb 08 10:13:34 AM UTC 25 |
Feb 08 10:13:38 AM UTC 25 |
2512611681 ps |
| T268 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1603400618 |
|
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Feb 08 10:13:34 AM UTC 25 |
Feb 08 10:13:39 AM UTC 25 |
2128730985 ps |
| T269 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3048470299 |
|
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Feb 08 10:13:27 AM UTC 25 |
Feb 08 10:13:40 AM UTC 25 |
3149909252 ps |
| T270 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3462164367 |
|
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Feb 08 10:13:07 AM UTC 25 |
Feb 08 10:13:41 AM UTC 25 |
12628636972 ps |
| T636 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2411326836 |
|
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Feb 08 10:13:35 AM UTC 25 |
Feb 08 10:13:41 AM UTC 25 |
2633822173 ps |
| T637 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.365879344 |
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Feb 08 10:13:35 AM UTC 25 |
Feb 08 10:13:41 AM UTC 25 |
2523822990 ps |
| T638 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4257279206 |
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Feb 08 10:13:37 AM UTC 25 |
Feb 08 10:13:42 AM UTC 25 |
8364077044 ps |
| T639 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.737363326 |
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Feb 08 10:13:37 AM UTC 25 |
Feb 08 10:13:42 AM UTC 25 |
3685021355 ps |
| T640 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.372801668 |
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Feb 08 10:13:35 AM UTC 25 |
Feb 08 10:13:44 AM UTC 25 |
2091044712 ps |
| T250 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.793697435 |
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Feb 08 10:13:38 AM UTC 25 |
Feb 08 10:13:47 AM UTC 25 |
3700384136 ps |
| T641 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3192673108 |
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Feb 08 10:13:42 AM UTC 25 |
Feb 08 10:13:48 AM UTC 25 |
2100423602 ps |
| T642 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.1106495323 |
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Feb 08 10:13:42 AM UTC 25 |
Feb 08 10:13:48 AM UTC 25 |
2124792074 ps |
| T643 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1777417000 |
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Feb 08 10:13:43 AM UTC 25 |
Feb 08 10:13:49 AM UTC 25 |
2638718212 ps |
| T644 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1817754325 |
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Feb 08 10:13:43 AM UTC 25 |
Feb 08 10:13:49 AM UTC 25 |
2523160077 ps |
| T645 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3088765035 |
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Feb 08 10:13:35 AM UTC 25 |
Feb 08 10:13:51 AM UTC 25 |
3694766984 ps |
| T646 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2726367570 |
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Feb 08 10:13:40 AM UTC 25 |
Feb 08 10:13:52 AM UTC 25 |
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