| T647 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.773132793 |
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Feb 08 10:13:44 AM UTC 25 |
Feb 08 10:13:52 AM UTC 25 |
5164980995 ps |
| T142 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3503185190 |
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Feb 08 10:12:26 AM UTC 25 |
Feb 08 10:13:53 AM UTC 25 |
565502278173 ps |
| T648 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.163872211 |
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Feb 08 10:12:37 AM UTC 25 |
Feb 08 10:13:54 AM UTC 25 |
1284892009548 ps |
| T649 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2324696026 |
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Feb 08 10:13:45 AM UTC 25 |
Feb 08 10:13:56 AM UTC 25 |
3295563284 ps |
| T650 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3746294507 |
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Feb 08 10:13:52 AM UTC 25 |
Feb 08 10:13:56 AM UTC 25 |
2052507264 ps |
| T651 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3514454396 |
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Feb 08 10:13:42 AM UTC 25 |
Feb 08 10:13:58 AM UTC 25 |
2450393433 ps |
| T454 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2757431536 |
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Feb 08 10:13:40 AM UTC 25 |
Feb 08 10:14:50 AM UTC 25 |
86313282018 ps |
| T652 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1651060357 |
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Feb 08 10:11:01 AM UTC 25 |
Feb 08 10:13:59 AM UTC 25 |
172253142611 ps |
| T653 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3541391496 |
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Feb 08 10:13:53 AM UTC 25 |
Feb 08 10:13:59 AM UTC 25 |
2467970940 ps |
| T654 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.3438236517 |
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Feb 08 10:13:53 AM UTC 25 |
Feb 08 10:14:00 AM UTC 25 |
2085614000 ps |
| T655 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.1101138658 |
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Feb 08 10:13:50 AM UTC 25 |
Feb 08 10:14:00 AM UTC 25 |
10889546247 ps |
| T119 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3373876246 |
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Feb 08 10:13:47 AM UTC 25 |
Feb 08 10:14:01 AM UTC 25 |
7991380120 ps |
| T656 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.251071730 |
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Feb 08 10:13:55 AM UTC 25 |
Feb 08 10:14:02 AM UTC 25 |
2531614138 ps |
| T657 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.3708001819 |
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Feb 08 10:13:49 AM UTC 25 |
Feb 08 10:14:02 AM UTC 25 |
4271458898 ps |
| T658 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3581930171 |
|
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Feb 08 10:13:56 AM UTC 25 |
Feb 08 10:14:04 AM UTC 25 |
2612746541 ps |
| T659 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2844955033 |
|
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Feb 08 10:13:53 AM UTC 25 |
Feb 08 10:14:05 AM UTC 25 |
2109326515 ps |
| T354 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1998775318 |
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Feb 08 10:11:35 AM UTC 25 |
Feb 08 10:14:06 AM UTC 25 |
97301950750 ps |
| T660 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2147302025 |
|
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Feb 08 10:12:52 AM UTC 25 |
Feb 08 10:14:07 AM UTC 25 |
17078674399 ps |
| T661 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2366705896 |
|
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Feb 08 10:14:03 AM UTC 25 |
Feb 08 10:14:10 AM UTC 25 |
2013219455 ps |
| T442 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.4044537976 |
|
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Feb 08 10:13:23 AM UTC 25 |
Feb 08 10:14:13 AM UTC 25 |
42768286482 ps |
| T662 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2268953705 |
|
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Feb 08 10:14:00 AM UTC 25 |
Feb 08 10:14:13 AM UTC 25 |
9310794923 ps |
| T663 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2031057218 |
|
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Feb 08 10:14:06 AM UTC 25 |
Feb 08 10:14:13 AM UTC 25 |
2036156021 ps |
| T473 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2657949315 |
|
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Feb 08 10:12:49 AM UTC 25 |
Feb 08 10:14:14 AM UTC 25 |
42427820198 ps |
| T664 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3284964121 |
|
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Feb 08 10:14:05 AM UTC 25 |
Feb 08 10:14:14 AM UTC 25 |
2459904105 ps |
| T665 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.3824040697 |
|
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Feb 08 10:14:04 AM UTC 25 |
Feb 08 10:14:14 AM UTC 25 |
2109943485 ps |
| T666 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.202265181 |
|
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Feb 08 10:12:24 AM UTC 25 |
Feb 08 10:14:14 AM UTC 25 |
25327880441 ps |
| T366 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1229529253 |
|
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Feb 08 10:14:02 AM UTC 25 |
Feb 08 10:14:15 AM UTC 25 |
7744538050 ps |
| T667 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2490057231 |
|
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Feb 08 10:14:11 AM UTC 25 |
Feb 08 10:14:16 AM UTC 25 |
2635537119 ps |
| T420 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2901788275 |
|
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Feb 08 10:13:31 AM UTC 25 |
Feb 08 10:14:17 AM UTC 25 |
51554679887 ps |
| T668 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.736036829 |
|
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Feb 08 10:14:08 AM UTC 25 |
Feb 08 10:14:18 AM UTC 25 |
2509895402 ps |
| T271 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.286388898 |
|
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Feb 08 10:14:02 AM UTC 25 |
Feb 08 10:14:22 AM UTC 25 |
4899584722 ps |
| T669 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3494390751 |
|
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Feb 08 10:14:18 AM UTC 25 |
Feb 08 10:14:23 AM UTC 25 |
2134686083 ps |
| T470 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4264533188 |
|
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Feb 08 10:13:38 AM UTC 25 |
Feb 08 10:14:24 AM UTC 25 |
28841327903 ps |
| T670 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3190321470 |
|
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Feb 08 10:14:14 AM UTC 25 |
Feb 08 10:14:24 AM UTC 25 |
3189121172 ps |
| T671 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1081228422 |
|
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Feb 08 10:14:15 AM UTC 25 |
Feb 08 10:14:24 AM UTC 25 |
2945338167 ps |
| T180 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.606151105 |
|
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Feb 08 10:13:32 AM UTC 25 |
Feb 08 10:14:25 AM UTC 25 |
665237771785 ps |
| T296 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.3475788601 |
|
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Feb 08 10:14:21 AM UTC 25 |
Feb 08 10:14:25 AM UTC 25 |
2125985012 ps |
| T297 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1469764401 |
|
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Feb 08 10:10:40 AM UTC 25 |
Feb 08 10:14:26 AM UTC 25 |
147569747095 ps |
| T298 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.3069145764 |
|
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Feb 08 10:14:22 AM UTC 25 |
Feb 08 10:14:26 AM UTC 25 |
2546429944 ps |
| T299 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2897550048 |
|
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Feb 08 10:14:17 AM UTC 25 |
Feb 08 10:14:27 AM UTC 25 |
2011092590 ps |
| T300 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3992299416 |
|
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Feb 08 10:13:58 AM UTC 25 |
Feb 08 10:14:27 AM UTC 25 |
4696967247 ps |
| T301 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.345661609 |
|
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Feb 08 10:08:01 AM UTC 25 |
Feb 08 10:14:28 AM UTC 25 |
138357413914 ps |
| T302 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1419436703 |
|
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Feb 08 10:14:19 AM UTC 25 |
Feb 08 10:14:28 AM UTC 25 |
2460505132 ps |
| T303 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2551141865 |
|
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Feb 08 10:14:24 AM UTC 25 |
Feb 08 10:14:29 AM UTC 25 |
3262282230 ps |
| T304 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.4193235345 |
|
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Feb 08 10:14:02 AM UTC 25 |
Feb 08 10:14:29 AM UTC 25 |
25355721438 ps |
| T378 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3454383236 |
|
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Feb 08 10:14:16 AM UTC 25 |
Feb 08 10:14:29 AM UTC 25 |
3057375890 ps |
| T672 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.3761767308 |
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Feb 08 10:13:33 AM UTC 25 |
Feb 08 10:14:30 AM UTC 25 |
13836596694 ps |
| T673 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.579224180 |
|
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Feb 08 10:12:40 AM UTC 25 |
Feb 08 10:14:31 AM UTC 25 |
35832020527 ps |
| T674 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3516104544 |
|
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Feb 08 10:14:24 AM UTC 25 |
Feb 08 10:14:32 AM UTC 25 |
2613806130 ps |
| T675 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2598499106 |
|
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Feb 08 10:14:29 AM UTC 25 |
Feb 08 10:14:32 AM UTC 25 |
2199435037 ps |
| T676 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.820134571 |
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Feb 08 10:14:28 AM UTC 25 |
Feb 08 10:14:33 AM UTC 25 |
2020760298 ps |
| T677 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4048022059 |
|
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Feb 08 10:14:13 AM UTC 25 |
Feb 08 10:14:34 AM UTC 25 |
3738200537 ps |
| T678 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1003465603 |
|
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Feb 08 10:14:29 AM UTC 25 |
Feb 08 10:14:34 AM UTC 25 |
2486998969 ps |
| T679 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.1143138029 |
|
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Feb 08 10:14:30 AM UTC 25 |
Feb 08 10:14:34 AM UTC 25 |
2538387332 ps |
| T130 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3236292540 |
|
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Feb 08 10:14:26 AM UTC 25 |
Feb 08 10:14:35 AM UTC 25 |
6290332007 ps |
| T680 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1289145451 |
|
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Feb 08 10:14:30 AM UTC 25 |
Feb 08 10:14:36 AM UTC 25 |
2100652513 ps |
| T367 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1305383036 |
|
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Feb 08 10:13:06 AM UTC 25 |
Feb 08 10:14:37 AM UTC 25 |
111426420214 ps |
| T681 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3644048641 |
|
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Feb 08 10:14:32 AM UTC 25 |
Feb 08 10:14:38 AM UTC 25 |
7954524194 ps |
| T682 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3092020102 |
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Feb 08 10:14:28 AM UTC 25 |
Feb 08 10:14:40 AM UTC 25 |
7290945186 ps |
| T683 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2057332375 |
|
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Feb 08 10:14:30 AM UTC 25 |
Feb 08 10:14:40 AM UTC 25 |
2617663926 ps |
| T247 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.3914311365 |
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Feb 08 10:14:27 AM UTC 25 |
Feb 08 10:14:41 AM UTC 25 |
3298388746 ps |
| T684 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1824315366 |
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Feb 08 10:14:35 AM UTC 25 |
Feb 08 10:14:41 AM UTC 25 |
3535849256 ps |
| T143 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1685871034 |
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Feb 08 10:12:48 AM UTC 25 |
Feb 08 10:14:41 AM UTC 25 |
34900019842 ps |
| T685 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3419681649 |
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Feb 08 10:14:38 AM UTC 25 |
Feb 08 10:14:42 AM UTC 25 |
2489705723 ps |
| T331 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2622494011 |
|
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Feb 08 10:13:24 AM UTC 25 |
Feb 08 10:14:42 AM UTC 25 |
1215103514769 ps |
| T686 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.692676442 |
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Feb 08 10:14:39 AM UTC 25 |
Feb 08 10:14:43 AM UTC 25 |
2092610467 ps |
| T687 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.3340142604 |
|
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Feb 08 10:14:03 AM UTC 25 |
Feb 08 10:14:43 AM UTC 25 |
11133357195 ps |
| T122 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.537970931 |
|
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Feb 08 10:14:35 AM UTC 25 |
Feb 08 10:14:46 AM UTC 25 |
30078113612 ps |
| T688 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3673768102 |
|
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Feb 08 10:14:41 AM UTC 25 |
Feb 08 10:14:47 AM UTC 25 |
3448740531 ps |
| T689 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1814197100 |
|
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Feb 08 10:14:42 AM UTC 25 |
Feb 08 10:14:47 AM UTC 25 |
7249586568 ps |
| T690 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3974014080 |
|
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Feb 08 10:14:31 AM UTC 25 |
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3266282483 ps |
| T691 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.1875559509 |
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Feb 08 10:14:37 AM UTC 25 |
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2113017489 ps |
| T347 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3410997253 |
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Feb 08 10:12:53 AM UTC 25 |
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83557488002 ps |
| T692 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1821456471 |
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Feb 08 10:14:36 AM UTC 25 |
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| T348 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.591895351 |
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Feb 08 10:13:05 AM UTC 25 |
Feb 08 10:14:49 AM UTC 25 |
129220456289 ps |
| T355 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2401398826 |
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Feb 08 10:07:50 AM UTC 25 |
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148145559115 ps |
| T693 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.886790721 |
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Feb 08 10:14:40 AM UTC 25 |
Feb 08 10:14:49 AM UTC 25 |
2614904762 ps |
| T332 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3611722033 |
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Feb 08 10:14:15 AM UTC 25 |
Feb 08 10:14:49 AM UTC 25 |
38031582200 ps |
| T694 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.97700810 |
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Feb 08 10:14:48 AM UTC 25 |
Feb 08 10:14:51 AM UTC 25 |
2031889143 ps |
| T695 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3799626356 |
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Feb 08 10:14:40 AM UTC 25 |
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2510098152 ps |
| T349 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.435356167 |
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Feb 08 10:13:48 AM UTC 25 |
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87067417067 ps |
| T696 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.1001007873 |
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Feb 08 10:14:48 AM UTC 25 |
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2137857866 ps |
| T697 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.228213993 |
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Feb 08 10:14:48 AM UTC 25 |
Feb 08 10:14:54 AM UTC 25 |
2482890660 ps |
| T698 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1366705731 |
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Feb 08 10:14:41 AM UTC 25 |
Feb 08 10:14:54 AM UTC 25 |
2885325688 ps |
| T242 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.1722729801 |
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Feb 08 10:14:50 AM UTC 25 |
Feb 08 10:14:55 AM UTC 25 |
3209653710 ps |
| T699 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1445137796 |
|
|
Feb 08 10:14:49 AM UTC 25 |
Feb 08 10:14:56 AM UTC 25 |
4949846099 ps |
| T700 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4005074822 |
|
|
Feb 08 10:14:49 AM UTC 25 |
Feb 08 10:14:57 AM UTC 25 |
2803612440 ps |
| T701 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2834904296 |
|
|
Feb 08 10:14:49 AM UTC 25 |
Feb 08 10:14:58 AM UTC 25 |
2136128084 ps |
| T702 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3023320456 |
|
|
Feb 08 10:14:49 AM UTC 25 |
Feb 08 10:14:58 AM UTC 25 |
2517159117 ps |
| T333 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1250986 |
|
|
Feb 08 10:14:26 AM UTC 25 |
Feb 08 10:14:59 AM UTC 25 |
33732469764 ps |
| T703 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.80824953 |
|
|
Feb 08 10:14:47 AM UTC 25 |
Feb 08 10:14:59 AM UTC 25 |
16433512402 ps |
| T704 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2756973413 |
|
|
Feb 08 10:14:54 AM UTC 25 |
Feb 08 10:14:59 AM UTC 25 |
2126471154 ps |
| T705 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.587844755 |
|
|
Feb 08 10:14:54 AM UTC 25 |
Feb 08 10:15:00 AM UTC 25 |
2016093965 ps |
| T706 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2164122870 |
|
|
Feb 08 10:14:16 AM UTC 25 |
Feb 08 10:15:00 AM UTC 25 |
15339015777 ps |
| T707 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.447020963 |
|
|
Feb 08 10:14:55 AM UTC 25 |
Feb 08 10:15:01 AM UTC 25 |
2492209932 ps |
| T708 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.316374635 |
|
|
Feb 08 10:14:56 AM UTC 25 |
Feb 08 10:15:02 AM UTC 25 |
2517474495 ps |
| T709 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2853847285 |
|
|
Feb 08 10:14:55 AM UTC 25 |
Feb 08 10:15:02 AM UTC 25 |
2254807354 ps |
| T710 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1099999905 |
|
|
Feb 08 10:14:58 AM UTC 25 |
Feb 08 10:15:03 AM UTC 25 |
3613601860 ps |
| T711 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.86456662 |
|
|
Feb 08 10:14:49 AM UTC 25 |
Feb 08 10:15:04 AM UTC 25 |
2609046534 ps |
| T411 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2707715321 |
|
|
Feb 08 10:14:15 AM UTC 25 |
Feb 08 10:15:06 AM UTC 25 |
138495726193 ps |
| T166 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2901504593 |
|
|
Feb 08 10:14:50 AM UTC 25 |
Feb 08 10:15:06 AM UTC 25 |
12459188931 ps |
| T334 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.2031623479 |
|
|
Feb 08 10:14:32 AM UTC 25 |
Feb 08 10:15:06 AM UTC 25 |
166665287952 ps |
| T712 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3857311921 |
|
|
Feb 08 10:14:57 AM UTC 25 |
Feb 08 10:15:07 AM UTC 25 |
2615075762 ps |
| T713 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.3358223398 |
|
|
Feb 08 10:15:01 AM UTC 25 |
Feb 08 10:15:07 AM UTC 25 |
2036590327 ps |
| T714 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.388200823 |
|
|
Feb 08 10:14:59 AM UTC 25 |
Feb 08 10:15:08 AM UTC 25 |
7611016438 ps |
| T715 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2970722514 |
|
|
Feb 08 10:15:00 AM UTC 25 |
Feb 08 10:15:08 AM UTC 25 |
2643343091 ps |
| T716 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.749998224 |
|
|
Feb 08 10:15:04 AM UTC 25 |
Feb 08 10:15:09 AM UTC 25 |
2078783781 ps |
| T717 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.3090695404 |
|
|
Feb 08 10:15:03 AM UTC 25 |
Feb 08 10:15:10 AM UTC 25 |
2119850402 ps |
| T718 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4012902746 |
|
|
Feb 08 10:14:59 AM UTC 25 |
Feb 08 10:15:10 AM UTC 25 |
3435145812 ps |
| T719 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1671649957 |
|
|
Feb 08 10:15:07 AM UTC 25 |
Feb 08 10:15:10 AM UTC 25 |
2634679894 ps |
| T720 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3024131115 |
|
|
Feb 08 10:15:07 AM UTC 25 |
Feb 08 10:15:12 AM UTC 25 |
4041874596 ps |
| T721 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1052624772 |
|
|
Feb 08 10:15:03 AM UTC 25 |
Feb 08 10:15:14 AM UTC 25 |
2456091452 ps |
| T409 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1537769987 |
|
|
Feb 08 10:11:56 AM UTC 25 |
Feb 08 10:15:17 AM UTC 25 |
64195094132 ps |
| T379 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2660272643 |
|
|
Feb 08 10:12:40 AM UTC 25 |
Feb 08 10:15:17 AM UTC 25 |
44731240119 ps |
| T722 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1460671110 |
|
|
Feb 08 10:15:05 AM UTC 25 |
Feb 08 10:15:18 AM UTC 25 |
2511764648 ps |
| T723 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3677402385 |
|
|
Feb 08 10:15:11 AM UTC 25 |
Feb 08 10:15:18 AM UTC 25 |
2017368655 ps |
| T724 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.701284035 |
|
|
Feb 08 10:15:16 AM UTC 25 |
Feb 08 10:15:19 AM UTC 25 |
2186545391 ps |
| T725 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3893234032 |
|
|
Feb 08 10:15:11 AM UTC 25 |
Feb 08 10:15:21 AM UTC 25 |
2110896669 ps |
| T726 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3680619428 |
|
|
Feb 08 10:15:08 AM UTC 25 |
Feb 08 10:15:21 AM UTC 25 |
3588713800 ps |
| T727 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.1553525846 |
|
|
Feb 08 10:15:10 AM UTC 25 |
Feb 08 10:15:22 AM UTC 25 |
12014136380 ps |
| T728 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.3241546255 |
|
|
Feb 08 10:15:18 AM UTC 25 |
Feb 08 10:15:22 AM UTC 25 |
2530681793 ps |
| T729 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2358122183 |
|
|
Feb 08 10:15:07 AM UTC 25 |
Feb 08 10:15:24 AM UTC 25 |
3285528473 ps |
| T730 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3392498913 |
|
|
Feb 08 10:15:20 AM UTC 25 |
Feb 08 10:15:24 AM UTC 25 |
4491643769 ps |
| T731 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.631658526 |
|
|
Feb 08 10:15:14 AM UTC 25 |
Feb 08 10:15:24 AM UTC 25 |
2479301010 ps |
| T732 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2783907772 |
|
|
Feb 08 10:15:19 AM UTC 25 |
Feb 08 10:15:24 AM UTC 25 |
3767859857 ps |
| T733 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.648341723 |
|
|
Feb 08 10:15:09 AM UTC 25 |
Feb 08 10:15:25 AM UTC 25 |
3879083982 ps |
| T734 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2166045690 |
|
|
Feb 08 10:15:19 AM UTC 25 |
Feb 08 10:15:25 AM UTC 25 |
3568714737 ps |
| T735 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.3306371506 |
|
|
Feb 08 10:15:01 AM UTC 25 |
Feb 08 10:15:26 AM UTC 25 |
9078391519 ps |
| T736 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3764857959 |
|
|
Feb 08 10:15:18 AM UTC 25 |
Feb 08 10:15:27 AM UTC 25 |
2617345789 ps |
| T225 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1458051177 |
|
|
Feb 08 10:15:22 AM UTC 25 |
Feb 08 10:15:29 AM UTC 25 |
2947052999 ps |
| T737 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3688293263 |
|
|
Feb 08 10:15:25 AM UTC 25 |
Feb 08 10:15:30 AM UTC 25 |
2489668244 ps |
| T738 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3158227971 |
|
|
Feb 08 10:15:28 AM UTC 25 |
Feb 08 10:15:36 AM UTC 25 |
4615324462 ps |
| T739 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.299492960 |
|
|
Feb 08 10:15:24 AM UTC 25 |
Feb 08 10:15:36 AM UTC 25 |
2014052670 ps |
| T412 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1283851699 |
|
|
Feb 08 10:12:23 AM UTC 25 |
Feb 08 10:15:37 AM UTC 25 |
46306374321 ps |
| T740 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2288773621 |
|
|
Feb 08 10:15:30 AM UTC 25 |
Feb 08 10:15:37 AM UTC 25 |
3696228034 ps |
| T741 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2414549229 |
|
|
Feb 08 10:15:25 AM UTC 25 |
Feb 08 10:15:37 AM UTC 25 |
2112574623 ps |
| T742 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4013996363 |
|
|
Feb 08 10:15:31 AM UTC 25 |
Feb 08 10:15:39 AM UTC 25 |
6574572499 ps |
| T743 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4041210833 |
|
|
Feb 08 10:15:27 AM UTC 25 |
Feb 08 10:15:40 AM UTC 25 |
2174739935 ps |
| T744 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3388559013 |
|
|
Feb 08 10:15:27 AM UTC 25 |
Feb 08 10:15:41 AM UTC 25 |
2512421099 ps |
| T475 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3883899691 |
|
|
Feb 08 10:13:49 AM UTC 25 |
Feb 08 10:15:42 AM UTC 25 |
149680525715 ps |
| T745 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2489892767 |
|
|
Feb 08 10:15:27 AM UTC 25 |
Feb 08 10:15:44 AM UTC 25 |
2610371737 ps |
| T746 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1837036370 |
|
|
Feb 08 10:15:24 AM UTC 25 |
Feb 08 10:15:45 AM UTC 25 |
11089970752 ps |
| T380 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.4166463798 |
|
|
Feb 08 10:13:50 AM UTC 25 |
Feb 08 10:15:46 AM UTC 25 |
35889989410 ps |
| T295 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.1648898031 |
|
|
Feb 08 10:15:38 AM UTC 25 |
Feb 08 10:15:47 AM UTC 25 |
3560589666 ps |
| T747 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3525906550 |
|
|
Feb 08 10:15:42 AM UTC 25 |
Feb 08 10:15:47 AM UTC 25 |
2486576929 ps |
| T748 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.2407694440 |
|
|
Feb 08 10:15:44 AM UTC 25 |
Feb 08 10:15:49 AM UTC 25 |
2528376085 ps |
| T749 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.990473578 |
|
|
Feb 08 10:15:45 AM UTC 25 |
Feb 08 10:15:51 AM UTC 25 |
2635667701 ps |
| T750 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2277527385 |
|
|
Feb 08 10:15:48 AM UTC 25 |
Feb 08 10:15:52 AM UTC 25 |
3008722920 ps |
| T751 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1660995163 |
|
|
Feb 08 10:15:39 AM UTC 25 |
Feb 08 10:15:52 AM UTC 25 |
2010267418 ps |
| T408 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3945910844 |
|
|
Feb 08 10:15:37 AM UTC 25 |
Feb 08 10:15:53 AM UTC 25 |
31025944406 ps |
| T752 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.1199143875 |
|
|
Feb 08 10:14:54 AM UTC 25 |
Feb 08 10:15:54 AM UTC 25 |
13869866481 ps |
| T753 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2691193915 |
|
|
Feb 08 10:15:40 AM UTC 25 |
Feb 08 10:15:54 AM UTC 25 |
2108556052 ps |
| T754 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1783938885 |
|
|
Feb 08 10:15:46 AM UTC 25 |
Feb 08 10:15:54 AM UTC 25 |
3869042576 ps |
| T755 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.1573744763 |
|
|
Feb 08 10:15:43 AM UTC 25 |
Feb 08 10:15:57 AM UTC 25 |
2076400575 ps |
| T756 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2366305628 |
|
|
Feb 08 10:15:55 AM UTC 25 |
Feb 08 10:15:58 AM UTC 25 |
2096028264 ps |
| T144 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.361547423 |
|
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Feb 08 10:11:49 AM UTC 25 |
Feb 08 10:16:06 AM UTC 25 |
85085123037 ps |
| T757 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3284974041 |
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Feb 08 10:15:50 AM UTC 25 |
Feb 08 10:16:07 AM UTC 25 |
4956949220 ps |
| T422 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.797333609 |
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Feb 08 10:11:47 AM UTC 25 |
Feb 08 10:16:07 AM UTC 25 |
89837978491 ps |
| T128 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1980825660 |
|
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Feb 08 10:15:09 AM UTC 25 |
Feb 08 10:16:08 AM UTC 25 |
85719827244 ps |
| T758 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2069835774 |
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Feb 08 10:15:47 AM UTC 25 |
Feb 08 10:16:08 AM UTC 25 |
3870472152 ps |
| T414 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.2503577946 |
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Feb 08 10:09:32 AM UTC 25 |
Feb 08 10:16:08 AM UTC 25 |
126607862515 ps |
| T759 |
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Feb 08 10:14:42 AM UTC 25 |
Feb 08 10:16:09 AM UTC 25 |
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| T108 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2185848038 |
|
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Feb 08 10:14:52 AM UTC 25 |
Feb 08 10:16:10 AM UTC 25 |
277733836194 ps |
| T760 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2640798648 |
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Feb 08 10:15:53 AM UTC 25 |
Feb 08 10:16:12 AM UTC 25 |
7798299834 ps |
| T455 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2278263916 |
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Feb 08 10:14:00 AM UTC 25 |
Feb 08 10:16:13 AM UTC 25 |
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| T444 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.427179634 |
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Feb 08 10:14:27 AM UTC 25 |
Feb 08 10:16:26 AM UTC 25 |
120505882753 ps |
| T430 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3845079203 |
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Feb 08 10:15:51 AM UTC 25 |
Feb 08 10:16:29 AM UTC 25 |
80331182656 ps |
| T306 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.33715971 |
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Feb 08 10:15:52 AM UTC 25 |
Feb 08 10:16:36 AM UTC 25 |
42949634714 ps |
| T761 |
/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1648953917 |
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Feb 08 10:14:44 AM UTC 25 |
Feb 08 10:16:43 AM UTC 25 |
81333562769 ps |
| T452 |
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Feb 08 10:15:00 AM UTC 25 |
Feb 08 10:16:45 AM UTC 25 |
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Feb 08 10:14:42 AM UTC 25 |
Feb 08 10:16:48 AM UTC 25 |
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Feb 08 10:15:00 AM UTC 25 |
Feb 08 10:16:49 AM UTC 25 |
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Feb 08 10:13:38 AM UTC 25 |
Feb 08 10:16:54 AM UTC 25 |
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Feb 08 10:15:09 AM UTC 25 |
Feb 08 10:16:55 AM UTC 25 |
52480304510 ps |
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Feb 08 10:15:00 AM UTC 25 |
Feb 08 10:16:58 AM UTC 25 |
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Feb 08 10:16:09 AM UTC 25 |
Feb 08 10:17:00 AM UTC 25 |
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Feb 08 10:15:58 AM UTC 25 |
Feb 08 10:17:06 AM UTC 25 |
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Feb 08 10:16:46 AM UTC 25 |
Feb 08 10:17:07 AM UTC 25 |
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Feb 08 10:16:31 AM UTC 25 |
Feb 08 10:17:13 AM UTC 25 |
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Feb 08 10:11:23 AM UTC 25 |
Feb 08 10:17:17 AM UTC 25 |
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Feb 08 10:16:44 AM UTC 25 |
Feb 08 10:17:19 AM UTC 25 |
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Feb 08 10:15:38 AM UTC 25 |
Feb 08 10:17:28 AM UTC 25 |
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Feb 08 10:16:07 AM UTC 25 |
Feb 08 10:17:28 AM UTC 25 |
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Feb 08 10:14:51 AM UTC 25 |
Feb 08 10:17:28 AM UTC 25 |
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Feb 08 10:15:38 AM UTC 25 |
Feb 08 10:17:31 AM UTC 25 |
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Feb 08 10:15:23 AM UTC 25 |
Feb 08 10:17:31 AM UTC 25 |
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Feb 08 10:12:13 AM UTC 25 |
Feb 08 10:17:33 AM UTC 25 |
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| T767 |
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Feb 08 10:13:29 AM UTC 25 |
Feb 08 10:17:34 AM UTC 25 |
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Feb 08 10:16:10 AM UTC 25 |
Feb 08 10:17:36 AM UTC 25 |
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Feb 08 10:16:10 AM UTC 25 |
Feb 08 10:17:37 AM UTC 25 |
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Feb 08 10:12:38 AM UTC 25 |
Feb 08 10:17:38 AM UTC 25 |
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Feb 08 10:13:39 AM UTC 25 |
Feb 08 10:17:38 AM UTC 25 |
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Feb 08 10:17:29 AM UTC 25 |
Feb 08 10:17:41 AM UTC 25 |
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Feb 08 10:08:15 AM UTC 25 |
Feb 08 10:17:42 AM UTC 25 |
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Feb 08 10:17:08 AM UTC 25 |
Feb 08 10:17:43 AM UTC 25 |
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Feb 08 10:15:22 AM UTC 25 |
Feb 08 10:17:45 AM UTC 25 |
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Feb 08 10:16:08 AM UTC 25 |
Feb 08 10:18:31 AM UTC 25 |
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Feb 08 10:16:49 AM UTC 25 |
Feb 08 10:17:47 AM UTC 25 |
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Feb 08 10:12:14 AM UTC 25 |
Feb 08 10:17:49 AM UTC 25 |
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Feb 08 10:17:18 AM UTC 25 |
Feb 08 10:17:54 AM UTC 25 |
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Feb 08 10:16:09 AM UTC 25 |
Feb 08 10:18:00 AM UTC 25 |
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Feb 08 10:17:29 AM UTC 25 |
Feb 08 10:18:03 AM UTC 25 |
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Feb 08 10:17:36 AM UTC 25 |
Feb 08 10:18:05 AM UTC 25 |
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Feb 08 10:16:09 AM UTC 25 |
Feb 08 10:18:05 AM UTC 25 |
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Feb 08 10:17:20 AM UTC 25 |
Feb 08 10:18:07 AM UTC 25 |
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Feb 08 10:15:55 AM UTC 25 |
Feb 08 10:18:07 AM UTC 25 |
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Feb 08 10:15:55 AM UTC 25 |
Feb 08 10:18:11 AM UTC 25 |
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Feb 08 10:13:06 AM UTC 25 |
Feb 08 10:18:12 AM UTC 25 |
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Feb 08 10:13:20 AM UTC 25 |
Feb 08 10:18:14 AM UTC 25 |
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Feb 08 10:17:34 AM UTC 25 |
Feb 08 10:18:17 AM UTC 25 |
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Feb 08 10:15:59 AM UTC 25 |
Feb 08 10:18:17 AM UTC 25 |
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Feb 08 10:16:28 AM UTC 25 |
Feb 08 10:18:18 AM UTC 25 |
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Feb 08 10:17:55 AM UTC 25 |
Feb 08 10:18:20 AM UTC 25 |
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Feb 08 10:17:01 AM UTC 25 |
Feb 08 10:18:23 AM UTC 25 |
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Feb 08 10:17:48 AM UTC 25 |
Feb 08 10:18:24 AM UTC 25 |
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Feb 08 10:17:29 AM UTC 25 |
Feb 08 10:18:30 AM UTC 25 |
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Feb 08 10:17:38 AM UTC 25 |
Feb 08 10:18:36 AM UTC 25 |
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Feb 08 10:16:37 AM UTC 25 |
Feb 08 10:18:39 AM UTC 25 |
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Feb 08 10:17:49 AM UTC 25 |
Feb 08 10:18:40 AM UTC 25 |
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Feb 08 10:17:38 AM UTC 25 |
Feb 08 10:18:45 AM UTC 25 |
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Feb 08 10:16:55 AM UTC 25 |
Feb 08 10:18:49 AM UTC 25 |
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Feb 08 10:17:44 AM UTC 25 |
Feb 08 10:18:56 AM UTC 25 |
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Feb 08 10:16:55 AM UTC 25 |
Feb 08 10:18:59 AM UTC 25 |
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Feb 08 10:17:06 AM UTC 25 |
Feb 08 10:19:00 AM UTC 25 |
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Feb 08 10:17:35 AM UTC 25 |
Feb 08 10:19:02 AM UTC 25 |
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Feb 08 10:17:37 AM UTC 25 |
Feb 08 10:19:08 AM UTC 25 |
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Feb 08 10:16:08 AM UTC 25 |
Feb 08 10:19:14 AM UTC 25 |
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Feb 08 10:15:21 AM UTC 25 |
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Feb 08 10:17:14 AM UTC 25 |
Feb 08 10:19:19 AM UTC 25 |
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Feb 08 10:17:42 AM UTC 25 |
Feb 08 10:19:32 AM UTC 25 |
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Feb 08 10:17:32 AM UTC 25 |
Feb 08 10:19:39 AM UTC 25 |
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Feb 08 10:17:46 AM UTC 25 |
Feb 08 10:19:42 AM UTC 25 |
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Feb 08 10:16:13 AM UTC 25 |
Feb 08 10:19:43 AM UTC 25 |
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Feb 08 10:15:48 AM UTC 25 |
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Feb 08 10:17:32 AM UTC 25 |
Feb 08 10:19:54 AM UTC 25 |
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Feb 08 10:15:55 AM UTC 25 |
Feb 08 10:20:14 AM UTC 25 |
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Feb 08 10:14:44 AM UTC 25 |
Feb 08 10:20:17 AM UTC 25 |
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Feb 08 10:14:27 AM UTC 25 |
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Feb 08 10:17:48 AM UTC 25 |
Feb 08 10:20:25 AM UTC 25 |
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Feb 08 10:17:43 AM UTC 25 |
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Feb 08 10:15:08 AM UTC 25 |
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