| T619 |
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Oct 14 10:21:05 PM UTC 24 |
Oct 14 10:21:17 PM UTC 24 |
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Oct 14 10:20:50 PM UTC 24 |
Oct 14 10:21:18 PM UTC 24 |
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Oct 14 10:21:16 PM UTC 24 |
Oct 14 10:21:21 PM UTC 24 |
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Oct 14 10:21:07 PM UTC 24 |
Oct 14 10:21:25 PM UTC 24 |
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Oct 14 10:21:15 PM UTC 24 |
Oct 14 10:21:25 PM UTC 24 |
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Oct 14 10:21:18 PM UTC 24 |
Oct 14 10:21:26 PM UTC 24 |
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Oct 14 10:21:21 PM UTC 24 |
Oct 14 10:21:26 PM UTC 24 |
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Oct 14 10:18:11 PM UTC 24 |
Oct 14 10:21:27 PM UTC 24 |
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Oct 14 10:21:00 PM UTC 24 |
Oct 14 10:21:29 PM UTC 24 |
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Oct 14 10:21:17 PM UTC 24 |
Oct 14 10:21:30 PM UTC 24 |
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Oct 14 10:21:17 PM UTC 24 |
Oct 14 10:21:30 PM UTC 24 |
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Oct 14 10:21:25 PM UTC 24 |
Oct 14 10:21:32 PM UTC 24 |
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Oct 14 10:17:28 PM UTC 24 |
Oct 14 10:21:32 PM UTC 24 |
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Oct 14 10:21:10 PM UTC 24 |
Oct 14 10:21:32 PM UTC 24 |
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Oct 14 10:17:26 PM UTC 24 |
Oct 14 10:21:36 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3232010227 |
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Oct 14 10:18:33 PM UTC 24 |
Oct 14 10:21:38 PM UTC 24 |
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Oct 14 10:12:59 PM UTC 24 |
Oct 14 10:21:38 PM UTC 24 |
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Oct 14 10:21:33 PM UTC 24 |
Oct 14 10:21:38 PM UTC 24 |
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Oct 14 10:21:31 PM UTC 24 |
Oct 14 10:21:40 PM UTC 24 |
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Oct 14 10:21:19 PM UTC 24 |
Oct 14 10:21:42 PM UTC 24 |
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Oct 14 10:21:31 PM UTC 24 |
Oct 14 10:21:42 PM UTC 24 |
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Oct 14 10:21:29 PM UTC 24 |
Oct 14 10:21:43 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.1274632360 |
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Oct 14 10:21:41 PM UTC 24 |
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Oct 14 10:21:36 PM UTC 24 |
Oct 14 10:21:44 PM UTC 24 |
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Oct 14 10:21:27 PM UTC 24 |
Oct 14 10:21:44 PM UTC 24 |
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Oct 14 10:21:33 PM UTC 24 |
Oct 14 10:21:45 PM UTC 24 |
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Oct 14 10:21:32 PM UTC 24 |
Oct 14 10:21:46 PM UTC 24 |
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Oct 14 10:21:40 PM UTC 24 |
Oct 14 10:21:46 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4011153431 |
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Oct 14 10:13:19 PM UTC 24 |
Oct 14 10:21:46 PM UTC 24 |
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Oct 14 10:21:45 PM UTC 24 |
Oct 14 10:21:50 PM UTC 24 |
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Oct 14 10:21:47 PM UTC 24 |
Oct 14 10:21:51 PM UTC 24 |
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Oct 14 10:21:47 PM UTC 24 |
Oct 14 10:21:51 PM UTC 24 |
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Oct 14 10:21:47 PM UTC 24 |
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Oct 14 10:21:39 PM UTC 24 |
Oct 14 10:21:52 PM UTC 24 |
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Oct 14 10:16:11 PM UTC 24 |
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Oct 14 10:21:45 PM UTC 24 |
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Oct 14 10:21:43 PM UTC 24 |
Oct 14 10:21:55 PM UTC 24 |
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Oct 14 10:20:49 PM UTC 24 |
Oct 14 10:22:37 PM UTC 24 |
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Oct 14 10:21:40 PM UTC 24 |
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Oct 14 10:21:49 PM UTC 24 |
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Oct 14 10:21:45 PM UTC 24 |
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Oct 14 10:21:57 PM UTC 24 |
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| T648 |
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Oct 14 10:21:57 PM UTC 24 |
Oct 14 10:22:00 PM UTC 24 |
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Oct 14 10:21:47 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1976911908 |
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Oct 14 10:21:57 PM UTC 24 |
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Oct 14 10:21:58 PM UTC 24 |
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Oct 14 10:21:54 PM UTC 24 |
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Oct 14 10:21:54 PM UTC 24 |
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Oct 14 10:21:53 PM UTC 24 |
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Oct 14 10:21:12 PM UTC 24 |
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Oct 14 10:21:51 PM UTC 24 |
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Oct 14 10:21:59 PM UTC 24 |
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Oct 14 10:21:58 PM UTC 24 |
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Oct 14 10:22:09 PM UTC 24 |
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Oct 14 10:22:00 PM UTC 24 |
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Oct 14 10:22:09 PM UTC 24 |
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Oct 14 10:22:07 PM UTC 24 |
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Oct 14 10:22:09 PM UTC 24 |
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Oct 14 10:22:00 PM UTC 24 |
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Oct 14 10:19:45 PM UTC 24 |
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Oct 14 10:21:26 PM UTC 24 |
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Oct 14 10:22:15 PM UTC 24 |
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Oct 14 10:22:08 PM UTC 24 |
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Oct 14 10:22:14 PM UTC 24 |
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Oct 14 10:22:03 PM UTC 24 |
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Oct 14 10:18:51 PM UTC 24 |
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Oct 14 10:22:14 PM UTC 24 |
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Oct 14 10:13:51 PM UTC 24 |
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Oct 14 10:22:22 PM UTC 24 |
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Oct 14 10:20:22 PM UTC 24 |
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Oct 14 10:22:15 PM UTC 24 |
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Oct 14 10:22:16 PM UTC 24 |
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| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4229657462 |
|
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Oct 14 10:22:33 PM UTC 24 |
Oct 14 10:22:40 PM UTC 24 |
10000444999 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.1444570299 |
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Oct 14 10:22:38 PM UTC 24 |
Oct 14 10:22:41 PM UTC 24 |
2140303723 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2343258087 |
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Oct 14 10:22:18 PM UTC 24 |
Oct 14 10:22:42 PM UTC 24 |
18682749305 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.3245590757 |
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Oct 14 10:22:34 PM UTC 24 |
Oct 14 10:22:43 PM UTC 24 |
2011822320 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.3302938294 |
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Oct 14 10:22:38 PM UTC 24 |
Oct 14 10:22:43 PM UTC 24 |
2121396924 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.2675231628 |
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Oct 14 10:22:40 PM UTC 24 |
Oct 14 10:22:44 PM UTC 24 |
2560522066 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.1761837587 |
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Oct 14 10:22:06 PM UTC 24 |
Oct 14 10:22:45 PM UTC 24 |
65070279967 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3888160254 |
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Oct 14 10:20:40 PM UTC 24 |
Oct 14 10:22:46 PM UTC 24 |
46249654215 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3285268449 |
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Oct 14 10:22:42 PM UTC 24 |
Oct 14 10:22:47 PM UTC 24 |
3348692718 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.421199457 |
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Oct 14 10:18:53 PM UTC 24 |
Oct 14 10:22:47 PM UTC 24 |
61680384120 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2449379287 |
|
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Oct 14 10:22:06 PM UTC 24 |
Oct 14 10:22:50 PM UTC 24 |
519156641013 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1828392091 |
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Oct 14 10:22:48 PM UTC 24 |
Oct 14 10:22:52 PM UTC 24 |
2040780277 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1826606797 |
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Oct 14 10:22:40 PM UTC 24 |
Oct 14 10:22:52 PM UTC 24 |
2609156480 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.491734129 |
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Oct 14 10:22:44 PM UTC 24 |
Oct 14 10:22:52 PM UTC 24 |
6625135298 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.911040515 |
|
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Oct 14 10:18:29 PM UTC 24 |
Oct 14 10:22:52 PM UTC 24 |
143364431053 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3464841915 |
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Oct 14 10:22:45 PM UTC 24 |
Oct 14 10:22:53 PM UTC 24 |
3015756386 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.237575037 |
|
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Oct 14 10:22:38 PM UTC 24 |
Oct 14 10:22:53 PM UTC 24 |
2462511804 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.873163421 |
|
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Oct 14 10:22:48 PM UTC 24 |
Oct 14 10:22:53 PM UTC 24 |
2121035605 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1740955400 |
|
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Oct 14 10:22:31 PM UTC 24 |
Oct 14 10:22:54 PM UTC 24 |
4550422164 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.533187212 |
|
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Oct 14 10:22:42 PM UTC 24 |
Oct 14 10:22:55 PM UTC 24 |
3288311594 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.631341585 |
|
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Oct 14 10:23:24 PM UTC 24 |
Oct 14 10:23:30 PM UTC 24 |
2538988922 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3660973346 |
|
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Oct 14 10:22:50 PM UTC 24 |
Oct 14 10:22:55 PM UTC 24 |
2480487204 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2672215551 |
|
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Oct 14 10:22:52 PM UTC 24 |
Oct 14 10:22:55 PM UTC 24 |
2609087269 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.234693408 |
|
|
Oct 14 10:22:52 PM UTC 24 |
Oct 14 10:22:56 PM UTC 24 |
2664115903 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1618692249 |
|
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Oct 14 10:20:03 PM UTC 24 |
Oct 14 10:22:58 PM UTC 24 |
115370546064 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2068389532 |
|
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Oct 14 10:22:47 PM UTC 24 |
Oct 14 10:22:59 PM UTC 24 |
18071956159 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2344515100 |
|
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Oct 14 10:21:43 PM UTC 24 |
Oct 14 10:22:59 PM UTC 24 |
18826954852 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.744607354 |
|
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Oct 14 10:22:54 PM UTC 24 |
Oct 14 10:23:00 PM UTC 24 |
3742747545 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.72894682 |
|
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Oct 14 10:22:50 PM UTC 24 |
Oct 14 10:23:00 PM UTC 24 |
2052580573 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.3942065232 |
|
|
Oct 14 10:22:57 PM UTC 24 |
Oct 14 10:23:02 PM UTC 24 |
2129903232 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.24082826 |
|
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Oct 14 10:22:56 PM UTC 24 |
Oct 14 10:23:02 PM UTC 24 |
2015455626 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3188361767 |
|
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Oct 14 10:22:59 PM UTC 24 |
Oct 14 10:23:04 PM UTC 24 |
2028062833 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.3610491781 |
|
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Oct 14 10:22:59 PM UTC 24 |
Oct 14 10:23:04 PM UTC 24 |
2488289875 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2916456266 |
|
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Oct 14 10:22:54 PM UTC 24 |
Oct 14 10:23:05 PM UTC 24 |
3435454523 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3516090798 |
|
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Oct 14 10:23:03 PM UTC 24 |
Oct 14 10:23:08 PM UTC 24 |
2691522918 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.2324293197 |
|
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Oct 14 10:20:25 PM UTC 24 |
Oct 14 10:23:08 PM UTC 24 |
428655781868 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3892822849 |
|
|
Oct 14 10:23:01 PM UTC 24 |
Oct 14 10:23:09 PM UTC 24 |
2618472215 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.5574737 |
|
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Oct 14 10:21:43 PM UTC 24 |
Oct 14 10:23:10 PM UTC 24 |
22832442013 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3686689216 |
|
|
Oct 14 10:23:01 PM UTC 24 |
Oct 14 10:23:10 PM UTC 24 |
3375050882 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3679579238 |
|
|
Oct 14 10:21:28 PM UTC 24 |
Oct 14 10:23:10 PM UTC 24 |
95264065191 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3003896791 |
|
|
Oct 14 10:23:05 PM UTC 24 |
Oct 14 10:23:10 PM UTC 24 |
3520198877 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.2492742563 |
|
|
Oct 14 10:23:00 PM UTC 24 |
Oct 14 10:23:11 PM UTC 24 |
2511759767 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2553406389 |
|
|
Oct 14 10:18:01 PM UTC 24 |
Oct 14 10:23:13 PM UTC 24 |
108887226732 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3103345949 |
|
|
Oct 14 10:22:55 PM UTC 24 |
Oct 14 10:23:14 PM UTC 24 |
3609146720 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.2717613379 |
|
|
Oct 14 10:23:12 PM UTC 24 |
Oct 14 10:23:16 PM UTC 24 |
2072965633 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1220474051 |
|
|
Oct 14 10:23:12 PM UTC 24 |
Oct 14 10:23:17 PM UTC 24 |
2524412367 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.911058931 |
|
|
Oct 14 10:13:42 PM UTC 24 |
Oct 14 10:23:18 PM UTC 24 |
284685480495 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3868837552 |
|
|
Oct 14 10:22:56 PM UTC 24 |
Oct 14 10:23:18 PM UTC 24 |
11269268327 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.1110323746 |
|
|
Oct 14 10:23:10 PM UTC 24 |
Oct 14 10:23:18 PM UTC 24 |
2110745948 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4153624702 |
|
|
Oct 14 10:23:13 PM UTC 24 |
Oct 14 10:23:20 PM UTC 24 |
2617759685 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1786834503 |
|
|
Oct 14 10:23:17 PM UTC 24 |
Oct 14 10:23:21 PM UTC 24 |
9052871440 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.488195879 |
|
|
Oct 14 10:23:14 PM UTC 24 |
Oct 14 10:23:22 PM UTC 24 |
2722639917 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.1485541966 |
|
|
Oct 14 10:23:09 PM UTC 24 |
Oct 14 10:23:22 PM UTC 24 |
2009456809 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1875448072 |
|
|
Oct 14 10:23:03 PM UTC 24 |
Oct 14 10:23:22 PM UTC 24 |
3419676817 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.3052962835 |
|
|
Oct 14 10:22:56 PM UTC 24 |
Oct 14 10:23:23 PM UTC 24 |
11620906623 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3454951768 |
|
|
Oct 14 10:22:20 PM UTC 24 |
Oct 14 10:23:23 PM UTC 24 |
16415473946 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.2364929600 |
|
|
Oct 14 10:23:10 PM UTC 24 |
Oct 14 10:23:24 PM UTC 24 |
2461768867 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.1828680341 |
|
|
Oct 14 10:20:00 PM UTC 24 |
Oct 14 10:23:25 PM UTC 24 |
62467280701 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.1322705159 |
|
|
Oct 14 10:20:58 PM UTC 24 |
Oct 14 10:23:25 PM UTC 24 |
49473436757 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3420429580 |
|
|
Oct 14 10:17:10 PM UTC 24 |
Oct 14 10:23:26 PM UTC 24 |
109006996460 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.49714571 |
|
|
Oct 14 10:23:23 PM UTC 24 |
Oct 14 10:23:27 PM UTC 24 |
2027294224 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1529368547 |
|
|
Oct 14 10:23:24 PM UTC 24 |
Oct 14 10:23:27 PM UTC 24 |
2650500830 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3109528575 |
|
|
Oct 14 10:23:15 PM UTC 24 |
Oct 14 10:23:28 PM UTC 24 |
3490724458 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3192565115 |
|
|
Oct 14 10:23:23 PM UTC 24 |
Oct 14 10:23:28 PM UTC 24 |
2498110030 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.1882112286 |
|
|
Oct 14 10:23:23 PM UTC 24 |
Oct 14 10:23:28 PM UTC 24 |
2134742979 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.524817747 |
|
|
Oct 14 10:23:19 PM UTC 24 |
Oct 14 10:23:28 PM UTC 24 |
3255418577 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2709796260 |
|
|
Oct 14 10:23:19 PM UTC 24 |
Oct 14 10:23:29 PM UTC 24 |
42747488561 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2465850776 |
|
|
Oct 14 10:23:26 PM UTC 24 |
Oct 14 10:23:29 PM UTC 24 |
3170758757 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3636828626 |
|
|
Oct 14 10:23:09 PM UTC 24 |
Oct 14 10:23:29 PM UTC 24 |
4200353799 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3129608006 |
|
|
Oct 14 10:23:23 PM UTC 24 |
Oct 14 10:23:30 PM UTC 24 |
2122257190 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2731195834 |
|
|
Oct 14 10:23:25 PM UTC 24 |
Oct 14 10:23:31 PM UTC 24 |
3116561509 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.935650069 |
|
|
Oct 14 10:23:28 PM UTC 24 |
Oct 14 10:23:32 PM UTC 24 |
3262585129 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.775410885 |
|
|
Oct 14 10:23:26 PM UTC 24 |
Oct 14 10:23:32 PM UTC 24 |
5330510746 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.1895912324 |
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|
Oct 14 10:22:54 PM UTC 24 |
Oct 14 10:25:58 PM UTC 24 |
119750086421 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.403286543 |
|
|
Oct 14 10:23:30 PM UTC 24 |
Oct 14 10:23:35 PM UTC 24 |
2488264826 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2457882691 |
|
|
Oct 14 10:23:31 PM UTC 24 |
Oct 14 10:23:35 PM UTC 24 |
8233545407 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.4100312771 |
|
|
Oct 14 10:23:30 PM UTC 24 |
Oct 14 10:23:36 PM UTC 24 |
2020162303 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1293342829 |
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|
Oct 14 10:23:20 PM UTC 24 |
Oct 14 10:23:36 PM UTC 24 |
16062719282 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.746349215 |
|
|
Oct 14 10:23:31 PM UTC 24 |
Oct 14 10:23:36 PM UTC 24 |
2630733527 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.889147509 |
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Oct 14 10:23:30 PM UTC 24 |
Oct 14 10:23:37 PM UTC 24 |
2112618154 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.172520620 |
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Oct 14 10:23:31 PM UTC 24 |
Oct 14 10:23:38 PM UTC 24 |
3647204849 ps |
| T298 |
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Oct 14 10:23:29 PM UTC 24 |
Oct 14 10:23:38 PM UTC 24 |
9251693978 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.1805353720 |
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Oct 14 10:23:37 PM UTC 24 |
Oct 14 10:23:40 PM UTC 24 |
2042977437 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.707395412 |
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Oct 14 10:23:30 PM UTC 24 |
Oct 14 10:23:40 PM UTC 24 |
2192134142 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.3818767207 |
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Oct 14 10:23:30 PM UTC 24 |
Oct 14 10:23:42 PM UTC 24 |
2512239726 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.151449740 |
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Oct 14 10:23:33 PM UTC 24 |
Oct 14 10:23:46 PM UTC 24 |
2835576594 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2911981892 |
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Oct 14 10:23:31 PM UTC 24 |
Oct 14 10:23:48 PM UTC 24 |
3201910611 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1490768042 |
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Oct 14 10:17:08 PM UTC 24 |
Oct 14 10:23:48 PM UTC 24 |
130856476342 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3706186195 |
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Oct 14 10:19:51 PM UTC 24 |
Oct 14 10:23:52 PM UTC 24 |
89423328002 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.955454622 |
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Oct 14 10:23:36 PM UTC 24 |
Oct 14 10:23:52 PM UTC 24 |
62922685816 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3122811363 |
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Oct 14 10:22:05 PM UTC 24 |
Oct 14 10:23:53 PM UTC 24 |
124704316588 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3355635078 |
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Oct 14 10:22:26 PM UTC 24 |
Oct 14 10:23:55 PM UTC 24 |
124838423012 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.3116194846 |
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Oct 14 10:21:54 PM UTC 24 |
Oct 14 10:23:55 PM UTC 24 |
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| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.4127152842 |
|
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Oct 14 10:23:29 PM UTC 24 |
Oct 14 10:23:56 PM UTC 24 |
10327188277 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.467084717 |
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Oct 14 10:23:37 PM UTC 24 |
Oct 14 10:23:57 PM UTC 24 |
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| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.641208666 |
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Oct 14 10:23:36 PM UTC 24 |
Oct 14 10:24:01 PM UTC 24 |
3953869654 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.112788531 |
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Oct 14 10:20:51 PM UTC 24 |
Oct 14 10:24:04 PM UTC 24 |
71311373992 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.3911274006 |
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Oct 14 10:21:01 PM UTC 24 |
Oct 14 10:24:06 PM UTC 24 |
64671778378 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1191868667 |
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Oct 14 10:19:20 PM UTC 24 |
Oct 14 10:24:06 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.3405517169 |
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Oct 14 10:22:28 PM UTC 24 |
Oct 14 10:24:09 PM UTC 24 |
81536812198 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.333719710 |
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Oct 14 10:22:54 PM UTC 24 |
Oct 14 10:24:14 PM UTC 24 |
328767122086 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.4256064726 |
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Oct 14 10:22:16 PM UTC 24 |
Oct 14 10:24:16 PM UTC 24 |
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| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2317438977 |
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Oct 14 10:23:38 PM UTC 24 |
Oct 14 10:24:21 PM UTC 24 |
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| T118 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.601671877 |
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Oct 14 10:21:10 PM UTC 24 |
Oct 14 10:24:28 PM UTC 24 |
121882549401 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4235574554 |
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Oct 14 10:23:49 PM UTC 24 |
Oct 14 10:24:38 PM UTC 24 |
35610140266 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2436220311 |
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Oct 14 10:23:42 PM UTC 24 |
Oct 14 10:24:39 PM UTC 24 |
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| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1522384687 |
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Oct 14 10:23:56 PM UTC 24 |
Oct 14 10:24:40 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2811698213 |
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Oct 14 10:23:29 PM UTC 24 |
Oct 14 10:24:44 PM UTC 24 |
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| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.4189177003 |
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Oct 14 10:23:09 PM UTC 24 |
Oct 14 10:24:45 PM UTC 24 |
96456157032 ps |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3468923683 |
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Oct 14 10:24:17 PM UTC 24 |
Oct 14 10:24:47 PM UTC 24 |
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Oct 14 10:23:47 PM UTC 24 |
Oct 14 10:24:50 PM UTC 24 |
72894228234 ps |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1796513109 |
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Oct 14 10:24:10 PM UTC 24 |
Oct 14 10:24:54 PM UTC 24 |
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| T331 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.170197956 |
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Oct 14 10:23:36 PM UTC 24 |
Oct 14 10:25:00 PM UTC 24 |
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| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.772877824 |
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Oct 14 10:23:49 PM UTC 24 |
Oct 14 10:25:00 PM UTC 24 |
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Oct 14 10:23:41 PM UTC 24 |
Oct 14 10:25:00 PM UTC 24 |
45693989288 ps |
| T336 |
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Oct 14 10:22:44 PM UTC 24 |
Oct 14 10:25:01 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2973001274 |
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Oct 14 10:24:07 PM UTC 24 |
Oct 14 10:25:10 PM UTC 24 |
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Oct 14 10:23:53 PM UTC 24 |
Oct 14 10:25:14 PM UTC 24 |
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| T762 |
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Oct 14 10:24:40 PM UTC 24 |
Oct 14 10:25:14 PM UTC 24 |
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Oct 14 10:22:46 PM UTC 24 |
Oct 14 10:25:16 PM UTC 24 |
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Oct 14 10:24:38 PM UTC 24 |
Oct 14 10:25:16 PM UTC 24 |
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Oct 14 10:25:04 PM UTC 24 |
Oct 14 10:25:24 PM UTC 24 |
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Oct 14 10:23:54 PM UTC 24 |
Oct 14 10:25:30 PM UTC 24 |
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Oct 14 10:21:30 PM UTC 24 |
Oct 14 10:25:31 PM UTC 24 |
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Oct 14 10:19:31 PM UTC 24 |
Oct 14 10:25:33 PM UTC 24 |
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Oct 14 10:23:49 PM UTC 24 |
Oct 14 10:25:37 PM UTC 24 |
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Oct 14 10:25:01 PM UTC 24 |
Oct 14 10:25:37 PM UTC 24 |
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Oct 14 10:17:58 PM UTC 24 |
Oct 14 10:25:39 PM UTC 24 |
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Oct 14 10:24:15 PM UTC 24 |
Oct 14 10:25:45 PM UTC 24 |
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Oct 14 10:24:22 PM UTC 24 |
Oct 14 10:25:45 PM UTC 24 |
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Oct 14 10:23:37 PM UTC 24 |
Oct 14 10:25:48 PM UTC 24 |
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Oct 14 10:25:15 PM UTC 24 |
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Oct 14 10:25:17 PM UTC 24 |
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Oct 14 10:22:47 PM UTC 24 |
Oct 14 10:25:49 PM UTC 24 |
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Oct 14 10:25:15 PM UTC 24 |
Oct 14 10:25:50 PM UTC 24 |
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Oct 14 10:23:56 PM UTC 24 |
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Oct 14 10:14:08 PM UTC 24 |
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Oct 14 10:21:53 PM UTC 24 |
Oct 14 10:25:56 PM UTC 24 |
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Oct 14 10:23:53 PM UTC 24 |
Oct 14 10:26:00 PM UTC 24 |
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Oct 14 10:22:55 PM UTC 24 |
Oct 14 10:26:06 PM UTC 24 |
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Oct 14 10:24:51 PM UTC 24 |
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Oct 14 10:25:02 PM UTC 24 |
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Oct 14 10:23:41 PM UTC 24 |
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Oct 14 10:24:07 PM UTC 24 |
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Oct 14 10:24:55 PM UTC 24 |
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Oct 14 10:22:32 PM UTC 24 |
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Oct 14 10:22:03 PM UTC 24 |
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Oct 14 10:25:16 PM UTC 24 |
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Oct 14 10:23:58 PM UTC 24 |
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Oct 14 10:25:04 PM UTC 24 |
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220459566355 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2051246043 |
|
|
Oct 14 10:23:39 PM UTC 24 |
Oct 14 10:27:21 PM UTC 24 |
128686992554 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.473091456 |
|
|
Oct 14 10:24:02 PM UTC 24 |
Oct 14 10:27:22 PM UTC 24 |
75744013884 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1207140923 |
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|
Oct 14 10:23:06 PM UTC 24 |
Oct 14 10:27:55 PM UTC 24 |
85389459834 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.660471501 |
|
|
Oct 14 10:23:38 PM UTC 24 |
Oct 14 10:28:06 PM UTC 24 |
88429794272 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3491769240 |
|
|
Oct 14 10:25:01 PM UTC 24 |
Oct 14 10:28:11 PM UTC 24 |
74207671583 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1097342005 |
|
|
Oct 14 10:20:35 PM UTC 24 |
Oct 14 10:28:15 PM UTC 24 |
156346117797 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.3007753723 |
|
|
Oct 14 10:23:33 PM UTC 24 |
Oct 14 10:28:23 PM UTC 24 |
197317777991 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2780262988 |
|
|
Oct 14 10:23:18 PM UTC 24 |
Oct 14 10:28:53 PM UTC 24 |
155160975728 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1998066692 |
|
|
Oct 14 10:23:27 PM UTC 24 |
Oct 14 10:30:06 PM UTC 24 |
123280047361 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.957091352 |
|
|
Oct 14 10:21:41 PM UTC 24 |
Oct 14 10:30:15 PM UTC 24 |
136751062774 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3428439877 |
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|
Oct 14 10:24:41 PM UTC 24 |
Oct 14 10:33:38 PM UTC 24 |
141860144497 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3926980646 |
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|
Oct 14 10:25:11 PM UTC 24 |
Oct 14 10:33:45 PM UTC 24 |
148997866358 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3876984846 |
|
|
Oct 14 10:13:36 PM UTC 24 |
Oct 14 10:45:17 PM UTC 24 |
655229613558 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.1200354858 |
|
|
Oct 14 10:20:22 PM UTC 24 |
Oct 14 11:06:20 PM UTC 24 |
835421349107 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.564079432 |
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|
Oct 14 10:19:58 PM UTC 24 |
Oct 14 11:12:01 PM UTC 24 |
1089615449738 ps |