Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.33	99.18	96.99	100.00	100.00	98.67	99.71	93.78

Total test records in report: 919

T803	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1937886027	Feb 08 10:08:43 AM UTC 25	Feb 08 10:36:15 AM UTC 25	536694226089 ps
T190	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1654046093	Feb 08 10:11:26 AM UTC 25	Feb 08 10:37:02 AM UTC 25	536513786601 ps
T804	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1578366585	Feb 08 10:14:31 AM UTC 25	Feb 08 10:44:16 AM UTC 25	616505701001 ps
T805	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1158480118	Feb 08 10:12:09 AM UTC 25	Feb 08 11:00:02 AM UTC 25	1023306499535 ps
T33	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.689520360	Feb 08 10:18:01 AM UTC 25	Feb 08 10:18:10 AM UTC 25	2068369192 ps
T806	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.720398685	Feb 08 10:18:06 AM UTC 25	Feb 08 10:18:12 AM UTC 25	2029382324 ps
T388	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1139401827	Feb 08 10:18:06 AM UTC 25	Feb 08 10:18:15 AM UTC 25	4053934336 ps
T34	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.830091598	Feb 08 10:18:07 AM UTC 25	Feb 08 10:18:16 AM UTC 25	2076978842 ps
T35	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4123088781	Feb 08 10:18:11 AM UTC 25	Feb 08 10:18:17 AM UTC 25	2720688429 ps
T36	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3152207448	Feb 08 10:18:12 AM UTC 25	Feb 08 10:18:21 AM UTC 25	2048648452 ps
T37	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.162139694	Feb 08 10:18:16 AM UTC 25	Feb 08 10:18:21 AM UTC 25	2115292210 ps
T18	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1394229024	Feb 08 10:18:11 AM UTC 25	Feb 08 10:18:26 AM UTC 25	10074425896 ps
T102	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.765638070	Feb 08 10:18:12 AM UTC 25	Feb 08 10:18:27 AM UTC 25	2096565615 ps
T807	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.160305510	Feb 08 10:18:15 AM UTC 25	Feb 08 10:18:28 AM UTC 25	2009995031 ps
T38	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1975577777	Feb 08 10:18:18 AM UTC 25	Feb 08 10:18:29 AM UTC 25	2977160433 ps
T103	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2663892190	Feb 08 10:18:22 AM UTC 25	Feb 08 10:18:30 AM UTC 25	2564627554 ps
T808	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3609740614	Feb 08 10:18:23 AM UTC 25	Feb 08 10:18:31 AM UTC 25	2021115052 ps
T19	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3937575698	Feb 08 10:18:18 AM UTC 25	Feb 08 10:18:31 AM UTC 25	5141978254 ps
T20	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1986068011	Feb 08 10:18:29 AM UTC 25	Feb 08 10:18:33 AM UTC 25	4977993333 ps
T110	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1890623791	Feb 08 10:18:19 AM UTC 25	Feb 08 10:18:34 AM UTC 25	2064168684 ps
T111	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098418553	Feb 08 10:18:30 AM UTC 25	Feb 08 10:18:35 AM UTC 25	2273121491 ps
T809	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3049595927	Feb 08 10:18:31 AM UTC 25	Feb 08 10:18:35 AM UTC 25	2068337315 ps
T406	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1261050613	Feb 08 10:18:25 AM UTC 25	Feb 08 10:18:37 AM UTC 25	2032000187 ps
T389	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.523979826	Feb 08 10:18:24 AM UTC 25	Feb 08 10:18:37 AM UTC 25	6032102060 ps
T390	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1253571873	Feb 08 10:18:15 AM UTC 25	Feb 08 10:18:37 AM UTC 25	4031592915 ps
T401	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.4109893056	Feb 08 10:18:32 AM UTC 25	Feb 08 10:18:38 AM UTC 25	2063980582 ps
T810	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4187118917	Feb 08 10:18:31 AM UTC 25	Feb 08 10:18:38 AM UTC 25	4050521590 ps
T391	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2881950953	Feb 08 10:18:28 AM UTC 25	Feb 08 10:18:39 AM UTC 25	3087666636 ps
T105	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2633721264	Feb 08 10:18:31 AM UTC 25	Feb 08 10:18:40 AM UTC 25	23829486439 ps
T811	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1371064544	Feb 08 10:18:38 AM UTC 25	Feb 08 10:18:42 AM UTC 25	2094869859 ps
T112	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.775258367	Feb 08 10:18:30 AM UTC 25	Feb 08 10:18:42 AM UTC 25	2135914319 ps
T463	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3044311819	Feb 08 10:18:37 AM UTC 25	Feb 08 10:18:46 AM UTC 25	2055030518 ps
T465	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3062086392	Feb 08 10:18:35 AM UTC 25	Feb 08 10:18:49 AM UTC 25	2503734324 ps
T466	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1947479455	Feb 08 10:18:41 AM UTC 25	Feb 08 10:18:50 AM UTC 25	2052571862 ps
T464	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1171476214	Feb 08 10:18:40 AM UTC 25	Feb 08 10:18:50 AM UTC 25	3523925686 ps
T104	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.317714917	Feb 08 10:18:37 AM UTC 25	Feb 08 10:18:50 AM UTC 25	2065868689 ps
T113	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3318659068	Feb 08 10:18:41 AM UTC 25	Feb 08 10:18:50 AM UTC 25	2643993745 ps
T402	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2305914319	Feb 08 10:18:39 AM UTC 25	Feb 08 10:18:51 AM UTC 25	2025261206 ps
T403	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2727040529	Feb 08 10:18:36 AM UTC 25	Feb 08 10:18:53 AM UTC 25	10020721860 ps
T404	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2619863097	Feb 08 10:18:40 AM UTC 25	Feb 08 10:19:11 AM UTC 25	9759764164 ps
T405	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2251686199	Feb 08 10:18:46 AM UTC 25	Feb 08 10:18:54 AM UTC 25	2049391417 ps
T106	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2527373867	Feb 08 10:18:42 AM UTC 25	Feb 08 10:18:55 AM UTC 25	22665140515 ps
T392	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3483935108	Feb 08 10:18:51 AM UTC 25	Feb 08 10:18:56 AM UTC 25	2099752263 ps
T812	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.793284184	Feb 08 10:18:44 AM UTC 25	Feb 08 10:18:56 AM UTC 25	2015855515 ps
T813	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1597588153	Feb 08 10:18:38 AM UTC 25	Feb 08 10:18:57 AM UTC 25	4033968692 ps
T814	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.807389308	Feb 08 10:18:51 AM UTC 25	Feb 08 10:18:58 AM UTC 25	2173495890 ps
T468	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3862615783	Feb 08 10:18:56 AM UTC 25	Feb 08 10:19:00 AM UTC 25	2185274483 ps
T107	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3670694020	Feb 08 10:18:13 AM UTC 25	Feb 08 10:19:00 AM UTC 25	22322336659 ps
T114	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3294070613	Feb 08 10:18:50 AM UTC 25	Feb 08 10:19:01 AM UTC 25	2047185188 ps
T815	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3428675547	Feb 08 10:18:51 AM UTC 25	Feb 08 10:19:01 AM UTC 25	4830171360 ps
T816	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2219023902	Feb 08 10:18:49 AM UTC 25	Feb 08 10:19:02 AM UTC 25	2070602040 ps
T817	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3314990629	Feb 08 10:19:01 AM UTC 25	Feb 08 10:19:12 AM UTC 25	2040036622 ps
T818	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.494234677	Feb 08 10:18:52 AM UTC 25	Feb 08 10:19:03 AM UTC 25	2054265227 ps
T819	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4156843007	Feb 08 10:18:57 AM UTC 25	Feb 08 10:19:03 AM UTC 25	2043497693 ps
T820	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2114517610	Feb 08 10:18:50 AM UTC 25	Feb 08 10:19:03 AM UTC 25	2015510567 ps
T821	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3395936362	Feb 08 10:18:57 AM UTC 25	Feb 08 10:19:04 AM UTC 25	2113481869 ps
T393	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3526708768	Feb 08 10:18:18 AM UTC 25	Feb 08 10:19:04 AM UTC 25	14036196214 ps
T822	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1042193673	Feb 08 10:18:55 AM UTC 25	Feb 08 10:19:05 AM UTC 25	2012930891 ps
T823	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3534191080	Feb 08 10:18:59 AM UTC 25	Feb 08 10:19:07 AM UTC 25	2016956544 ps
T394	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1775551304	Feb 08 10:19:02 AM UTC 25	Feb 08 10:19:08 AM UTC 25	2067023635 ps
T824	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.764376503	Feb 08 10:19:01 AM UTC 25	Feb 08 10:19:09 AM UTC 25	2049563238 ps
T825	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.747365449	Feb 08 10:19:05 AM UTC 25	Feb 08 10:19:09 AM UTC 25	2035949734 ps
T826	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.269003184	Feb 08 10:19:05 AM UTC 25	Feb 08 10:19:09 AM UTC 25	2119245977 ps
T827	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3630742420	Feb 08 10:19:02 AM UTC 25	Feb 08 10:19:09 AM UTC 25	2021835837 ps
T828	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3388329143	Feb 08 10:19:00 AM UTC 25	Feb 08 10:19:09 AM UTC 25	2033606929 ps
T829	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3142073330	Feb 08 10:19:02 AM UTC 25	Feb 08 10:19:10 AM UTC 25	8050194902 ps
T395	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2867245528	Feb 08 10:19:05 AM UTC 25	Feb 08 10:19:10 AM UTC 25	2068482575 ps
T830	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2054390471	Feb 08 10:19:05 AM UTC 25	Feb 08 10:19:11 AM UTC 25	2271267777 ps
T831	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3670315799	Feb 08 10:18:57 AM UTC 25	Feb 08 10:19:15 AM UTC 25	9279120520 ps
T456	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2611452403	Feb 08 10:18:38 AM UTC 25	Feb 08 10:19:16 AM UTC 25	22278241656 ps
T832	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.696259766	Feb 08 10:19:08 AM UTC 25	Feb 08 10:19:16 AM UTC 25	2121720857 ps
T833	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1328709420	Feb 08 10:19:09 AM UTC 25	Feb 08 10:19:16 AM UTC 25	2404551548 ps
T834	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3215877956	Feb 08 10:19:06 AM UTC 25	Feb 08 10:19:16 AM UTC 25	5119772339 ps
T835	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1020631166	Feb 08 10:19:12 AM UTC 25	Feb 08 10:19:17 AM UTC 25	2054560936 ps
T836	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.793727168	Feb 08 10:19:10 AM UTC 25	Feb 08 10:19:17 AM UTC 25	2115324288 ps
T837	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.245517586	Feb 08 10:19:13 AM UTC 25	Feb 08 10:19:19 AM UTC 25	2096902361 ps
T838	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1889258843	Feb 08 10:19:10 AM UTC 25	Feb 08 10:19:20 AM UTC 25	2013328472 ps
T839	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1096241070	Feb 08 10:19:10 AM UTC 25	Feb 08 10:19:20 AM UTC 25	2034101592 ps
T396	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3735075634	Feb 08 10:19:13 AM UTC 25	Feb 08 10:19:21 AM UTC 25	2052502238 ps
T840	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1736802828	Feb 08 10:19:17 AM UTC 25	Feb 08 10:19:22 AM UTC 25	2017275777 ps
T841	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3560568841	Feb 08 10:19:17 AM UTC 25	Feb 08 10:19:23 AM UTC 25	2111869923 ps
T460	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.450938997	Feb 08 10:18:04 AM UTC 25	Feb 08 10:19:23 AM UTC 25	42623362298 ps
T842	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2488059143	Feb 08 10:19:15 AM UTC 25	Feb 08 10:19:23 AM UTC 25	2165460325 ps
T843	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2645993988	Feb 08 10:19:20 AM UTC 25	Feb 08 10:19:24 AM UTC 25	2181893574 ps
T844	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3797872901	Feb 08 10:19:17 AM UTC 25	Feb 08 10:19:24 AM UTC 25	2376704025 ps
T845	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.391028283	Feb 08 10:19:17 AM UTC 25	Feb 08 10:19:25 AM UTC 25	5265184507 ps
T846	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1289726199	Feb 08 10:19:10 AM UTC 25	Feb 08 10:19:25 AM UTC 25	2046308100 ps
T847	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.537546690	Feb 08 10:19:01 AM UTC 25	Feb 08 10:19:26 AM UTC 25	22281925553 ps
T848	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2823049285	Feb 08 10:19:16 AM UTC 25	Feb 08 10:19:26 AM UTC 25	22523779973 ps
T849	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1703222282	Feb 08 10:19:18 AM UTC 25	Feb 08 10:19:26 AM UTC 25	2013457615 ps
T850	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2973782509	Feb 08 10:19:00 AM UTC 25	Feb 08 10:19:26 AM UTC 25	8174638307 ps
T851	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2397958631	Feb 08 10:19:09 AM UTC 25	Feb 08 10:19:27 AM UTC 25	22889794665 ps
T852	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.652662013	Feb 08 10:19:22 AM UTC 25	Feb 08 10:19:28 AM UTC 25	2130644793 ps
T853	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1698233267	Feb 08 10:19:17 AM UTC 25	Feb 08 10:19:28 AM UTC 25	2036832620 ps
T854	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3357230858	Feb 08 10:19:10 AM UTC 25	Feb 08 10:19:29 AM UTC 25	5489283142 ps
T855	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3662718672	Feb 08 10:19:25 AM UTC 25	Feb 08 10:19:29 AM UTC 25	2044487689 ps
T856	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2607595421	Feb 08 10:19:24 AM UTC 25	Feb 08 10:19:30 AM UTC 25	2026349052 ps
T857	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328486483	Feb 08 10:19:26 AM UTC 25	Feb 08 10:19:31 AM UTC 25	2113471121 ps
T397	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1510223317	Feb 08 10:19:26 AM UTC 25	Feb 08 10:19:31 AM UTC 25	2078314257 ps
T399	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.205705951	Feb 08 10:19:24 AM UTC 25	Feb 08 10:19:32 AM UTC 25	2060140941 ps
T858	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.468977328	Feb 08 10:19:24 AM UTC 25	Feb 08 10:19:32 AM UTC 25	2079905563 ps
T859	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1248014138	Feb 08 10:19:22 AM UTC 25	Feb 08 10:19:33 AM UTC 25	2185881176 ps
T860	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1871587390	Feb 08 10:19:25 AM UTC 25	Feb 08 10:19:33 AM UTC 25	2071831061 ps
T861	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1035116021	Feb 08 10:19:29 AM UTC 25	Feb 08 10:19:33 AM UTC 25	2034905566 ps
T862	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3457966260	Feb 08 10:19:26 AM UTC 25	Feb 08 10:19:34 AM UTC 25	4514176969 ps
T863	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3051860025	Feb 08 10:19:27 AM UTC 25	Feb 08 10:19:34 AM UTC 25	2703622757 ps
T864	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3792228863	Feb 08 10:19:29 AM UTC 25	Feb 08 10:19:35 AM UTC 25	2047168771 ps
T865	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2876019993	Feb 08 10:19:32 AM UTC 25	Feb 08 10:19:35 AM UTC 25	2094852404 ps
T461	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2547129671	Feb 08 10:19:25 AM UTC 25	Feb 08 10:19:36 AM UTC 25	23000074718 ps
T866	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.806369596	Feb 08 10:19:30 AM UTC 25	Feb 08 10:19:38 AM UTC 25	2062192415 ps
T462	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2103302152	Feb 08 10:18:23 AM UTC 25	Feb 08 10:19:38 AM UTC 25	22248666178 ps
T867	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3835642062	Feb 08 10:19:20 AM UTC 25	Feb 08 10:19:39 AM UTC 25	10527800356 ps
T868	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.433250084	Feb 08 10:19:05 AM UTC 25	Feb 08 10:19:40 AM UTC 25	22221218207 ps
T400	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3458150625	Feb 08 10:19:32 AM UTC 25	Feb 08 10:19:40 AM UTC 25	2036568431 ps
T869	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.462046266	Feb 08 10:19:34 AM UTC 25	Feb 08 10:19:40 AM UTC 25	2068982243 ps
T870	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3416709626	Feb 08 10:19:37 AM UTC 25	Feb 08 10:19:41 AM UTC 25	2038839732 ps
T871	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.4183987094	Feb 08 10:19:33 AM UTC 25	Feb 08 10:19:41 AM UTC 25	2056518892 ps
T872	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.742343330	Feb 08 10:19:31 AM UTC 25	Feb 08 10:19:42 AM UTC 25	2052623356 ps
T873	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1367309972	Feb 08 10:19:34 AM UTC 25	Feb 08 10:19:42 AM UTC 25	2025946898 ps
T874	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4234621891	Feb 08 10:19:37 AM UTC 25	Feb 08 10:19:42 AM UTC 25	2018492075 ps
T875	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3845877068	Feb 08 10:19:34 AM UTC 25	Feb 08 10:19:42 AM UTC 25	2063786703 ps
T876	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3814064120	Feb 08 10:18:47 AM UTC 25	Feb 08 10:19:44 AM UTC 25	9981470578 ps
T877	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.360373605	Feb 08 10:19:40 AM UTC 25	Feb 08 10:19:44 AM UTC 25	2036226556 ps
T878	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2914328702	Feb 08 10:19:39 AM UTC 25	Feb 08 10:19:45 AM UTC 25	2029167202 ps
T879	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3403319947	Feb 08 10:19:22 AM UTC 25	Feb 08 10:19:45 AM UTC 25	22284109397 ps
T880	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.556892947	Feb 08 10:19:34 AM UTC 25	Feb 08 10:19:46 AM UTC 25	9378565209 ps
T881	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.559283376	Feb 08 10:19:33 AM UTC 25	Feb 08 10:19:46 AM UTC 25	2041216190 ps
T882	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2582644298	Feb 08 10:19:41 AM UTC 25	Feb 08 10:19:47 AM UTC 25	2017971679 ps
T883	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1001404393	Feb 08 10:19:41 AM UTC 25	Feb 08 10:19:47 AM UTC 25	2041567526 ps
T884	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1352980172	Feb 08 10:19:44 AM UTC 25	Feb 08 10:19:47 AM UTC 25	2058050446 ps
T885	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.822684595	Feb 08 10:19:43 AM UTC 25	Feb 08 10:19:48 AM UTC 25	2040858817 ps
T886	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2389659870	Feb 08 10:19:10 AM UTC 25	Feb 08 10:19:48 AM UTC 25	42500286728 ps
T887	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1399631652	Feb 08 10:19:42 AM UTC 25	Feb 08 10:19:48 AM UTC 25	2021024463 ps
T888	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2900891743	Feb 08 10:19:45 AM UTC 25	Feb 08 10:19:49 AM UTC 25	2025214846 ps
T889	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4115606518	Feb 08 10:19:41 AM UTC 25	Feb 08 10:19:49 AM UTC 25	2020391339 ps
T890	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.560264378	Feb 08 10:19:39 AM UTC 25	Feb 08 10:19:49 AM UTC 25	2011256508 ps
T891	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3538921661	Feb 08 10:19:40 AM UTC 25	Feb 08 10:19:49 AM UTC 25	2010482138 ps
T892	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1670754735	Feb 08 10:19:41 AM UTC 25	Feb 08 10:19:49 AM UTC 25	2013615317 ps
T893	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3750286033	Feb 08 10:19:46 AM UTC 25	Feb 08 10:19:50 AM UTC 25	2048470447 ps
T894	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4141793862	Feb 08 10:19:37 AM UTC 25	Feb 08 10:19:50 AM UTC 25	2012448483 ps
T895	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2815712621	Feb 08 10:19:44 AM UTC 25	Feb 08 10:19:50 AM UTC 25	2018257242 ps
T896	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3032628769	Feb 08 10:19:47 AM UTC 25	Feb 08 10:19:50 AM UTC 25	2086989872 ps
T897	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3191529838	Feb 08 10:19:41 AM UTC 25	Feb 08 10:19:51 AM UTC 25	2010739707 ps
T898	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1225725386	Feb 08 10:19:47 AM UTC 25	Feb 08 10:19:51 AM UTC 25	2097388764 ps
T899	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3525070832	Feb 08 10:19:47 AM UTC 25	Feb 08 10:19:51 AM UTC 25	2034290621 ps
T900	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1624701067	Feb 08 10:19:47 AM UTC 25	Feb 08 10:19:52 AM UTC 25	2037814448 ps
T901	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1779195321	Feb 08 10:19:44 AM UTC 25	Feb 08 10:19:52 AM UTC 25	2013002150 ps
T902	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.158759113	Feb 08 10:19:43 AM UTC 25	Feb 08 10:19:53 AM UTC 25	2014210749 ps
T903	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.283030298	Feb 08 10:19:48 AM UTC 25	Feb 08 10:19:54 AM UTC 25	2030833831 ps
T904	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3693646328	Feb 08 10:19:50 AM UTC 25	Feb 08 10:19:54 AM UTC 25	2050267181 ps
T905	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1799131764	Feb 08 10:19:45 AM UTC 25	Feb 08 10:19:54 AM UTC 25	2013353394 ps
T906	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.818974883	Feb 08 10:19:46 AM UTC 25	Feb 08 10:19:54 AM UTC 25	2011389360 ps
T907	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1716444690	Feb 08 10:19:48 AM UTC 25	Feb 08 10:19:55 AM UTC 25	2025611752 ps
T908	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3672845249	Feb 08 10:19:29 AM UTC 25	Feb 08 10:19:58 AM UTC 25	5117542424 ps
T909	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2307440927	Feb 08 10:19:48 AM UTC 25	Feb 08 10:19:59 AM UTC 25	2013884532 ps
T457	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.633521484	Feb 08 10:18:50 AM UTC 25	Feb 08 10:20:14 AM UTC 25	42405703968 ps
T910	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1790433789	Feb 08 10:19:24 AM UTC 25	Feb 08 10:20:01 AM UTC 25	9696313202 ps
T911	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1949517827	Feb 08 10:19:13 AM UTC 25	Feb 08 10:20:01 AM UTC 25	7473026633 ps
T912	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1748854391	Feb 08 10:18:27 AM UTC 25	Feb 08 10:20:22 AM UTC 25	39169012913 ps
T913	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1959412431	Feb 08 10:19:33 AM UTC 25	Feb 08 10:20:28 AM UTC 25	7475787913 ps
T914	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2514291698	Feb 08 10:19:31 AM UTC 25	Feb 08 10:20:36 AM UTC 25	22226144916 ps
T458	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2464084629	Feb 08 10:18:54 AM UTC 25	Feb 08 10:20:43 AM UTC 25	42467372569 ps
T915	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.839733690	Feb 08 10:19:34 AM UTC 25	Feb 08 10:20:54 AM UTC 25	22215018295 ps
T916	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2983516624	Feb 08 10:19:18 AM UTC 25	Feb 08 10:21:04 AM UTC 25	42515714045 ps
T917	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2775993132	Feb 08 10:18:58 AM UTC 25	Feb 08 10:21:48 AM UTC 25	42445245207 ps
T459	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1573086269	Feb 08 10:19:27 AM UTC 25	Feb 08 10:21:52 AM UTC 25	42372380440 ps
T918	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1515931126	Feb 08 10:18:34 AM UTC 25	Feb 08 10:24:34 AM UTC 25	73680111748 ps
T398	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1121364119	Feb 08 10:18:09 AM UTC 25	Feb 08 10:25:45 AM UTC 25	76068548997 ps
T919	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3382812050	Feb 08 10:18:39 AM UTC 25	Feb 08 10:27:22 AM UTC 25	76924717904 ps

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2704060435
Short name	T1
Test name
Test status
Simulation time	2545984863 ps
CPU time	3.44 seconds
Started	Feb 08 10:03:51 AM UTC 25
Finished	Feb 08 10:03:56 AM UTC 25
Peak memory	209864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704060435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2704060435
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.3284265803
Short name	T21
Test name
Test status
Simulation time	39282173385 ps
CPU time	79.17 seconds
Started	Feb 08 10:04:12 AM UTC 25
Finished	Feb 08 10:05:33 AM UTC 25
Peak memory	209924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284265803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3284265803
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2169574353
Short name	T25
Test name
Test status
Simulation time	2513368402 ps
CPU time	15.82 seconds
Started	Feb 08 10:03:52 AM UTC 25
Finished	Feb 08 10:04:10 AM UTC 25
Peak memory	209588 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169574353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2169574353
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.240570850
Short name	T54
Test name
Test status
Simulation time	44809021341 ps
CPU time	95.84 seconds
Started	Feb 08 10:05:08 AM UTC 25
Finished	Feb 08 10:06:46 AM UTC 25
Peak memory	226648 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=240570850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysr st_ctrl_stress_all_with_rand_reset.240570850
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3699659642
Short name	T40
Test name
Test status
Simulation time	147054128236 ps
CPU time	121.05 seconds
Started	Feb 08 10:03:55 AM UTC 25
Finished	Feb 08 10:05:58 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699659642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.3699659642
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1964462790
Short name	T357
Test name
Test status
Simulation time	67314780550 ps
CPU time	63.81 seconds
Started	Feb 08 10:07:51 AM UTC 25
Finished	Feb 08 10:08:57 AM UTC 25
Peak memory	226544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1964462790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sy srst_ctrl_stress_all_with_rand_reset.1964462790
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.1652396181
Short name	T56
Test name
Test status
Simulation time	39985500732 ps
CPU time	158.02 seconds
Started	Feb 08 10:03:56 AM UTC 25
Finished	Feb 08 10:06:37 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652396181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1652396181
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2527373867
Short name	T106
Test name
Test status
Simulation time	22665140515 ps
CPU time	11.03 seconds
Started	Feb 08 10:18:42 AM UTC 25
Finished	Feb 08 10:18:55 AM UTC 25
Peak memory	211576 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527373867 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.2527373867
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.4198068302
Short name	T140
Test name
Test status
Simulation time	166564203115 ps
CPU time	308.14 seconds
Started	Feb 08 10:06:33 AM UTC 25
Finished	Feb 08 10:11:45 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198068302 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.4198068302
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.4158748925
Short name	T32
Test name
Test status
Simulation time	100550621067 ps
CPU time	85.91 seconds
Started	Feb 08 10:04:14 AM UTC 25
Finished	Feb 08 10:05:42 AM UTC 25
Peak memory	220184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4158748925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sys rst_ctrl_stress_all_with_rand_reset.4158748925
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2693341825
Short name	T4
Test name
Test status
Simulation time	3332894727 ps
CPU time	2.78 seconds
Started	Feb 08 10:03:52 AM UTC 25
Finished	Feb 08 10:03:57 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693341825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2693341825
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.239090861
Short name	T219
Test name
Test status
Simulation time	133301636294 ps
CPU time	138.98 seconds
Started	Feb 08 10:08:31 AM UTC 25
Finished	Feb 08 10:10:53 AM UTC 25
Peak memory	220236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=239090861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sys rst_ctrl_stress_all_with_rand_reset.239090861
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.606151105
Short name	T180
Test name
Test status
Simulation time	665237771785 ps
CPU time	50.9 seconds
Started	Feb 08 10:13:32 AM UTC 25
Finished	Feb 08 10:14:25 AM UTC 25
Peak memory	220112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=606151105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sys rst_ctrl_stress_all_with_rand_reset.606151105
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2386114106
Short name	T361
Test name
Test status
Simulation time	167470045139 ps
CPU time	92.01 seconds
Started	Feb 08 10:07:37 AM UTC 25
Finished	Feb 08 10:09:11 AM UTC 25
Peak memory	210168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386114106 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.2386114106
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.2221896232
Short name	T117
Test name
Test status
Simulation time	16833016167 ps
CPU time	21.26 seconds
Started	Feb 08 10:09:01 AM UTC 25
Finished	Feb 08 10:09:25 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221896232 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.2221896232
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1126318832
Short name	T98
Test name
Test status
Simulation time	22010495347 ps
CPU time	76.94 seconds
Started	Feb 08 10:03:58 AM UTC 25
Finished	Feb 08 10:05:17 AM UTC 25
Peak memory	237592 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126318832 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1126318832
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1975577777
Short name	T38
Test name
Test status
Simulation time	2977160433 ps
CPU time	9.21 seconds
Started	Feb 08 10:18:18 AM UTC 25
Finished	Feb 08 10:18:29 AM UTC 25
Peak memory	211476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975577777 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.1975577777
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.3330602536
Short name	T189
Test name
Test status
Simulation time	3981934362 ps
CPU time	16.57 seconds
Started	Feb 08 10:09:14 AM UTC 25
Finished	Feb 08 10:09:33 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330602536 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.3330602536
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2185848038
Short name	T108
Test name
Test status
Simulation time	277733836194 ps
CPU time	75.16 seconds
Started	Feb 08 10:14:52 AM UTC 25
Finished	Feb 08 10:16:10 AM UTC 25
Peak memory	220324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2185848038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sy srst_ctrl_stress_all_with_rand_reset.2185848038
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3008461222
Short name	T185
Test name
Test status
Simulation time	45409374385 ps
CPU time	159.84 seconds
Started	Feb 08 10:06:45 AM UTC 25
Finished	Feb 08 10:09:28 AM UTC 25
Peak memory	209920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008461222 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.3008461222
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.800920655
Short name	T131
Test name
Test status
Simulation time	19843995511 ps
CPU time	66.74 seconds
Started	Feb 08 10:05:45 AM UTC 25
Finished	Feb 08 10:06:54 AM UTC 25
Peak memory	220144 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=800920655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysr st_ctrl_stress_all_with_rand_reset.800920655
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.681035254
Short name	T199
Test name
Test status
Simulation time	75478598978 ps
CPU time	243.21 seconds
Started	Feb 08 10:06:05 AM UTC 25
Finished	Feb 08 10:10:12 AM UTC 25
Peak memory	210248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681035254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.681035254
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.948688866
Short name	T100
Test name
Test status
Simulation time	38154679838 ps
CPU time	97.34 seconds
Started	Feb 08 10:06:06 AM UTC 25
Finished	Feb 08 10:07:46 AM UTC 25
Peak memory	220168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=948688866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysr st_ctrl_stress_all_with_rand_reset.948688866
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.700012435
Short name	T39
Test name
Test status
Simulation time	5642822907 ps
CPU time	7.61 seconds
Started	Feb 08 10:05:41 AM UTC 25
Finished	Feb 08 10:05:50 AM UTC 25
Peak memory	209756 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700012435 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.700012435
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.775258367
Short name	T112
Test name
Test status
Simulation time	2135914319 ps
CPU time	10.48 seconds
Started	Feb 08 10:18:30 AM UTC 25
Finished	Feb 08 10:18:42 AM UTC 25
Peak memory	211560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775258367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.775258367
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4213410601
Short name	T174
Test name
Test status
Simulation time	227759195608 ps
CPU time	107.68 seconds
Started	Feb 08 10:05:31 AM UTC 25
Finished	Feb 08 10:07:21 AM UTC 25
Peak memory	209892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213410601 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.4213410601
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.4207751869
Short name	T14
Test name
Test status
Simulation time	2062170735 ps
CPU time	6.11 seconds
Started	Feb 08 10:03:51 AM UTC 25
Finished	Feb 08 10:03:59 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207751869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.4207751869
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.751099421
Short name	T127
Test name
Test status
Simulation time	68775778271 ps
CPU time	56.22 seconds
Started	Feb 08 10:09:15 AM UTC 25
Finished	Feb 08 10:10:14 AM UTC 25
Peak memory	226324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=751099421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sys rst_ctrl_stress_all_with_rand_reset.751099421
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2770100148
Short name	T45
Test name
Test status
Simulation time	3693054618 ps
CPU time	2.96 seconds
Started	Feb 08 10:05:07 AM UTC 25
Finished	Feb 08 10:05:11 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770100148 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.2770100148
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.2031623479
Short name	T334
Test name
Test status
Simulation time	166665287952 ps
CPU time	32.22 seconds
Started	Feb 08 10:14:32 AM UTC 25
Finished	Feb 08 10:15:06 AM UTC 25
Peak memory	210092 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031623479 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.2031623479
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.2890658889
Short name	T192
Test name
Test status
Simulation time	5614599394 ps
CPU time	10.34 seconds
Started	Feb 08 10:08:30 AM UTC 25
Finished	Feb 08 10:08:42 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890658889 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.2890658889
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.4139842874
Short name	T431
Test name
Test status
Simulation time	168983042561 ps
CPU time	186.04 seconds
Started	Feb 08 10:10:13 AM UTC 25
Finished	Feb 08 10:13:22 AM UTC 25
Peak memory	209748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139842874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.4139842874
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.2629042347
Short name	T215
Test name
Test status
Simulation time	4509132813 ps
CPU time	7.9 seconds
Started	Feb 08 10:08:43 AM UTC 25
Finished	Feb 08 10:08:52 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629042347 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.2629042347
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.93382107
Short name	T26
Test name
Test status
Simulation time	2508350430 ps
CPU time	10.36 seconds
Started	Feb 08 10:04:04 AM UTC 25
Finished	Feb 08 10:04:16 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93382107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.93382107
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2633721264
Short name	T105
Test name
Test status
Simulation time	23829486439 ps
CPU time	7.42 seconds
Started	Feb 08 10:18:31 AM UTC 25
Finished	Feb 08 10:18:40 AM UTC 25
Peak memory	211548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633721264 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.2633721264
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2828458533
Short name	T474
Test name
Test status
Simulation time	21351596414 ps
CPU time	70.32 seconds
Started	Feb 08 10:07:18 AM UTC 25
Finished	Feb 08 10:08:30 AM UTC 25
Peak memory	210056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828458533 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.2828458533
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1796463440
Short name	T178
Test name
Test status
Simulation time	192839983652 ps
CPU time	157.6 seconds
Started	Feb 08 10:04:45 AM UTC 25
Finished	Feb 08 10:07:26 AM UTC 25
Peak memory	220100 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1796463440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sys rst_ctrl_stress_all_with_rand_reset.1796463440
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2137073025
Short name	T74
Test name
Test status
Simulation time	2013384693 ps
CPU time	7.08 seconds
Started	Feb 08 10:03:58 AM UTC 25
Finished	Feb 08 10:04:06 AM UTC 25
Peak memory	209640 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137073025 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.2137073025
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1394229024
Short name	T18
Test name
Test status
Simulation time	10074425896 ps
CPU time	13.89 seconds
Started	Feb 08 10:18:11 AM UTC 25
Finished	Feb 08 10:18:26 AM UTC 25
Peak memory	211368 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394229024 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.1394229024
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1654046093
Short name	T190
Test name
Test status
Simulation time	536513786601 ps
CPU time	1519.4 seconds
Started	Feb 08 10:11:26 AM UTC 25
Finished	Feb 08 10:37:02 AM UTC 25
Peak memory	212620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654046093 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.1654046093
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3181496944
Short name	T350
Test name
Test status
Simulation time	62077930879 ps
CPU time	94.22 seconds
Started	Feb 08 10:08:58 AM UTC 25
Finished	Feb 08 10:10:34 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181496944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.3181496944
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1944847450
Short name	T191
Test name
Test status
Simulation time	48557547476 ps
CPU time	122.55 seconds
Started	Feb 08 10:08:03 AM UTC 25
Finished	Feb 08 10:10:08 AM UTC 25
Peak memory	226548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1944847450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sy srst_ctrl_stress_all_with_rand_reset.1944847450
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3670694020
Short name	T107
Test name
Test status
Simulation time	22322336659 ps
CPU time	45.54 seconds
Started	Feb 08 10:18:13 AM UTC 25
Finished	Feb 08 10:19:00 AM UTC 25
Peak memory	211420 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670694020 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.3670694020
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3612463776
Short name	T272
Test name
Test status
Simulation time	174590505009 ps
CPU time	275.61 seconds
Started	Feb 08 10:08:07 AM UTC 25
Finished	Feb 08 10:12:47 AM UTC 25
Peak memory	210152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612463776 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.3612463776
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2403155902
Short name	T115
Test name
Test status
Simulation time	26386855464 ps
CPU time	42.18 seconds
Started	Feb 08 10:06:33 AM UTC 25
Finished	Feb 08 10:07:17 AM UTC 25
Peak memory	226400 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2403155902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sys rst_ctrl_stress_all_with_rand_reset.2403155902
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.2503577946
Short name	T414
Test name
Test status
Simulation time	126607862515 ps
CPU time	391.67 seconds
Started	Feb 08 10:09:32 AM UTC 25
Finished	Feb 08 10:16:08 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503577946 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.2503577946
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2707715321
Short name	T411
Test name
Test status
Simulation time	138495726193 ps
CPU time	49.11 seconds
Started	Feb 08 10:14:15 AM UTC 25
Finished	Feb 08 10:15:06 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707715321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.2707715321
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.602749498
Short name	T425
Test name
Test status
Simulation time	103549933900 ps
CPU time	78.61 seconds
Started	Feb 08 10:16:07 AM UTC 25
Finished	Feb 08 10:17:28 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602749498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.602749498
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.733328271
Short name	T27
Test name
Test status
Simulation time	3228276057 ps
CPU time	9.75 seconds
Started	Feb 08 10:04:07 AM UTC 25
Finished	Feb 08 10:04:19 AM UTC 25
Peak memory	210008 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733328271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.733328271
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3305109608
Short name	T92
Test name
Test status
Simulation time	86534399527 ps
CPU time	65.37 seconds
Started	Feb 08 10:07:16 AM UTC 25
Finished	Feb 08 10:08:23 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305109608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.3305109608
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.797333609
Short name	T422
Test name
Test status
Simulation time	89837978491 ps
CPU time	256.06 seconds
Started	Feb 08 10:11:47 AM UTC 25
Finished	Feb 08 10:16:07 AM UTC 25
Peak memory	209900 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797333609 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.797333609
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.812490484
Short name	T413
Test name
Test status
Simulation time	150340350949 ps
CPU time	133.37 seconds
Started	Feb 08 10:15:55 AM UTC 25
Finished	Feb 08 10:18:11 AM UTC 25
Peak memory	209892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812490484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.812490484
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.2616864731
Short name	T51
Test name
Test status
Simulation time	7979638153 ps
CPU time	6.91 seconds
Started	Feb 08 10:04:47 AM UTC 25
Finished	Feb 08 10:04:56 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616864731 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.2616864731
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3137151281
Short name	T231
Test name
Test status
Simulation time	2805867084 ps
CPU time	7.6 seconds
Started	Feb 08 10:11:47 AM UTC 25
Finished	Feb 08 10:11:56 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137151281 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.3137151281
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.264116098
Short name	T261
Test name
Test status
Simulation time	11630515026 ps
CPU time	13.3 seconds
Started	Feb 08 10:14:36 AM UTC 25
Finished	Feb 08 10:14:51 AM UTC 25
Peak memory	209720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264116098 -assert nopostproc +UVM_TESTNAME=sysrst_ ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.264116098
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1175169097
Short name	T362
Test name
Test status
Simulation time	152734587273 ps
CPU time	159.71 seconds
Started	Feb 08 10:07:13 AM UTC 25
Finished	Feb 08 10:09:56 AM UTC 25
Peak memory	210220 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175169097 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.1175169097
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1558551204
Short name	T441
Test name
Test status
Simulation time	136693612265 ps
CPU time	81.23 seconds
Started	Feb 08 10:09:34 AM UTC 25
Finished	Feb 08 10:10:58 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558551204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.1558551204
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2657949315
Short name	T473
Test name
Test status
Simulation time	42427820198 ps
CPU time	80.96 seconds
Started	Feb 08 10:12:49 AM UTC 25
Finished	Feb 08 10:14:14 AM UTC 25
Peak memory	209980 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657949315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.2657949315
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1863892970
Short name	T329
Test name
Test status
Simulation time	123667003487 ps
CPU time	297.47 seconds
Started	Feb 08 10:05:26 AM UTC 25
Finished	Feb 08 10:10:28 AM UTC 25
Peak memory	210300 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863892970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.1863892970
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.427179634
Short name	T444
Test name
Test status
Simulation time	120505882753 ps
CPU time	116.67 seconds
Started	Feb 08 10:14:27 AM UTC 25
Finished	Feb 08 10:16:26 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427179634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.427179634
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3690742458
Short name	T450
Test name
Test status
Simulation time	103841463513 ps
CPU time	181.67 seconds
Started	Feb 08 10:16:08 AM UTC 25
Finished	Feb 08 10:19:14 AM UTC 25
Peak memory	210236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690742458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.3690742458
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1936961067
Short name	T439
Test name
Test status
Simulation time	80153150146 ps
CPU time	249.48 seconds
Started	Feb 08 10:16:12 AM UTC 25
Finished	Feb 08 10:20:26 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936961067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.1936961067
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1573086269
Short name	T459
Test name
Test status
Simulation time	42372380440 ps
CPU time	141.86 seconds
Started	Feb 08 10:19:27 AM UTC 25
Finished	Feb 08 10:21:52 AM UTC 25
Peak memory	211576 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573086269 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.1573086269
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.1258074251
Short name	T22
Test name
Test status
Simulation time	2457481696 ps
CPU time	12.65 seconds
Started	Feb 08 10:03:51 AM UTC 25
Finished	Feb 08 10:04:05 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258074251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1258074251
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2974392462
Short name	T324
Test name
Test status
Simulation time	26831879596 ps
CPU time	134.45 seconds
Started	Feb 08 10:08:43 AM UTC 25
Finished	Feb 08 10:11:00 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974392462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.2974392462
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.904906819
Short name	T171
Test name
Test status
Simulation time	272213803751 ps
CPU time	164.94 seconds
Started	Feb 08 10:08:43 AM UTC 25
Finished	Feb 08 10:11:31 AM UTC 25
Peak memory	226428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=904906819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sys rst_ctrl_stress_all_with_rand_reset.904906819
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.563978863
Short name	T204
Test name
Test status
Simulation time	40265017779 ps
CPU time	117.17 seconds
Started	Feb 08 10:10:13 AM UTC 25
Finished	Feb 08 10:12:13 AM UTC 25
Peak memory	220072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=563978863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sys rst_ctrl_stress_all_with_rand_reset.563978863
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1469764401
Short name	T297
Test name
Test status
Simulation time	147569747095 ps
CPU time	222.52 seconds
Started	Feb 08 10:10:40 AM UTC 25
Finished	Feb 08 10:14:26 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469764401 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.1469764401
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1574445950
Short name	T365
Test name
Test status
Simulation time	580809488421 ps
CPU time	159.04 seconds
Started	Feb 08 10:10:42 AM UTC 25
Finished	Feb 08 10:13:24 AM UTC 25
Peak memory	220260 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1574445950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sy srst_ctrl_stress_all_with_rand_reset.1574445950
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.250160691
Short name	T274
Test name
Test status
Simulation time	86138024910 ps
CPU time	101.14 seconds
Started	Feb 08 10:11:03 AM UTC 25
Finished	Feb 08 10:12:47 AM UTC 25
Peak memory	209900 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250160691 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.250160691
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1356656267
Short name	T172
Test name
Test status
Simulation time	515345470876 ps
CPU time	328.7 seconds
Started	Feb 08 10:14:44 AM UTC 25
Finished	Feb 08 10:20:17 AM UTC 25
Peak memory	220260 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1356656267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sy srst_ctrl_stress_all_with_rand_reset.1356656267
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3385500421
Short name	T426
Test name
Test status
Simulation time	70777296826 ps
CPU time	124.27 seconds
Started	Feb 08 10:17:32 AM UTC 25
Finished	Feb 08 10:19:39 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385500421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.3385500421
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1903604343
Short name	T344
Test name
Test status
Simulation time	91989199909 ps
CPU time	70.48 seconds
Started	Feb 08 10:17:44 AM UTC 25
Finished	Feb 08 10:18:56 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903604343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.1903604343
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.765638070
Short name	T102
Test name
Test status
Simulation time	2096565615 ps
CPU time	13.19 seconds
Started	Feb 08 10:18:12 AM UTC 25
Finished	Feb 08 10:18:27 AM UTC 25
Peak memory	211488 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765638070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.765638070
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4123088781
Short name	T35
Test name
Test status
Simulation time	2720688429 ps
CPU time	4.89 seconds
Started	Feb 08 10:18:11 AM UTC 25
Finished	Feb 08 10:18:17 AM UTC 25
Peak memory	211260 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123088781 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.4123088781
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1121364119
Short name	T398
Test name
Test status
Simulation time	76068548997 ps
CPU time	450.69 seconds
Started	Feb 08 10:18:09 AM UTC 25
Finished	Feb 08 10:25:45 AM UTC 25
Peak memory	212736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121364119 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.1121364119
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1139401827
Short name	T388
Test name
Test status
Simulation time	4053934336 ps
CPU time	6.77 seconds
Started	Feb 08 10:18:06 AM UTC 25
Finished	Feb 08 10:18:15 AM UTC 25
Peak memory	211092 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139401827 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.1139401827
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3152207448
Short name	T36
Test name
Test status
Simulation time	2048648452 ps
CPU time	8.11 seconds
Started	Feb 08 10:18:12 AM UTC 25
Finished	Feb 08 10:18:21 AM UTC 25
Peak memory	211304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 52207448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_r w_with_rand_reset.3152207448
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.830091598
Short name	T34
Test name
Test status
Simulation time	2076978842 ps
CPU time	6.63 seconds
Started	Feb 08 10:18:07 AM UTC 25
Finished	Feb 08 10:18:16 AM UTC 25
Peak memory	211156 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830091598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrs t_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.830091598
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.720398685
Short name	T806
Test name
Test status
Simulation time	2029382324 ps
CPU time	3.74 seconds
Started	Feb 08 10:18:06 AM UTC 25
Finished	Feb 08 10:18:12 AM UTC 25
Peak memory	210836 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720398685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.720398685
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.689520360
Short name	T33
Test name
Test status
Simulation time	2068369192 ps
CPU time	7.38 seconds
Started	Feb 08 10:18:01 AM UTC 25
Finished	Feb 08 10:18:10 AM UTC 25
Peak memory	211676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689520360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.689520360
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.450938997
Short name	T460
Test name
Test status
Simulation time	42623362298 ps
CPU time	76.14 seconds
Started	Feb 08 10:18:04 AM UTC 25
Finished	Feb 08 10:19:23 AM UTC 25
Peak memory	211496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450938997 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.450938997
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3526708768
Short name	T393
Test name
Test status
Simulation time	14036196214 ps
CPU time	43.5 seconds
Started	Feb 08 10:18:18 AM UTC 25
Finished	Feb 08 10:19:04 AM UTC 25
Peak memory	211456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526708768 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.3526708768
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1253571873
Short name	T390
Test name
Test status
Simulation time	4031592915 ps
CPU time	20.47 seconds
Started	Feb 08 10:18:15 AM UTC 25
Finished	Feb 08 10:18:37 AM UTC 25
Peak memory	211240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253571873 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.1253571873
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1890623791
Short name	T110
Test name
Test status
Simulation time	2064168684 ps
CPU time	12.3 seconds
Started	Feb 08 10:18:19 AM UTC 25
Finished	Feb 08 10:18:34 AM UTC 25
Peak memory	211440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18 90623791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_r w_with_rand_reset.1890623791
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.162139694
Short name	T37
Test name
Test status
Simulation time	2115292210 ps
CPU time	3.69 seconds
Started	Feb 08 10:18:16 AM UTC 25
Finished	Feb 08 10:18:21 AM UTC 25
Peak memory	211364 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162139694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrs t_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.162139694
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.160305510
Short name	T807
Test name
Test status
Simulation time	2009995031 ps
CPU time	11.05 seconds
Started	Feb 08 10:18:15 AM UTC 25
Finished	Feb 08 10:18:28 AM UTC 25
Peak memory	210552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160305510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.160305510
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3937575698
Short name	T19
Test name
Test status
Simulation time	5141978254 ps
CPU time	11.2 seconds
Started	Feb 08 10:18:18 AM UTC 25
Finished	Feb 08 10:18:31 AM UTC 25
Peak memory	211692 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937575698 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.3937575698
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.696259766
Short name	T832
Test name
Test status
Simulation time	2121720857 ps
CPU time	6.01 seconds
Started	Feb 08 10:19:08 AM UTC 25
Finished	Feb 08 10:19:16 AM UTC 25
Peak memory	211376 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69 6259766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_r w_with_rand_reset.696259766
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2867245528
Short name	T395
Test name
Test status
Simulation time	2068482575 ps
CPU time	3.81 seconds
Started	Feb 08 10:19:05 AM UTC 25
Finished	Feb 08 10:19:10 AM UTC 25
Peak memory	211164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867245528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.2867245528
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.747365449
Short name	T825
Test name
Test status
Simulation time	2035949734 ps
CPU time	2.84 seconds
Started	Feb 08 10:19:05 AM UTC 25
Finished	Feb 08 10:19:09 AM UTC 25
Peak memory	211204 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747365449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.747365449
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3215877956
Short name	T834
Test name
Test status
Simulation time	5119772339 ps
CPU time	8.68 seconds
Started	Feb 08 10:19:06 AM UTC 25
Finished	Feb 08 10:19:16 AM UTC 25
Peak memory	211668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215877956 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.3215877956
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2054390471
Short name	T830
Test name
Test status
Simulation time	2271267777 ps
CPU time	5.02 seconds
Started	Feb 08 10:19:05 AM UTC 25
Finished	Feb 08 10:19:11 AM UTC 25
Peak memory	211760 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054390471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.2054390471
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.433250084
Short name	T868
Test name
Test status
Simulation time	22221218207 ps
CPU time	33.14 seconds
Started	Feb 08 10:19:05 AM UTC 25
Finished	Feb 08 10:19:40 AM UTC 25
Peak memory	211604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433250084 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.433250084
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1096241070
Short name	T839
Test name
Test status
Simulation time	2034101592 ps
CPU time	7.8 seconds
Started	Feb 08 10:19:10 AM UTC 25
Finished	Feb 08 10:19:20 AM UTC 25
Peak memory	211360 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10 96241070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_ rw_with_rand_reset.1096241070
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1289726199
Short name	T846
Test name
Test status
Simulation time	2046308100 ps
CPU time	12.29 seconds
Started	Feb 08 10:19:10 AM UTC 25
Finished	Feb 08 10:19:25 AM UTC 25
Peak memory	211300 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289726199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.1289726199
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1889258843
Short name	T838
Test name
Test status
Simulation time	2013328472 ps
CPU time	7.67 seconds
Started	Feb 08 10:19:10 AM UTC 25
Finished	Feb 08 10:19:20 AM UTC 25
Peak memory	211288 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889258843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.1889258843
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3357230858
Short name	T854
Test name
Test status
Simulation time	5489283142 ps
CPU time	16.33 seconds
Started	Feb 08 10:19:10 AM UTC 25
Finished	Feb 08 10:19:29 AM UTC 25
Peak memory	211448 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357230858 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.3357230858
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1328709420
Short name	T833
Test name
Test status
Simulation time	2404551548 ps
CPU time	5.08 seconds
Started	Feb 08 10:19:09 AM UTC 25
Finished	Feb 08 10:19:16 AM UTC 25
Peak memory	211756 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328709420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.1328709420
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2397958631
Short name	T851
Test name
Test status
Simulation time	22889794665 ps
CPU time	16.23 seconds
Started	Feb 08 10:19:09 AM UTC 25
Finished	Feb 08 10:19:27 AM UTC 25
Peak memory	211572 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397958631 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.2397958631
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.245517586
Short name	T837
Test name
Test status
Simulation time	2096902361 ps
CPU time	4.21 seconds
Started	Feb 08 10:19:13 AM UTC 25
Finished	Feb 08 10:19:19 AM UTC 25
Peak memory	211312 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24 5517586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_r w_with_rand_reset.245517586
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3735075634
Short name	T396
Test name
Test status
Simulation time	2052502238 ps
CPU time	6.18 seconds
Started	Feb 08 10:19:13 AM UTC 25
Finished	Feb 08 10:19:21 AM UTC 25
Peak memory	211236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735075634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.3735075634
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1020631166
Short name	T835
Test name
Test status
Simulation time	2054560936 ps
CPU time	2.91 seconds
Started	Feb 08 10:19:12 AM UTC 25
Finished	Feb 08 10:19:17 AM UTC 25
Peak memory	211024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020631166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.1020631166
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1949517827
Short name	T911
Test name
Test status
Simulation time	7473026633 ps
CPU time	45.28 seconds
Started	Feb 08 10:19:13 AM UTC 25
Finished	Feb 08 10:20:01 AM UTC 25
Peak memory	211556 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949517827 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.1949517827
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.793727168
Short name	T836
Test name
Test status
Simulation time	2115324288 ps
CPU time	4.23 seconds
Started	Feb 08 10:19:10 AM UTC 25
Finished	Feb 08 10:19:17 AM UTC 25
Peak memory	211700 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793727168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.793727168
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2389659870
Short name	T886
Test name
Test status
Simulation time	42500286728 ps
CPU time	34.94 seconds
Started	Feb 08 10:19:10 AM UTC 25
Finished	Feb 08 10:19:48 AM UTC 25
Peak memory	211696 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389659870 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.2389659870
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1698233267
Short name	T853
Test name
Test status
Simulation time	2036832620 ps
CPU time	8.77 seconds
Started	Feb 08 10:19:17 AM UTC 25
Finished	Feb 08 10:19:28 AM UTC 25
Peak memory	211368 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 98233267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_ rw_with_rand_reset.1698233267
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3560568841
Short name	T841
Test name
Test status
Simulation time	2111869923 ps
CPU time	3.87 seconds
Started	Feb 08 10:19:17 AM UTC 25
Finished	Feb 08 10:19:23 AM UTC 25
Peak memory	211160 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560568841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.3560568841
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1736802828
Short name	T840
Test name
Test status
Simulation time	2017275777 ps
CPU time	3.63 seconds
Started	Feb 08 10:19:17 AM UTC 25
Finished	Feb 08 10:19:22 AM UTC 25
Peak memory	211196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736802828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.1736802828
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.391028283
Short name	T845
Test name
Test status
Simulation time	5265184507 ps
CPU time	5.67 seconds
Started	Feb 08 10:19:17 AM UTC 25
Finished	Feb 08 10:19:25 AM UTC 25
Peak memory	211556 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391028283 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.391028283
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2488059143
Short name	T842
Test name
Test status
Simulation time	2165460325 ps
CPU time	6.27 seconds
Started	Feb 08 10:19:15 AM UTC 25
Finished	Feb 08 10:19:23 AM UTC 25
Peak memory	211760 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488059143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.2488059143
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2823049285
Short name	T848
Test name
Test status
Simulation time	22523779973 ps
CPU time	7.84 seconds
Started	Feb 08 10:19:16 AM UTC 25
Finished	Feb 08 10:19:26 AM UTC 25
Peak memory	211560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823049285 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.2823049285
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.652662013
Short name	T852
Test name
Test status
Simulation time	2130644793 ps
CPU time	4.33 seconds
Started	Feb 08 10:19:22 AM UTC 25
Finished	Feb 08 10:19:28 AM UTC 25
Peak memory	211444 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65 2662013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_r w_with_rand_reset.652662013
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2645993988
Short name	T843
Test name
Test status
Simulation time	2181893574 ps
CPU time	1.85 seconds
Started	Feb 08 10:19:20 AM UTC 25
Finished	Feb 08 10:19:24 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645993988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.2645993988
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1703222282
Short name	T849
Test name
Test status
Simulation time	2013457615 ps
CPU time	6.54 seconds
Started	Feb 08 10:19:18 AM UTC 25
Finished	Feb 08 10:19:26 AM UTC 25
Peak memory	210684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703222282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.1703222282
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3835642062
Short name	T867
Test name
Test status
Simulation time	10527800356 ps
CPU time	16.43 seconds
Started	Feb 08 10:19:20 AM UTC 25
Finished	Feb 08 10:19:39 AM UTC 25
Peak memory	211628 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835642062 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.3835642062
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3797872901
Short name	T844
Test name
Test status
Simulation time	2376704025 ps
CPU time	5.34 seconds
Started	Feb 08 10:19:17 AM UTC 25
Finished	Feb 08 10:19:24 AM UTC 25
Peak memory	221696 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797872901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.3797872901
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2983516624
Short name	T916
Test name
Test status
Simulation time	42515714045 ps
CPU time	103.05 seconds
Started	Feb 08 10:19:18 AM UTC 25
Finished	Feb 08 10:21:04 AM UTC 25
Peak memory	211440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983516624 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.2983516624
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.468977328
Short name	T858
Test name
Test status
Simulation time	2079905563 ps
CPU time	6.55 seconds
Started	Feb 08 10:19:24 AM UTC 25
Finished	Feb 08 10:19:32 AM UTC 25
Peak memory	227660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46 8977328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_r w_with_rand_reset.468977328
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.205705951
Short name	T399
Test name
Test status
Simulation time	2060140941 ps
CPU time	6.45 seconds
Started	Feb 08 10:19:24 AM UTC 25
Finished	Feb 08 10:19:32 AM UTC 25
Peak memory	211236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205705951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrs t_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.205705951
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2607595421
Short name	T856
Test name
Test status
Simulation time	2026349052 ps
CPU time	4.26 seconds
Started	Feb 08 10:19:24 AM UTC 25
Finished	Feb 08 10:19:30 AM UTC 25
Peak memory	210904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607595421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.2607595421
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1790433789
Short name	T910
Test name
Test status
Simulation time	9696313202 ps
CPU time	34.85 seconds
Started	Feb 08 10:19:24 AM UTC 25
Finished	Feb 08 10:20:01 AM UTC 25
Peak memory	211580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790433789 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.1790433789
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1248014138
Short name	T859
Test name
Test status
Simulation time	2185881176 ps
CPU time	9.5 seconds
Started	Feb 08 10:19:22 AM UTC 25
Finished	Feb 08 10:19:33 AM UTC 25
Peak memory	211608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248014138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.1248014138
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3403319947
Short name	T879
Test name
Test status
Simulation time	22284109397 ps
CPU time	21.31 seconds
Started	Feb 08 10:19:22 AM UTC 25
Finished	Feb 08 10:19:45 AM UTC 25
Peak memory	211552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403319947 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.3403319947
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328486483
Short name	T857
Test name
Test status
Simulation time	2113471121 ps
CPU time	2.83 seconds
Started	Feb 08 10:19:26 AM UTC 25
Finished	Feb 08 10:19:31 AM UTC 25
Peak memory	211504 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 28486483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_ rw_with_rand_reset.2328486483
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1510223317
Short name	T397
Test name
Test status
Simulation time	2078314257 ps
CPU time	3.58 seconds
Started	Feb 08 10:19:26 AM UTC 25
Finished	Feb 08 10:19:31 AM UTC 25
Peak memory	211164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510223317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.1510223317
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3662718672
Short name	T855
Test name
Test status
Simulation time	2044487689 ps
CPU time	2.87 seconds
Started	Feb 08 10:19:25 AM UTC 25
Finished	Feb 08 10:19:29 AM UTC 25
Peak memory	211024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662718672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.3662718672
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3457966260
Short name	T862
Test name
Test status
Simulation time	4514176969 ps
CPU time	6.01 seconds
Started	Feb 08 10:19:26 AM UTC 25
Finished	Feb 08 10:19:34 AM UTC 25
Peak memory	211296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457966260 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.3457966260
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1871587390
Short name	T860
Test name
Test status
Simulation time	2071831061 ps
CPU time	6.49 seconds
Started	Feb 08 10:19:25 AM UTC 25
Finished	Feb 08 10:19:33 AM UTC 25
Peak memory	211372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871587390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.1871587390
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2547129671
Short name	T461
Test name
Test status
Simulation time	23000074718 ps
CPU time	9.1 seconds
Started	Feb 08 10:19:25 AM UTC 25
Finished	Feb 08 10:19:36 AM UTC 25
Peak memory	211640 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547129671 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.2547129671
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.806369596
Short name	T866
Test name
Test status
Simulation time	2062192415 ps
CPU time	6.5 seconds
Started	Feb 08 10:19:30 AM UTC 25
Finished	Feb 08 10:19:38 AM UTC 25
Peak memory	211304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80 6369596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_r w_with_rand_reset.806369596
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3792228863
Short name	T864
Test name
Test status
Simulation time	2047168771 ps
CPU time	5.03 seconds
Started	Feb 08 10:19:29 AM UTC 25
Finished	Feb 08 10:19:35 AM UTC 25
Peak memory	211288 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792228863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.3792228863
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1035116021
Short name	T861
Test name
Test status
Simulation time	2034905566 ps
CPU time	3.05 seconds
Started	Feb 08 10:19:29 AM UTC 25
Finished	Feb 08 10:19:33 AM UTC 25
Peak memory	210820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035116021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.1035116021
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3672845249
Short name	T908
Test name
Test status
Simulation time	5117542424 ps
CPU time	27.85 seconds
Started	Feb 08 10:19:29 AM UTC 25
Finished	Feb 08 10:19:58 AM UTC 25
Peak memory	211168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672845249 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.3672845249
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3051860025
Short name	T863
Test name
Test status
Simulation time	2703622757 ps
CPU time	4.55 seconds
Started	Feb 08 10:19:27 AM UTC 25
Finished	Feb 08 10:19:34 AM UTC 25
Peak memory	211820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051860025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.3051860025
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.559283376
Short name	T881
Test name
Test status
Simulation time	2041216190 ps
CPU time	11.32 seconds
Started	Feb 08 10:19:33 AM UTC 25
Finished	Feb 08 10:19:46 AM UTC 25
Peak memory	211444 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55 9283376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_r w_with_rand_reset.559283376
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3458150625
Short name	T400
Test name
Test status
Simulation time	2036568431 ps
CPU time	6.58 seconds
Started	Feb 08 10:19:32 AM UTC 25
Finished	Feb 08 10:19:40 AM UTC 25
Peak memory	211164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458150625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.3458150625
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2876019993
Short name	T865
Test name
Test status
Simulation time	2094852404 ps
CPU time	2.13 seconds
Started	Feb 08 10:19:32 AM UTC 25
Finished	Feb 08 10:19:35 AM UTC 25
Peak memory	210904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876019993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.2876019993
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1959412431
Short name	T913
Test name
Test status
Simulation time	7475787913 ps
CPU time	53.27 seconds
Started	Feb 08 10:19:33 AM UTC 25
Finished	Feb 08 10:20:28 AM UTC 25
Peak memory	211664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959412431 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.1959412431
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.742343330
Short name	T872
Test name
Test status
Simulation time	2052623356 ps
CPU time	9.24 seconds
Started	Feb 08 10:19:31 AM UTC 25
Finished	Feb 08 10:19:42 AM UTC 25
Peak memory	221584 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742343330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.742343330
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2514291698
Short name	T914
Test name
Test status
Simulation time	22226144916 ps
CPU time	62.93 seconds
Started	Feb 08 10:19:31 AM UTC 25
Finished	Feb 08 10:20:36 AM UTC 25
Peak memory	211576 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514291698 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.2514291698
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3845877068
Short name	T875
Test name
Test status
Simulation time	2063786703 ps
CPU time	5.88 seconds
Started	Feb 08 10:19:34 AM UTC 25
Finished	Feb 08 10:19:42 AM UTC 25
Peak memory	211436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 45877068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_ rw_with_rand_reset.3845877068
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.462046266
Short name	T869
Test name
Test status
Simulation time	2068982243 ps
CPU time	4.29 seconds
Started	Feb 08 10:19:34 AM UTC 25
Finished	Feb 08 10:19:40 AM UTC 25
Peak memory	211164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462046266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrs t_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.462046266
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1367309972
Short name	T873
Test name
Test status
Simulation time	2025946898 ps
CPU time	5.69 seconds
Started	Feb 08 10:19:34 AM UTC 25
Finished	Feb 08 10:19:42 AM UTC 25
Peak memory	210824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367309972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.1367309972
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.556892947
Short name	T880
Test name
Test status
Simulation time	9378565209 ps
CPU time	9.54 seconds
Started	Feb 08 10:19:34 AM UTC 25
Finished	Feb 08 10:19:46 AM UTC 25
Peak memory	211496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556892947 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.556892947
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.4183987094
Short name	T871
Test name
Test status
Simulation time	2056518892 ps
CPU time	5.92 seconds
Started	Feb 08 10:19:33 AM UTC 25
Finished	Feb 08 10:19:41 AM UTC 25
Peak memory	211560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183987094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.4183987094
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.839733690
Short name	T915
Test name
Test status
Simulation time	22215018295 ps
CPU time	77.19 seconds
Started	Feb 08 10:19:34 AM UTC 25
Finished	Feb 08 10:20:54 AM UTC 25
Peak memory	211572 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839733690 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.839733690
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2881950953
Short name	T391
Test name
Test status
Simulation time	3087666636 ps
CPU time	9.19 seconds
Started	Feb 08 10:18:28 AM UTC 25
Finished	Feb 08 10:18:39 AM UTC 25
Peak memory	211512 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881950953 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.2881950953
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1748854391
Short name	T912
Test name
Test status
Simulation time	39169012913 ps
CPU time	111.95 seconds
Started	Feb 08 10:18:27 AM UTC 25
Finished	Feb 08 10:20:22 AM UTC 25
Peak memory	211628 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748854391 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.1748854391
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.523979826
Short name	T389
Test name
Test status
Simulation time	6032102060 ps
CPU time	11.07 seconds
Started	Feb 08 10:18:24 AM UTC 25
Finished	Feb 08 10:18:37 AM UTC 25
Peak memory	211236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523979826 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression /sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.523979826
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098418553
Short name	T111
Test name
Test status
Simulation time	2273121491 ps
CPU time	3.32 seconds
Started	Feb 08 10:18:30 AM UTC 25
Finished	Feb 08 10:18:35 AM UTC 25
Peak memory	211376 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10 98418553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_r w_with_rand_reset.1098418553
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1261050613
Short name	T406
Test name
Test status
Simulation time	2032000187 ps
CPU time	10.13 seconds
Started	Feb 08 10:18:25 AM UTC 25
Finished	Feb 08 10:18:37 AM UTC 25
Peak memory	211360 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261050613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.1261050613
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3609740614
Short name	T808
Test name
Test status
Simulation time	2021115052 ps
CPU time	6.18 seconds
Started	Feb 08 10:18:23 AM UTC 25
Finished	Feb 08 10:18:31 AM UTC 25
Peak memory	211124 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609740614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.3609740614
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1986068011
Short name	T20
Test name
Test status
Simulation time	4977993333 ps
CPU time	2.38 seconds
Started	Feb 08 10:18:29 AM UTC 25
Finished	Feb 08 10:18:33 AM UTC 25
Peak memory	211408 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986068011 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.1986068011
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2663892190
Short name	T103
Test name
Test status
Simulation time	2564627554 ps
CPU time	6.6 seconds
Started	Feb 08 10:18:22 AM UTC 25
Finished	Feb 08 10:18:30 AM UTC 25
Peak memory	211760 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663892190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.2663892190
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2103302152
Short name	T462
Test name
Test status
Simulation time	22248666178 ps
CPU time	72.75 seconds
Started	Feb 08 10:18:23 AM UTC 25
Finished	Feb 08 10:19:38 AM UTC 25
Peak memory	211688 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103302152 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.2103302152
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3416709626
Short name	T870
Test name
Test status
Simulation time	2038839732 ps
CPU time	2.72 seconds
Started	Feb 08 10:19:37 AM UTC 25
Finished	Feb 08 10:19:41 AM UTC 25
Peak memory	211024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416709626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.3416709626
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4141793862
Short name	T894
Test name
Test status
Simulation time	2012448483 ps
CPU time	11.76 seconds
Started	Feb 08 10:19:37 AM UTC 25
Finished	Feb 08 10:19:50 AM UTC 25
Peak memory	211024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141793862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.4141793862
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4234621891
Short name	T874
Test name
Test status
Simulation time	2018492075 ps
CPU time	3.97 seconds
Started	Feb 08 10:19:37 AM UTC 25
Finished	Feb 08 10:19:42 AM UTC 25
Peak memory	210824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234621891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.4234621891
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.560264378
Short name	T890
Test name
Test status
Simulation time	2011256508 ps
CPU time	8.66 seconds
Started	Feb 08 10:19:39 AM UTC 25
Finished	Feb 08 10:19:49 AM UTC 25
Peak memory	210836 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560264378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.560264378
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2914328702
Short name	T878
Test name
Test status
Simulation time	2029167202 ps
CPU time	4.39 seconds
Started	Feb 08 10:19:39 AM UTC 25
Finished	Feb 08 10:19:45 AM UTC 25
Peak memory	210960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914328702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.2914328702
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.360373605
Short name	T877
Test name
Test status
Simulation time	2036226556 ps
CPU time	2.63 seconds
Started	Feb 08 10:19:40 AM UTC 25
Finished	Feb 08 10:19:44 AM UTC 25
Peak memory	210824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360373605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.360373605
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3538921661
Short name	T891
Test name
Test status
Simulation time	2010482138 ps
CPU time	7.68 seconds
Started	Feb 08 10:19:40 AM UTC 25
Finished	Feb 08 10:19:49 AM UTC 25
Peak memory	210884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538921661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.3538921661
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1001404393
Short name	T883
Test name
Test status
Simulation time	2041567526 ps
CPU time	3.44 seconds
Started	Feb 08 10:19:41 AM UTC 25
Finished	Feb 08 10:19:47 AM UTC 25
Peak memory	211164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001404393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.1001404393
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3191529838
Short name	T897
Test name
Test status
Simulation time	2010739707 ps
CPU time	7.41 seconds
Started	Feb 08 10:19:41 AM UTC 25
Finished	Feb 08 10:19:51 AM UTC 25
Peak memory	211240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191529838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.3191529838
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4115606518
Short name	T889
Test name
Test status
Simulation time	2020391339 ps
CPU time	5.64 seconds
Started	Feb 08 10:19:41 AM UTC 25
Finished	Feb 08 10:19:49 AM UTC 25
Peak memory	211276 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115606518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.4115606518
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3062086392
Short name	T465
Test name
Test status
Simulation time	2503734324 ps
CPU time	12.66 seconds
Started	Feb 08 10:18:35 AM UTC 25
Finished	Feb 08 10:18:49 AM UTC 25
Peak memory	211620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062086392 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.3062086392
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1515931126
Short name	T918
Test name
Test status
Simulation time	73680111748 ps
CPU time	355.47 seconds
Started	Feb 08 10:18:34 AM UTC 25
Finished	Feb 08 10:24:34 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515931126 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.1515931126
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4187118917
Short name	T810
Test name
Test status
Simulation time	4050521590 ps
CPU time	5.34 seconds
Started	Feb 08 10:18:31 AM UTC 25
Finished	Feb 08 10:18:38 AM UTC 25
Peak memory	211368 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187118917 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.4187118917
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3044311819
Short name	T463
Test name
Test status
Simulation time	2055030518 ps
CPU time	6.87 seconds
Started	Feb 08 10:18:37 AM UTC 25
Finished	Feb 08 10:18:46 AM UTC 25
Peak memory	211304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 44311819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_r w_with_rand_reset.3044311819
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.4109893056
Short name	T401
Test name
Test status
Simulation time	2063980582 ps
CPU time	3.7 seconds
Started	Feb 08 10:18:32 AM UTC 25
Finished	Feb 08 10:18:38 AM UTC 25
Peak memory	211156 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109893056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.4109893056
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3049595927
Short name	T809
Test name
Test status
Simulation time	2068337315 ps
CPU time	2.41 seconds
Started	Feb 08 10:18:31 AM UTC 25
Finished	Feb 08 10:18:35 AM UTC 25
Peak memory	210832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049595927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.3049595927
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2727040529
Short name	T403
Test name
Test status
Simulation time	10020721860 ps
CPU time	15.69 seconds
Started	Feb 08 10:18:36 AM UTC 25
Finished	Feb 08 10:18:53 AM UTC 25
Peak memory	211516 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727040529 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.2727040529
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2582644298
Short name	T882
Test name
Test status
Simulation time	2017971679 ps
CPU time	3.4 seconds
Started	Feb 08 10:19:41 AM UTC 25
Finished	Feb 08 10:19:47 AM UTC 25
Peak memory	211028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582644298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.2582644298
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1670754735
Short name	T892
Test name
Test status
Simulation time	2013615317 ps
CPU time	5.98 seconds
Started	Feb 08 10:19:41 AM UTC 25
Finished	Feb 08 10:19:49 AM UTC 25
Peak memory	210960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670754735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.1670754735
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1399631652
Short name	T887
Test name
Test status
Simulation time	2021024463 ps
CPU time	3.93 seconds
Started	Feb 08 10:19:42 AM UTC 25
Finished	Feb 08 10:19:48 AM UTC 25
Peak memory	211152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399631652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.1399631652
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.158759113
Short name	T902
Test name
Test status
Simulation time	2014210749 ps
CPU time	9.02 seconds
Started	Feb 08 10:19:43 AM UTC 25
Finished	Feb 08 10:19:53 AM UTC 25
Peak memory	210836 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158759113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.158759113
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.822684595
Short name	T885
Test name
Test status
Simulation time	2040858817 ps
CPU time	3.51 seconds
Started	Feb 08 10:19:43 AM UTC 25
Finished	Feb 08 10:19:48 AM UTC 25
Peak memory	211196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822684595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.822684595
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2815712621
Short name	T895
Test name
Test status
Simulation time	2018257242 ps
CPU time	4.95 seconds
Started	Feb 08 10:19:44 AM UTC 25
Finished	Feb 08 10:19:50 AM UTC 25
Peak memory	211224 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815712621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.2815712621
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1352980172
Short name	T884
Test name
Test status
Simulation time	2058050446 ps
CPU time	2.15 seconds
Started	Feb 08 10:19:44 AM UTC 25
Finished	Feb 08 10:19:47 AM UTC 25
Peak memory	211032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352980172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.1352980172
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1779195321
Short name	T901
Test name
Test status
Simulation time	2013002150 ps
CPU time	6.67 seconds
Started	Feb 08 10:19:44 AM UTC 25
Finished	Feb 08 10:19:52 AM UTC 25
Peak memory	210888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779195321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.1779195321
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1799131764
Short name	T905
Test name
Test status
Simulation time	2013353394 ps
CPU time	7.67 seconds
Started	Feb 08 10:19:45 AM UTC 25
Finished	Feb 08 10:19:54 AM UTC 25
Peak memory	211288 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799131764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.1799131764
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2900891743
Short name	T888
Test name
Test status
Simulation time	2025214846 ps
CPU time	2.7 seconds
Started	Feb 08 10:19:45 AM UTC 25
Finished	Feb 08 10:19:49 AM UTC 25
Peak memory	211220 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900891743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.2900891743
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1171476214
Short name	T464
Test name
Test status
Simulation time	3523925686 ps
CPU time	7.91 seconds
Started	Feb 08 10:18:40 AM UTC 25
Finished	Feb 08 10:18:50 AM UTC 25
Peak memory	211616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171476214 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.1171476214
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3382812050
Short name	T919
Test name
Test status
Simulation time	76924717904 ps
CPU time	515.73 seconds
Started	Feb 08 10:18:39 AM UTC 25
Finished	Feb 08 10:27:22 AM UTC 25
Peak memory	212476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382812050 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.3382812050
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1597588153
Short name	T813
Test name
Test status
Simulation time	4033968692 ps
CPU time	16.67 seconds
Started	Feb 08 10:18:38 AM UTC 25
Finished	Feb 08 10:18:57 AM UTC 25
Peak memory	211304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597588153 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.1597588153
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1947479455
Short name	T466
Test name
Test status
Simulation time	2052571862 ps
CPU time	6.74 seconds
Started	Feb 08 10:18:41 AM UTC 25
Finished	Feb 08 10:18:50 AM UTC 25
Peak memory	211192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 47479455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_r w_with_rand_reset.1947479455
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2305914319
Short name	T402
Test name
Test status
Simulation time	2025261206 ps
CPU time	10.33 seconds
Started	Feb 08 10:18:39 AM UTC 25
Finished	Feb 08 10:18:51 AM UTC 25
Peak memory	210964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305914319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.2305914319
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1371064544
Short name	T811
Test name
Test status
Simulation time	2094869859 ps
CPU time	2 seconds
Started	Feb 08 10:18:38 AM UTC 25
Finished	Feb 08 10:18:42 AM UTC 25
Peak memory	210928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371064544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.1371064544
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2619863097
Short name	T404
Test name
Test status
Simulation time	9759764164 ps
CPU time	29.29 seconds
Started	Feb 08 10:18:40 AM UTC 25
Finished	Feb 08 10:19:11 AM UTC 25
Peak memory	211496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619863097 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.2619863097
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.317714917
Short name	T104
Test name
Test status
Simulation time	2065868689 ps
CPU time	10.92 seconds
Started	Feb 08 10:18:37 AM UTC 25
Finished	Feb 08 10:18:50 AM UTC 25
Peak memory	211632 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317714917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.317714917
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2611452403
Short name	T456
Test name
Test status
Simulation time	22278241656 ps
CPU time	35.78 seconds
Started	Feb 08 10:18:38 AM UTC 25
Finished	Feb 08 10:19:16 AM UTC 25
Peak memory	211548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611452403 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.2611452403
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3750286033
Short name	T893
Test name
Test status
Simulation time	2048470447 ps
CPU time	2.14 seconds
Started	Feb 08 10:19:46 AM UTC 25
Finished	Feb 08 10:19:50 AM UTC 25
Peak memory	211020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750286033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.3750286033
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.818974883
Short name	T906
Test name
Test status
Simulation time	2011389360 ps
CPU time	6.67 seconds
Started	Feb 08 10:19:46 AM UTC 25
Finished	Feb 08 10:19:54 AM UTC 25
Peak memory	210892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818974883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.818974883
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1624701067
Short name	T900
Test name
Test status
Simulation time	2037814448 ps
CPU time	2.87 seconds
Started	Feb 08 10:19:47 AM UTC 25
Finished	Feb 08 10:19:52 AM UTC 25
Peak memory	211160 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624701067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.1624701067
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3525070832
Short name	T899
Test name
Test status
Simulation time	2034290621 ps
CPU time	2.61 seconds
Started	Feb 08 10:19:47 AM UTC 25
Finished	Feb 08 10:19:51 AM UTC 25
Peak memory	211192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525070832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.3525070832
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3032628769
Short name	T896
Test name
Test status
Simulation time	2086989872 ps
CPU time	1.58 seconds
Started	Feb 08 10:19:47 AM UTC 25
Finished	Feb 08 10:19:50 AM UTC 25
Peak memory	210360 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032628769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.3032628769
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1225725386
Short name	T898
Test name
Test status
Simulation time	2097388764 ps
CPU time	1.78 seconds
Started	Feb 08 10:19:47 AM UTC 25
Finished	Feb 08 10:19:51 AM UTC 25
Peak memory	210360 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225725386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.1225725386
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1716444690
Short name	T907
Test name
Test status
Simulation time	2025611752 ps
CPU time	4.92 seconds
Started	Feb 08 10:19:48 AM UTC 25
Finished	Feb 08 10:19:55 AM UTC 25
Peak memory	210904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716444690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.1716444690
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.283030298
Short name	T903
Test name
Test status
Simulation time	2030833831 ps
CPU time	3.3 seconds
Started	Feb 08 10:19:48 AM UTC 25
Finished	Feb 08 10:19:54 AM UTC 25
Peak memory	211024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283030298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.283030298
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2307440927
Short name	T909
Test name
Test status
Simulation time	2013884532 ps
CPU time	8.52 seconds
Started	Feb 08 10:19:48 AM UTC 25
Finished	Feb 08 10:19:59 AM UTC 25
Peak memory	210832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307440927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.2307440927
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3693646328
Short name	T904
Test name
Test status
Simulation time	2050267181 ps
CPU time	2.26 seconds
Started	Feb 08 10:19:50 AM UTC 25
Finished	Feb 08 10:19:54 AM UTC 25
Peak memory	211032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693646328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.3693646328
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2219023902
Short name	T816
Test name
Test status
Simulation time	2070602040 ps
CPU time	10.93 seconds
Started	Feb 08 10:18:49 AM UTC 25
Finished	Feb 08 10:19:02 AM UTC 25
Peak memory	211440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22 19023902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_r w_with_rand_reset.2219023902
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2251686199
Short name	T405
Test name
Test status
Simulation time	2049391417 ps
CPU time	6.41 seconds
Started	Feb 08 10:18:46 AM UTC 25
Finished	Feb 08 10:18:54 AM UTC 25
Peak memory	211236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251686199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.2251686199
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.793284184
Short name	T812
Test name
Test status
Simulation time	2015855515 ps
CPU time	10.9 seconds
Started	Feb 08 10:18:44 AM UTC 25
Finished	Feb 08 10:18:56 AM UTC 25
Peak memory	211028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793284184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.793284184
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3814064120
Short name	T876
Test name
Test status
Simulation time	9981470578 ps
CPU time	55.17 seconds
Started	Feb 08 10:18:47 AM UTC 25
Finished	Feb 08 10:19:44 AM UTC 25
Peak memory	211496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814064120 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.3814064120
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3318659068
Short name	T113
Test name
Test status
Simulation time	2643993745 ps
CPU time	7.15 seconds
Started	Feb 08 10:18:41 AM UTC 25
Finished	Feb 08 10:18:50 AM UTC 25
Peak memory	211452 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318659068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.3318659068
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.807389308
Short name	T814
Test name
Test status
Simulation time	2173495890 ps
CPU time	4.38 seconds
Started	Feb 08 10:18:51 AM UTC 25
Finished	Feb 08 10:18:58 AM UTC 25
Peak memory	211620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80 7389308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw _with_rand_reset.807389308
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3483935108
Short name	T392
Test name
Test status
Simulation time	2099752263 ps
CPU time	2.43 seconds
Started	Feb 08 10:18:51 AM UTC 25
Finished	Feb 08 10:18:56 AM UTC 25
Peak memory	211164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483935108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.3483935108
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2114517610
Short name	T820
Test name
Test status
Simulation time	2015510567 ps
CPU time	11.32 seconds
Started	Feb 08 10:18:50 AM UTC 25
Finished	Feb 08 10:19:03 AM UTC 25
Peak memory	210824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114517610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.2114517610
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3428675547
Short name	T815
Test name
Test status
Simulation time	4830171360 ps
CPU time	7.99 seconds
Started	Feb 08 10:18:51 AM UTC 25
Finished	Feb 08 10:19:01 AM UTC 25
Peak memory	211432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428675547 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.3428675547
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3294070613
Short name	T114
Test name
Test status
Simulation time	2047185188 ps
CPU time	8.55 seconds
Started	Feb 08 10:18:50 AM UTC 25
Finished	Feb 08 10:19:01 AM UTC 25
Peak memory	211584 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294070613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.3294070613
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.633521484
Short name	T457
Test name
Test status
Simulation time	42405703968 ps
CPU time	81.49 seconds
Started	Feb 08 10:18:50 AM UTC 25
Finished	Feb 08 10:20:14 AM UTC 25
Peak memory	211584 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633521484 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.633521484
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4156843007
Short name	T819
Test name
Test status
Simulation time	2043497693 ps
CPU time	4.86 seconds
Started	Feb 08 10:18:57 AM UTC 25
Finished	Feb 08 10:19:03 AM UTC 25
Peak memory	211304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 56843007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_r w_with_rand_reset.4156843007
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3862615783
Short name	T468
Test name
Test status
Simulation time	2185274483 ps
CPU time	2.63 seconds
Started	Feb 08 10:18:56 AM UTC 25
Finished	Feb 08 10:19:00 AM UTC 25
Peak memory	211232 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862615783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.3862615783
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1042193673
Short name	T822
Test name
Test status
Simulation time	2012930891 ps
CPU time	8.15 seconds
Started	Feb 08 10:18:55 AM UTC 25
Finished	Feb 08 10:19:05 AM UTC 25
Peak memory	210832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042193673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.1042193673
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3670315799
Short name	T831
Test name
Test status
Simulation time	9279120520 ps
CPU time	16.15 seconds
Started	Feb 08 10:18:57 AM UTC 25
Finished	Feb 08 10:19:15 AM UTC 25
Peak memory	211440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670315799 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.3670315799
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.494234677
Short name	T818
Test name
Test status
Simulation time	2054265227 ps
CPU time	8.75 seconds
Started	Feb 08 10:18:52 AM UTC 25
Finished	Feb 08 10:19:03 AM UTC 25
Peak memory	221632 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494234677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_bas e_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.494234677
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2464084629
Short name	T458
Test name
Test status
Simulation time	42467372569 ps
CPU time	105.75 seconds
Started	Feb 08 10:18:54 AM UTC 25
Finished	Feb 08 10:20:43 AM UTC 25
Peak memory	211748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464084629 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.2464084629
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.764376503
Short name	T824
Test name
Test status
Simulation time	2049563238 ps
CPU time	6.22 seconds
Started	Feb 08 10:19:01 AM UTC 25
Finished	Feb 08 10:19:09 AM UTC 25
Peak memory	211296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76 4376503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw _with_rand_reset.764376503
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3388329143
Short name	T828
Test name
Test status
Simulation time	2033606929 ps
CPU time	7.8 seconds
Started	Feb 08 10:19:00 AM UTC 25
Finished	Feb 08 10:19:09 AM UTC 25
Peak memory	211300 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388329143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.3388329143
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3534191080
Short name	T823
Test name
Test status
Simulation time	2016956544 ps
CPU time	6.66 seconds
Started	Feb 08 10:18:59 AM UTC 25
Finished	Feb 08 10:19:07 AM UTC 25
Peak memory	211032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534191080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.3534191080
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2973782509
Short name	T850
Test name
Test status
Simulation time	8174638307 ps
CPU time	24.67 seconds
Started	Feb 08 10:19:00 AM UTC 25
Finished	Feb 08 10:19:26 AM UTC 25
Peak memory	211468 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973782509 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.2973782509
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3395936362
Short name	T821
Test name
Test status
Simulation time	2113481869 ps
CPU time	5.03 seconds
Started	Feb 08 10:18:57 AM UTC 25
Finished	Feb 08 10:19:04 AM UTC 25
Peak memory	211648 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395936362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.3395936362
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2775993132
Short name	T917
Test name
Test status
Simulation time	42445245207 ps
CPU time	166.37 seconds
Started	Feb 08 10:18:58 AM UTC 25
Finished	Feb 08 10:21:48 AM UTC 25
Peak memory	211492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775993132 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.2775993132
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.269003184
Short name	T826
Test name
Test status
Simulation time	2119245977 ps
CPU time	3.01 seconds
Started	Feb 08 10:19:05 AM UTC 25
Finished	Feb 08 10:19:09 AM UTC 25
Peak memory	211564 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 9003184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw _with_rand_reset.269003184
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1775551304
Short name	T394
Test name
Test status
Simulation time	2067023635 ps
CPU time	3.96 seconds
Started	Feb 08 10:19:02 AM UTC 25
Finished	Feb 08 10:19:08 AM UTC 25
Peak memory	211152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775551304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.1775551304
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3630742420
Short name	T827
Test name
Test status
Simulation time	2021835837 ps
CPU time	5.2 seconds
Started	Feb 08 10:19:02 AM UTC 25
Finished	Feb 08 10:19:09 AM UTC 25
Peak memory	210968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630742420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.3630742420
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3142073330
Short name	T829
Test name
Test status
Simulation time	8050194902 ps
CPU time	5.76 seconds
Started	Feb 08 10:19:02 AM UTC 25
Finished	Feb 08 10:19:10 AM UTC 25
Peak memory	211620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142073330 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.3142073330
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3314990629
Short name	T817
Test name
Test status
Simulation time	2040036622 ps
CPU time	9.11 seconds
Started	Feb 08 10:19:01 AM UTC 25
Finished	Feb 08 10:19:12 AM UTC 25
Peak memory	211608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314990629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_ba se_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.3314990629
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.537546690
Short name	T847
Test name
Test status
Simulation time	22281925553 ps
CPU time	22.73 seconds
Started	Feb 08 10:19:01 AM UTC 25
Finished	Feb 08 10:19:26 AM UTC 25
Peak memory	211556 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537546690 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.537546690
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3725275141
Short name	T6
Test name
Test status
Simulation time	37895246315 ps
CPU time	23.57 seconds
Started	Feb 08 10:03:55 AM UTC 25
Finished	Feb 08 10:04:20 AM UTC 25
Peak memory	210056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725275141 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.3725275141
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1251689532
Short name	T2
Test name
Test status
Simulation time	2429943431 ps
CPU time	3.93 seconds
Started	Feb 08 10:03:51 AM UTC 25
Finished	Feb 08 10:03:57 AM UTC 25
Peak memory	209984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251689532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1251689532
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.521601682
Short name	T16
Test name
Test status
Simulation time	5192844740 ps
CPU time	7.07 seconds
Started	Feb 08 10:03:52 AM UTC 25
Finished	Feb 08 10:04:01 AM UTC 25
Peak memory	209696 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521601682 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.521601682
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2600256782
Short name	T3
Test name
Test status
Simulation time	2404869757 ps
CPU time	7.5 seconds
Started	Feb 08 10:03:55 AM UTC 25
Finished	Feb 08 10:04:04 AM UTC 25
Peak memory	209604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600256782 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.2600256782
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.88756479
Short name	T13
Test name
Test status
Simulation time	2619429737 ps
CPU time	4.82 seconds
Started	Feb 08 10:03:52 AM UTC 25
Finished	Feb 08 10:03:59 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88756479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.88756479
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.1332766611
Short name	T15
Test name
Test status
Simulation time	2114447241 ps
CPU time	6.79 seconds
Started	Feb 08 10:03:51 AM UTC 25
Finished	Feb 08 10:04:00 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332766611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.1332766611
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3173948645
Short name	T121
Test name
Test status
Simulation time	117049581077 ps
CPU time	218.82 seconds
Started	Feb 08 10:03:57 AM UTC 25
Finished	Feb 08 10:07:39 AM UTC 25
Peak memory	210176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173948645 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.3173948645
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1696365099
Short name	T55
Test name
Test status
Simulation time	65124855501 ps
CPU time	183.33 seconds
Started	Feb 08 10:03:56 AM UTC 25
Finished	Feb 08 10:07:02 AM UTC 25
Peak memory	224544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1696365099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sys rst_ctrl_stress_all_with_rand_reset.1696365099
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2073077456
Short name	T12
Test name
Test status
Simulation time	3733275986 ps
CPU time	2.06 seconds
Started	Feb 08 10:03:53 AM UTC 25
Finished	Feb 08 10:03:57 AM UTC 25
Peak memory	210000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073077456 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.2073077456
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3644963231
Short name	T66
Test name
Test status
Simulation time	2031932795 ps
CPU time	3.59 seconds
Started	Feb 08 10:04:21 AM UTC 25
Finished	Feb 08 10:04:26 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644963231 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.3644963231
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3661562224
Short name	T407
Test name
Test status
Simulation time	164590292915 ps
CPU time	494.21 seconds
Started	Feb 08 10:04:08 AM UTC 25
Finished	Feb 08 10:12:28 AM UTC 25
Peak memory	212560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661562224 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.3661562224
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3485297655
Short name	T31
Test name
Test status
Simulation time	2244886877 ps
CPU time	4.4 seconds
Started	Feb 08 10:04:00 AM UTC 25
Finished	Feb 08 10:04:06 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485297655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.3485297655
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2785729346
Short name	T7
Test name
Test status
Simulation time	2534022399 ps
CPU time	4.27 seconds
Started	Feb 08 10:04:01 AM UTC 25
Finished	Feb 08 10:04:07 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785729346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2785729346
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3322307893
Short name	T11
Test name
Test status
Simulation time	150090025068 ps
CPU time	43.59 seconds
Started	Feb 08 10:04:11 AM UTC 25
Finished	Feb 08 10:04:56 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322307893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.3322307893
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1889578550
Short name	T68
Test name
Test status
Simulation time	4094633236 ps
CPU time	23.69 seconds
Started	Feb 08 10:04:06 AM UTC 25
Finished	Feb 08 10:04:32 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889578550 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.1889578550
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3201499473
Short name	T8
Test name
Test status
Simulation time	3137648407 ps
CPU time	15.58 seconds
Started	Feb 08 10:04:08 AM UTC 25
Finished	Feb 08 10:04:25 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201499473 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.3201499473
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3117432393
Short name	T65
Test name
Test status
Simulation time	2614801966 ps
CPU time	14.94 seconds
Started	Feb 08 10:04:04 AM UTC 25
Finished	Feb 08 10:04:21 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117432393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.3117432393
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1746646007
Short name	T23
Test name
Test status
Simulation time	2490686228 ps
CPU time	4.9 seconds
Started	Feb 08 10:04:00 AM UTC 25
Finished	Feb 08 10:04:07 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746646007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1746646007
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.3683336824
Short name	T81
Test name
Test status
Simulation time	2025749365 ps
CPU time	6.93 seconds
Started	Feb 08 10:04:02 AM UTC 25
Finished	Feb 08 10:04:11 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683336824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3683336824
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.640603777
Short name	T94
Test name
Test status
Simulation time	42217731350 ps
CPU time	37.66 seconds
Started	Feb 08 10:04:19 AM UTC 25
Finished	Feb 08 10:04:58 AM UTC 25
Peak memory	239636 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640603777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.640603777
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1194253681
Short name	T17
Test name
Test status
Simulation time	2134517704 ps
CPU time	3.9 seconds
Started	Feb 08 10:03:58 AM UTC 25
Finished	Feb 08 10:04:03 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194253681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.1194253681
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2551132927
Short name	T28
Test name
Test status
Simulation time	13309435440 ps
CPU time	28.01 seconds
Started	Feb 08 10:04:17 AM UTC 25
Finished	Feb 08 10:04:46 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551132927 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.2551132927
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.884572565
Short name	T5
Test name
Test status
Simulation time	3446240732 ps
CPU time	4.44 seconds
Started	Feb 08 10:04:07 AM UTC 25
Finished	Feb 08 10:04:13 AM UTC 25
Peak memory	209704 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884572565 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.884572565
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.38330178
Short name	T245
Test name
Test status
Simulation time	2013181298 ps
CPU time	10.02 seconds
Started	Feb 08 10:07:19 AM UTC 25
Finished	Feb 08 10:07:30 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38330178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.38330178
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1140928418
Short name	T556
Test name
Test status
Simulation time	306335095244 ps
CPU time	252.84 seconds
Started	Feb 08 10:07:11 AM UTC 25
Finished	Feb 08 10:11:28 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140928418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1140928418
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.381506504
Short name	T489
Test name
Test status
Simulation time	5366385808 ps
CPU time	23.36 seconds
Started	Feb 08 10:07:10 AM UTC 25
Finished	Feb 08 10:07:35 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381506504 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.381506504
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2152178067
Short name	T125
Test name
Test status
Simulation time	3240105686 ps
CPU time	4.16 seconds
Started	Feb 08 10:07:15 AM UTC 25
Finished	Feb 08 10:07:20 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152178067 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.2152178067
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2476283010
Short name	T312
Test name
Test status
Simulation time	2623585415 ps
CPU time	4.61 seconds
Started	Feb 08 10:07:10 AM UTC 25
Finished	Feb 08 10:07:16 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476283010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2476283010
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.1822925926
Short name	T310
Test name
Test status
Simulation time	2487183025 ps
CPU time	6.69 seconds
Started	Feb 08 10:07:06 AM UTC 25
Finished	Feb 08 10:07:14 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822925926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1822925926
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1310590137
Short name	T311
Test name
Test status
Simulation time	2166998585 ps
CPU time	5.64 seconds
Started	Feb 08 10:07:08 AM UTC 25
Finished	Feb 08 10:07:15 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310590137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1310590137
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3776123180
Short name	T173
Test name
Test status
Simulation time	2508790708 ps
CPU time	8.47 seconds
Started	Feb 08 10:07:10 AM UTC 25
Finished	Feb 08 10:07:20 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776123180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3776123180
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.4069213391
Short name	T308
Test name
Test status
Simulation time	2132293575 ps
CPU time	3.78 seconds
Started	Feb 08 10:07:05 AM UTC 25
Finished	Feb 08 10:07:10 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069213391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.4069213391
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2883741994
Short name	T129
Test name
Test status
Simulation time	36185842359 ps
CPU time	54.03 seconds
Started	Feb 08 10:07:17 AM UTC 25
Finished	Feb 08 10:08:13 AM UTC 25
Peak memory	220192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2883741994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sy srst_ctrl_stress_all_with_rand_reset.2883741994
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3157106163
Short name	T97
Test name
Test status
Simulation time	3676662026 ps
CPU time	3.49 seconds
Started	Feb 08 10:07:13 AM UTC 25
Finished	Feb 08 10:07:18 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157106163 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.3157106163
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1732587187
Short name	T488
Test name
Test status
Simulation time	2073275120 ps
CPU time	2.26 seconds
Started	Feb 08 10:07:31 AM UTC 25
Finished	Feb 08 10:07:35 AM UTC 25
Peak memory	209592 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732587187 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.1732587187
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2270205902
Short name	T243
Test name
Test status
Simulation time	3449818757 ps
CPU time	3.84 seconds
Started	Feb 08 10:07:22 AM UTC 25
Finished	Feb 08 10:07:28 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270205902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2270205902
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3976745428
Short name	T363
Test name
Test status
Simulation time	120954014035 ps
CPU time	155.15 seconds
Started	Feb 08 10:07:26 AM UTC 25
Finished	Feb 08 10:10:04 AM UTC 25
Peak memory	209940 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976745428 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.3976745428
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1166095728
Short name	T327
Test name
Test status
Simulation time	47382851701 ps
CPU time	169.44 seconds
Started	Feb 08 10:07:28 AM UTC 25
Finished	Feb 08 10:10:20 AM UTC 25
Peak memory	209896 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166095728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.1166095728
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3721487616
Short name	T244
Test name
Test status
Simulation time	4151052332 ps
CPU time	4.02 seconds
Started	Feb 08 10:07:22 AM UTC 25
Finished	Feb 08 10:07:28 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721487616 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.3721487616
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.490341130
Short name	T47
Test name
Test status
Simulation time	3465733267 ps
CPU time	5.81 seconds
Started	Feb 08 10:07:27 AM UTC 25
Finished	Feb 08 10:07:34 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490341130 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.490341130
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.965934903
Short name	T487
Test name
Test status
Simulation time	2620813944 ps
CPU time	8.89 seconds
Started	Feb 08 10:07:21 AM UTC 25
Finished	Feb 08 10:07:32 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965934903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.965934903
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3553549383
Short name	T179
Test name
Test status
Simulation time	2489519692 ps
CPU time	4.65 seconds
Started	Feb 08 10:07:20 AM UTC 25
Finished	Feb 08 10:07:26 AM UTC 25
Peak memory	209776 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553549383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3553549383
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.770895636
Short name	T176
Test name
Test status
Simulation time	2251126133 ps
CPU time	2.77 seconds
Started	Feb 08 10:07:20 AM UTC 25
Finished	Feb 08 10:07:24 AM UTC 25
Peak memory	209676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770895636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.770895636
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2581906403
Short name	T490
Test name
Test status
Simulation time	2511890386 ps
CPU time	12.69 seconds
Started	Feb 08 10:07:21 AM UTC 25
Finished	Feb 08 10:07:36 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581906403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2581906403
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.4073006704
Short name	T177
Test name
Test status
Simulation time	2136519858 ps
CPU time	3.36 seconds
Started	Feb 08 10:07:20 AM UTC 25
Finished	Feb 08 10:07:25 AM UTC 25
Peak memory	209620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073006704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.4073006704
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2238104403
Short name	T123
Test name
Test status
Simulation time	15998313063 ps
CPU time	56.71 seconds
Started	Feb 08 10:07:29 AM UTC 25
Finished	Feb 08 10:08:27 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238104403 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.2238104403
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1988418124
Short name	T257
Test name
Test status
Simulation time	2021820380 ps
CPU time	3.03 seconds
Started	Feb 08 10:07:41 AM UTC 25
Finished	Feb 08 10:07:46 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988418124 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.1988418124
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3183694524
Short name	T253
Test name
Test status
Simulation time	3188591154 ps
CPU time	3.27 seconds
Started	Feb 08 10:07:36 AM UTC 25
Finished	Feb 08 10:07:40 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183694524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3183694524
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3156760497
Short name	T328
Test name
Test status
Simulation time	98489078735 ps
CPU time	139.57 seconds
Started	Feb 08 10:07:39 AM UTC 25
Finished	Feb 08 10:10:01 AM UTC 25
Peak memory	210232 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156760497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_with_pre_cond.3156760497
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2132646031
Short name	T497
Test name
Test status
Simulation time	3277529740 ps
CPU time	15.66 seconds
Started	Feb 08 10:07:36 AM UTC 25
Finished	Feb 08 10:07:53 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132646031 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.2132646031
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3332238234
Short name	T254
Test name
Test status
Simulation time	2953961911 ps
CPU time	4.18 seconds
Started	Feb 08 10:07:37 AM UTC 25
Finished	Feb 08 10:07:43 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332238234 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.3332238234
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3541072485
Short name	T258
Test name
Test status
Simulation time	2613084907 ps
CPU time	11.14 seconds
Started	Feb 08 10:07:36 AM UTC 25
Finished	Feb 08 10:07:48 AM UTC 25
Peak memory	209716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541072485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3541072485
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.4177704222
Short name	T493
Test name
Test status
Simulation time	2476208091 ps
CPU time	4.32 seconds
Started	Feb 08 10:07:32 AM UTC 25
Finished	Feb 08 10:07:38 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177704222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.4177704222
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.774873141
Short name	T492
Test name
Test status
Simulation time	2191333623 ps
CPU time	2.32 seconds
Started	Feb 08 10:07:32 AM UTC 25
Finished	Feb 08 10:07:36 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774873141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.774873141
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.2196774979
Short name	T252
Test name
Test status
Simulation time	2519086507 ps
CPU time	6.48 seconds
Started	Feb 08 10:07:32 AM UTC 25
Finished	Feb 08 10:07:40 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196774979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2196774979
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1534299530
Short name	T491
Test name
Test status
Simulation time	2138181682 ps
CPU time	3.48 seconds
Started	Feb 08 10:07:31 AM UTC 25
Finished	Feb 08 10:07:36 AM UTC 25
Peak memory	209676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534299530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1534299530
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.1083415271
Short name	T246
Test name
Test status
Simulation time	14469678820 ps
CPU time	40.65 seconds
Started	Feb 08 10:07:40 AM UTC 25
Finished	Feb 08 10:08:23 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083415271 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.1083415271
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2533086922
Short name	T137
Test name
Test status
Simulation time	89569942589 ps
CPU time	204.79 seconds
Started	Feb 08 10:07:40 AM UTC 25
Finished	Feb 08 10:11:08 AM UTC 25
Peak memory	220184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2533086922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sy srst_ctrl_stress_all_with_rand_reset.2533086922
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3312726471
Short name	T163
Test name
Test status
Simulation time	4740119358 ps
CPU time	11.05 seconds
Started	Feb 08 10:07:37 AM UTC 25
Finished	Feb 08 10:07:49 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312726471 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.3312726471
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.759379704
Short name	T498
Test name
Test status
Simulation time	2042242562 ps
CPU time	2.98 seconds
Started	Feb 08 10:07:52 AM UTC 25
Finished	Feb 08 10:07:57 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759379704 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.759379704
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1417976486
Short name	T358
Test name
Test status
Simulation time	2955645175 ps
CPU time	3.45 seconds
Started	Feb 08 10:07:47 AM UTC 25
Finished	Feb 08 10:07:52 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417976486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1417976486
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2401398826
Short name	T355
Test name
Test status
Simulation time	148145559115 ps
CPU time	413.47 seconds
Started	Feb 08 10:07:50 AM UTC 25
Finished	Feb 08 10:14:49 AM UTC 25
Peak memory	212564 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401398826 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.2401398826
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1867529180
Short name	T326
Test name
Test status
Simulation time	113808934320 ps
CPU time	330.41 seconds
Started	Feb 08 10:07:50 AM UTC 25
Finished	Feb 08 10:13:25 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867529180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.1867529180
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1725049963
Short name	T313
Test name
Test status
Simulation time	3272279297 ps
CPU time	11.94 seconds
Started	Feb 08 10:07:47 AM UTC 25
Finished	Feb 08 10:08:00 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725049963 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.1725049963
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.3580054168
Short name	T218
Test name
Test status
Simulation time	2443108272 ps
CPU time	16.69 seconds
Started	Feb 08 10:07:50 AM UTC 25
Finished	Feb 08 10:08:08 AM UTC 25
Peak memory	209936 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580054168 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.3580054168
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3391005226
Short name	T496
Test name
Test status
Simulation time	2618469453 ps
CPU time	4.43 seconds
Started	Feb 08 10:07:46 AM UTC 25
Finished	Feb 08 10:07:52 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391005226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3391005226
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.2981397679
Short name	T255
Test name
Test status
Simulation time	2573127617 ps
CPU time	1.27 seconds
Started	Feb 08 10:07:42 AM UTC 25
Finished	Feb 08 10:07:45 AM UTC 25
Peak memory	208084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981397679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2981397679
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1939524043
Short name	T494
Test name
Test status
Simulation time	2082545168 ps
CPU time	3.58 seconds
Started	Feb 08 10:07:44 AM UTC 25
Finished	Feb 08 10:07:49 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939524043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1939524043
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.963160191
Short name	T314
Test name
Test status
Simulation time	2509707331 ps
CPU time	15.31 seconds
Started	Feb 08 10:07:44 AM UTC 25
Finished	Feb 08 10:08:00 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963160191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.963160191
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.1241048897
Short name	T495
Test name
Test status
Simulation time	2113877311 ps
CPU time	7.59 seconds
Started	Feb 08 10:07:41 AM UTC 25
Finished	Feb 08 10:07:50 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241048897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.1241048897
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3060970532
Short name	T504
Test name
Test status
Simulation time	8843346352 ps
CPU time	21.03 seconds
Started	Feb 08 10:07:51 AM UTC 25
Finished	Feb 08 10:08:14 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060970532 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.3060970532
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1160692505
Short name	T164
Test name
Test status
Simulation time	3590843924 ps
CPU time	6.68 seconds
Started	Feb 08 10:07:49 AM UTC 25
Finished	Feb 08 10:07:57 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160692505 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.1160692505
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2650669750
Short name	T502
Test name
Test status
Simulation time	2032957868 ps
CPU time	3.56 seconds
Started	Feb 08 10:08:07 AM UTC 25
Finished	Feb 08 10:08:12 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650669750 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.2650669750
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3668942708
Short name	T500
Test name
Test status
Simulation time	3478665940 ps
CPU time	7.78 seconds
Started	Feb 08 10:08:00 AM UTC 25
Finished	Feb 08 10:08:09 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668942708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.3668942708
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.345661609
Short name	T301
Test name
Test status
Simulation time	138357413914 ps
CPU time	381.68 seconds
Started	Feb 08 10:08:01 AM UTC 25
Finished	Feb 08 10:14:28 AM UTC 25
Peak memory	212560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345661609 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.345661609
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1101561055
Short name	T134
Test name
Test status
Simulation time	98037336566 ps
CPU time	91.08 seconds
Started	Feb 08 10:08:02 AM UTC 25
Finished	Feb 08 10:09:35 AM UTC 25
Peak memory	210220 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101561055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.1101561055
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.639866917
Short name	T319
Test name
Test status
Simulation time	4429179393 ps
CPU time	6.47 seconds
Started	Feb 08 10:08:00 AM UTC 25
Finished	Feb 08 10:08:08 AM UTC 25
Peak memory	209576 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639866917 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.639866917
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2667389324
Short name	T221
Test name
Test status
Simulation time	2728971777 ps
CPU time	15 seconds
Started	Feb 08 10:08:02 AM UTC 25
Finished	Feb 08 10:08:19 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667389324 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.2667389324
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1887250138
Short name	T501
Test name
Test status
Simulation time	2613288730 ps
CPU time	10.66 seconds
Started	Feb 08 10:07:59 AM UTC 25
Finished	Feb 08 10:08:11 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887250138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1887250138
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2111928750
Short name	T370
Test name
Test status
Simulation time	2497818307 ps
CPU time	3.8 seconds
Started	Feb 08 10:07:53 AM UTC 25
Finished	Feb 08 10:07:59 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111928750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2111928750
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4090359294
Short name	T315
Test name
Test status
Simulation time	2186180889 ps
CPU time	3.14 seconds
Started	Feb 08 10:07:56 AM UTC 25
Finished	Feb 08 10:08:01 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090359294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.4090359294
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.2141213011
Short name	T317
Test name
Test status
Simulation time	2524710577 ps
CPU time	6.97 seconds
Started	Feb 08 10:07:57 AM UTC 25
Finished	Feb 08 10:08:06 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141213011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.2141213011
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.2368565440
Short name	T316
Test name
Test status
Simulation time	2108878786 ps
CPU time	8.53 seconds
Started	Feb 08 10:07:52 AM UTC 25
Finished	Feb 08 10:08:03 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368565440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.2368565440
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.290269412
Short name	T165
Test name
Test status
Simulation time	5811168204 ps
CPU time	12.45 seconds
Started	Feb 08 10:08:00 AM UTC 25
Finished	Feb 08 10:08:14 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290269412 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.290269412
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1107578484
Short name	T511
Test name
Test status
Simulation time	2015003601 ps
CPU time	9.78 seconds
Started	Feb 08 10:08:19 AM UTC 25
Finished	Feb 08 10:08:30 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107578484 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.1107578484
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2116488758
Short name	T359
Test name
Test status
Simulation time	3688640487 ps
CPU time	14.68 seconds
Started	Feb 08 10:08:14 AM UTC 25
Finished	Feb 08 10:08:30 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116488758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2116488758
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.3675064538
Short name	T769
Test name
Test status
Simulation time	176950296180 ps
CPU time	559.95 seconds
Started	Feb 08 10:08:15 AM UTC 25
Finished	Feb 08 10:17:42 AM UTC 25
Peak memory	212640 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675064538 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.3675064538
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2336060071
Short name	T44
Test name
Test status
Simulation time	32642687982 ps
CPU time	27.98 seconds
Started	Feb 08 10:08:18 AM UTC 25
Finished	Feb 08 10:08:48 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336060071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.2336060071
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2839725652
Short name	T510
Test name
Test status
Simulation time	3154120394 ps
CPU time	13.81 seconds
Started	Feb 08 10:08:14 AM UTC 25
Finished	Feb 08 10:08:29 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839725652 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.2839725652
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.2025696647
Short name	T194
Test name
Test status
Simulation time	2452543769 ps
CPU time	9.95 seconds
Started	Feb 08 10:08:15 AM UTC 25
Finished	Feb 08 10:08:26 AM UTC 25
Peak memory	209672 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025696647 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.2025696647
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2661287253
Short name	T505
Test name
Test status
Simulation time	2660101586 ps
CPU time	2.64 seconds
Started	Feb 08 10:08:13 AM UTC 25
Finished	Feb 08 10:08:17 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661287253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.2661287253
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1298707480
Short name	T371
Test name
Test status
Simulation time	2471749530 ps
CPU time	6.4 seconds
Started	Feb 08 10:08:09 AM UTC 25
Finished	Feb 08 10:08:17 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298707480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1298707480
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3767656526
Short name	T508
Test name
Test status
Simulation time	2200831084 ps
CPU time	14.81 seconds
Started	Feb 08 10:08:10 AM UTC 25
Finished	Feb 08 10:08:27 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767656526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3767656526
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.1913594800
Short name	T506
Test name
Test status
Simulation time	2528872219 ps
CPU time	5.17 seconds
Started	Feb 08 10:08:11 AM UTC 25
Finished	Feb 08 10:08:18 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913594800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.1913594800
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.4063485680
Short name	T503
Test name
Test status
Simulation time	2144647192 ps
CPU time	2.95 seconds
Started	Feb 08 10:08:08 AM UTC 25
Finished	Feb 08 10:08:13 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063485680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.4063485680
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.2385950462
Short name	T360
Test name
Test status
Simulation time	12649017075 ps
CPU time	11.91 seconds
Started	Feb 08 10:08:19 AM UTC 25
Finished	Feb 08 10:08:33 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385950462 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.2385950462
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1952236384
Short name	T374
Test name
Test status
Simulation time	4953073255 ps
CPU time	3.82 seconds
Started	Feb 08 10:08:14 AM UTC 25
Finished	Feb 08 10:08:19 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952236384 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.1952236384
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2226444330
Short name	T320
Test name
Test status
Simulation time	2016660780 ps
CPU time	9.02 seconds
Started	Feb 08 10:08:31 AM UTC 25
Finished	Feb 08 10:08:42 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226444330 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.2226444330
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1106722092
Short name	T512
Test name
Test status
Simulation time	2831715265 ps
CPU time	4.47 seconds
Started	Feb 08 10:08:27 AM UTC 25
Finished	Feb 08 10:08:33 AM UTC 25
Peak memory	209816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106722092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1106722092
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2863610799
Short name	T353
Test name
Test status
Simulation time	84109944474 ps
CPU time	270.84 seconds
Started	Feb 08 10:08:28 AM UTC 25
Finished	Feb 08 10:13:03 AM UTC 25
Peak memory	210168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863610799 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.2863610799
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2500440447
Short name	T351
Test name
Test status
Simulation time	47627777774 ps
CPU time	136.62 seconds
Started	Feb 08 10:08:30 AM UTC 25
Finished	Feb 08 10:10:49 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500440447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.2500440447
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1864272625
Short name	T516
Test name
Test status
Simulation time	4830489758 ps
CPU time	27.12 seconds
Started	Feb 08 10:08:27 AM UTC 25
Finished	Feb 08 10:08:56 AM UTC 25
Peak memory	209776 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864272625 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.1864272625
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3693273917
Short name	T499
Test name
Test status
Simulation time	2618228662 ps
CPU time	8.27 seconds
Started	Feb 08 10:08:26 AM UTC 25
Finished	Feb 08 10:08:35 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693273917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3693273917
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2086958578
Short name	T256
Test name
Test status
Simulation time	2481650177 ps
CPU time	11.19 seconds
Started	Feb 08 10:08:23 AM UTC 25
Finished	Feb 08 10:08:36 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086958578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2086958578
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3292803692
Short name	T509
Test name
Test status
Simulation time	2186255014 ps
CPU time	4.07 seconds
Started	Feb 08 10:08:23 AM UTC 25
Finished	Feb 08 10:08:29 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292803692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3292803692
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2752806671
Short name	T486
Test name
Test status
Simulation time	2509293944 ps
CPU time	9.88 seconds
Started	Feb 08 10:08:25 AM UTC 25
Finished	Feb 08 10:08:36 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752806671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2752806671
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.4203984214
Short name	T507
Test name
Test status
Simulation time	2136128289 ps
CPU time	3.23 seconds
Started	Feb 08 10:08:20 AM UTC 25
Finished	Feb 08 10:08:25 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203984214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.4203984214
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2815861723
Short name	T181
Test name
Test status
Simulation time	12041877845 ps
CPU time	51.74 seconds
Started	Feb 08 10:08:31 AM UTC 25
Finished	Feb 08 10:09:25 AM UTC 25
Peak memory	209864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815861723 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.2815861723
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3283008248
Short name	T216
Test name
Test status
Simulation time	2035899284 ps
CPU time	3.95 seconds
Started	Feb 08 10:08:47 AM UTC 25
Finished	Feb 08 10:08:53 AM UTC 25
Peak memory	209560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283008248 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.3283008248
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2057498252
Short name	T211
Test name
Test status
Simulation time	3428524120 ps
CPU time	4.15 seconds
Started	Feb 08 10:08:37 AM UTC 25
Finished	Feb 08 10:08:42 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057498252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.2057498252
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2439084649
Short name	T345
Test name
Test status
Simulation time	107569187777 ps
CPU time	85.62 seconds
Started	Feb 08 10:08:39 AM UTC 25
Finished	Feb 08 10:10:07 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439084649 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.2439084649
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1303299981
Short name	T214
Test name
Test status
Simulation time	3625786326 ps
CPU time	10.48 seconds
Started	Feb 08 10:08:37 AM UTC 25
Finished	Feb 08 10:08:49 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303299981 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.1303299981
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.56316058
Short name	T210
Test name
Test status
Simulation time	2636415195 ps
CPU time	3.98 seconds
Started	Feb 08 10:08:37 AM UTC 25
Finished	Feb 08 10:08:42 AM UTC 25
Peak memory	209924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56316058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.56316058
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.449115982
Short name	T372
Test name
Test status
Simulation time	2487511165 ps
CPU time	2.91 seconds
Started	Feb 08 10:08:33 AM UTC 25
Finished	Feb 08 10:08:38 AM UTC 25
Peak memory	209520 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449115982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.449115982
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1112240164
Short name	T213
Test name
Test status
Simulation time	2105622822 ps
CPU time	13.11 seconds
Started	Feb 08 10:08:33 AM UTC 25
Finished	Feb 08 10:08:48 AM UTC 25
Peak memory	209572 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112240164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1112240164
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.575310399
Short name	T373
Test name
Test status
Simulation time	2589346862 ps
CPU time	1.63 seconds
Started	Feb 08 10:08:35 AM UTC 25
Finished	Feb 08 10:08:38 AM UTC 25
Peak memory	208024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575310399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.575310399
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.4000120088
Short name	T212
Test name
Test status
Simulation time	2109780520 ps
CPU time	11.76 seconds
Started	Feb 08 10:08:33 AM UTC 25
Finished	Feb 08 10:08:47 AM UTC 25
Peak memory	209384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000120088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.4000120088
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1937886027
Short name	T803
Test name
Test status
Simulation time	536694226089 ps
CPU time	1635.58 seconds
Started	Feb 08 10:08:43 AM UTC 25
Finished	Feb 08 10:36:15 AM UTC 25
Peak memory	212788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937886027 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.1937886027
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.117024808
Short name	T800
Test name
Test status
Simulation time	3363136077506 ps
CPU time	1054.88 seconds
Started	Feb 08 10:08:39 AM UTC 25
Finished	Feb 08 10:26:25 AM UTC 25
Peak memory	212468 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117024808 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.117024808
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2912134193
Short name	T386
Test name
Test status
Simulation time	2024980881 ps
CPU time	4.39 seconds
Started	Feb 08 10:09:01 AM UTC 25
Finished	Feb 08 10:09:07 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912134193 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.2912134193
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2645701024
Short name	T384
Test name
Test status
Simulation time	3242618870 ps
CPU time	3.85 seconds
Started	Feb 08 10:08:55 AM UTC 25
Finished	Feb 08 10:09:00 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645701024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.2645701024
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.1103966322
Short name	T136
Test name
Test status
Simulation time	169075699551 ps
CPU time	90.83 seconds
Started	Feb 08 10:08:56 AM UTC 25
Finished	Feb 08 10:10:29 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103966322 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.1103966322
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1668650806
Short name	T519
Test name
Test status
Simulation time	3036846136 ps
CPU time	18.24 seconds
Started	Feb 08 10:08:54 AM UTC 25
Finished	Feb 08 10:09:13 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668650806 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.1668650806
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.3181597114
Short name	T287
Test name
Test status
Simulation time	3039367183 ps
CPU time	5.3 seconds
Started	Feb 08 10:08:57 AM UTC 25
Finished	Feb 08 10:09:04 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181597114 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.3181597114
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.4163503481
Short name	T385
Test name
Test status
Simulation time	2612016014 ps
CPU time	7.55 seconds
Started	Feb 08 10:08:54 AM UTC 25
Finished	Feb 08 10:09:03 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163503481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.4163503481
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.3136125130
Short name	T513
Test name
Test status
Simulation time	2483479766 ps
CPU time	3.84 seconds
Started	Feb 08 10:08:48 AM UTC 25
Finished	Feb 08 10:08:54 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136125130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3136125130
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1172805058
Short name	T515
Test name
Test status
Simulation time	2274101590 ps
CPU time	3.75 seconds
Started	Feb 08 10:08:49 AM UTC 25
Finished	Feb 08 10:08:55 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172805058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1172805058
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3492578111
Short name	T383
Test name
Test status
Simulation time	2520554982 ps
CPU time	6.33 seconds
Started	Feb 08 10:08:49 AM UTC 25
Finished	Feb 08 10:08:58 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492578111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3492578111
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.877774680
Short name	T514
Test name
Test status
Simulation time	2118913601 ps
CPU time	6.06 seconds
Started	Feb 08 10:08:47 AM UTC 25
Finished	Feb 08 10:08:55 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877774680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.877774680
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2743520730
Short name	T249
Test name
Test status
Simulation time	40205671072 ps
CPU time	120.81 seconds
Started	Feb 08 10:08:58 AM UTC 25
Finished	Feb 08 10:11:01 AM UTC 25
Peak memory	220168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2743520730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sy srst_ctrl_stress_all_with_rand_reset.2743520730
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3321111432
Short name	T377
Test name
Test status
Simulation time	8102096813 ps
CPU time	4.9 seconds
Started	Feb 08 10:08:56 AM UTC 25
Finished	Feb 08 10:09:02 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321111432 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.3321111432
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2720698241
Short name	T184
Test name
Test status
Simulation time	2017078888 ps
CPU time	5.19 seconds
Started	Feb 08 10:09:21 AM UTC 25
Finished	Feb 08 10:09:28 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720698241 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.2720698241
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.4054568171
Short name	T521
Test name
Test status
Simulation time	3599488963 ps
CPU time	6.46 seconds
Started	Feb 08 10:09:12 AM UTC 25
Finished	Feb 08 10:09:20 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054568171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.4054568171
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2549136417
Short name	T238
Test name
Test status
Simulation time	95997312840 ps
CPU time	167.92 seconds
Started	Feb 08 10:09:14 AM UTC 25
Finished	Feb 08 10:12:05 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549136417 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.2549136417
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.66087397
Short name	T467
Test name
Test status
Simulation time	38347689674 ps
CPU time	177.04 seconds
Started	Feb 08 10:09:14 AM UTC 25
Finished	Feb 08 10:12:15 AM UTC 25
Peak memory	209932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66087397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.66087397
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3544027090
Short name	T182
Test name
Test status
Simulation time	4001689029 ps
CPU time	12.41 seconds
Started	Feb 08 10:09:12 AM UTC 25
Finished	Feb 08 10:09:26 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544027090 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.3544027090
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2551480683
Short name	T183
Test name
Test status
Simulation time	2615473014 ps
CPU time	14.32 seconds
Started	Feb 08 10:09:10 AM UTC 25
Finished	Feb 08 10:09:26 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551480683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2551480683
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.332416782
Short name	T520
Test name
Test status
Simulation time	2463790625 ps
CPU time	9.85 seconds
Started	Feb 08 10:09:03 AM UTC 25
Finished	Feb 08 10:09:15 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332416782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.332416782
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3398974503
Short name	T518
Test name
Test status
Simulation time	2202420014 ps
CPU time	7.15 seconds
Started	Feb 08 10:09:04 AM UTC 25
Finished	Feb 08 10:09:13 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398974503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3398974503
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.1927271963
Short name	T517
Test name
Test status
Simulation time	2618436813 ps
CPU time	1.67 seconds
Started	Feb 08 10:09:08 AM UTC 25
Finished	Feb 08 10:09:12 AM UTC 25
Peak memory	208024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927271963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1927271963
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3096549467
Short name	T387
Test name
Test status
Simulation time	2117977149 ps
CPU time	3.67 seconds
Started	Feb 08 10:09:03 AM UTC 25
Finished	Feb 08 10:09:08 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096549467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3096549467
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2295637282
Short name	T290
Test name
Test status
Simulation time	6839066185 ps
CPU time	10.12 seconds
Started	Feb 08 10:09:21 AM UTC 25
Finished	Feb 08 10:09:33 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295637282 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.2295637282
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.710130496
Short name	T522
Test name
Test status
Simulation time	8514763457 ps
CPU time	5.26 seconds
Started	Feb 08 10:09:13 AM UTC 25
Finished	Feb 08 10:09:20 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710130496 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.710130496
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2047161810
Short name	T101
Test name
Test status
Simulation time	2047109569 ps
CPU time	3.19 seconds
Started	Feb 08 10:04:48 AM UTC 25
Finished	Feb 08 10:04:52 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047161810 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.2047161810
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3473825244
Short name	T58
Test name
Test status
Simulation time	3461722517 ps
CPU time	19.53 seconds
Started	Feb 08 10:04:35 AM UTC 25
Finished	Feb 08 10:04:56 AM UTC 25
Peak memory	209784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473825244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3473825244
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.916383983
Short name	T41
Test name
Test status
Simulation time	165650103446 ps
CPU time	126.26 seconds
Started	Feb 08 10:04:41 AM UTC 25
Finished	Feb 08 10:06:50 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916383983 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.916383983
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1094862110
Short name	T57
Test name
Test status
Simulation time	2214372394 ps
CPU time	3.97 seconds
Started	Feb 08 10:04:27 AM UTC 25
Finished	Feb 08 10:04:33 AM UTC 25
Peak memory	209984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094862110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.1094862110
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.214085048
Short name	T29
Test name
Test status
Simulation time	2284652853 ps
CPU time	3.41 seconds
Started	Feb 08 10:04:27 AM UTC 25
Finished	Feb 08 10:04:32 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214085048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.214085048
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1905304967
Short name	T30
Test name
Test status
Simulation time	44417148309 ps
CPU time	61.65 seconds
Started	Feb 08 10:04:43 AM UTC 25
Finished	Feb 08 10:05:47 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905304967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.1905304967
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.4178969434
Short name	T69
Test name
Test status
Simulation time	3077423715 ps
CPU time	2.19 seconds
Started	Feb 08 10:04:34 AM UTC 25
Finished	Feb 08 10:04:37 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178969434 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.4178969434
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.1404920248
Short name	T10
Test name
Test status
Simulation time	2789368605 ps
CPU time	8.07 seconds
Started	Feb 08 10:04:42 AM UTC 25
Finished	Feb 08 10:04:52 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404920248 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.1404920248
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2757364252
Short name	T82
Test name
Test status
Simulation time	2640447957 ps
CPU time	4.79 seconds
Started	Feb 08 10:04:34 AM UTC 25
Finished	Feb 08 10:04:40 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757364252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.2757364252
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3044083808
Short name	T24
Test name
Test status
Simulation time	2453250728 ps
CPU time	15.81 seconds
Started	Feb 08 10:04:25 AM UTC 25
Finished	Feb 08 10:04:42 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044083808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3044083808
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.2007382248
Short name	T220
Test name
Test status
Simulation time	2058499407 ps
CPU time	11.18 seconds
Started	Feb 08 10:04:28 AM UTC 25
Finished	Feb 08 10:04:41 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007382248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2007382248
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.1747084306
Short name	T83
Test name
Test status
Simulation time	2511755858 ps
CPU time	12.59 seconds
Started	Feb 08 10:04:33 AM UTC 25
Finished	Feb 08 10:04:47 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747084306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1747084306
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2975539995
Short name	T99
Test name
Test status
Simulation time	22013203638 ps
CPU time	75.38 seconds
Started	Feb 08 10:04:47 AM UTC 25
Finished	Feb 08 10:06:05 AM UTC 25
Peak memory	239700 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975539995 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2975539995
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.4049046532
Short name	T67
Test name
Test status
Simulation time	2123424820 ps
CPU time	4.15 seconds
Started	Feb 08 10:04:22 AM UTC 25
Finished	Feb 08 10:04:28 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049046532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.4049046532
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2746200269
Short name	T9
Test name
Test status
Simulation time	5195448408 ps
CPU time	4.56 seconds
Started	Feb 08 10:04:38 AM UTC 25
Finished	Feb 08 10:04:44 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746200269 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.2746200269
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.4190433750
Short name	T524
Test name
Test status
Simulation time	2008543946 ps
CPU time	10.55 seconds
Started	Feb 08 10:09:34 AM UTC 25
Finished	Feb 08 10:09:46 AM UTC 25
Peak memory	209924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190433750 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.4190433750
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2059427727
Short name	T135
Test name
Test status
Simulation time	3612458254 ps
CPU time	19.94 seconds
Started	Feb 08 10:09:30 AM UTC 25
Finished	Feb 08 10:09:52 AM UTC 25
Peak memory	209932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059427727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2059427727
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2959649306
Short name	T798
Test name
Test status
Simulation time	553434643311 ps
CPU time	886.59 seconds
Started	Feb 08 10:09:29 AM UTC 25
Finished	Feb 08 10:24:25 AM UTC 25
Peak memory	212468 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959649306 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.2959649306
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.3900051661
Short name	T229
Test name
Test status
Simulation time	2562287531 ps
CPU time	3.92 seconds
Started	Feb 08 10:09:33 AM UTC 25
Finished	Feb 08 10:09:38 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900051661 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.3900051661
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.579021357
Short name	T292
Test name
Test status
Simulation time	2634505888 ps
CPU time	3.61 seconds
Started	Feb 08 10:09:29 AM UTC 25
Finished	Feb 08 10:09:34 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579021357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.579021357
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.1061312965
Short name	T188
Test name
Test status
Simulation time	2469172253 ps
CPU time	3.89 seconds
Started	Feb 08 10:09:25 AM UTC 25
Finished	Feb 08 10:09:31 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061312965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1061312965
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.1812546434
Short name	T187
Test name
Test status
Simulation time	2162834539 ps
CPU time	1.93 seconds
Started	Feb 08 10:09:27 AM UTC 25
Finished	Feb 08 10:09:30 AM UTC 25
Peak memory	208088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812546434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1812546434
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.4076279924
Short name	T291
Test name
Test status
Simulation time	2529036777 ps
CPU time	5.18 seconds
Started	Feb 08 10:09:27 AM UTC 25
Finished	Feb 08 10:09:33 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076279924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.4076279924
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.3120843443
Short name	T186
Test name
Test status
Simulation time	2127982768 ps
CPU time	2.29 seconds
Started	Feb 08 10:09:25 AM UTC 25
Finished	Feb 08 10:09:29 AM UTC 25
Peak memory	209672 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120843443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.3120843443
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2230488820
Short name	T529
Test name
Test status
Simulation time	9449935894 ps
CPU time	26.48 seconds
Started	Feb 08 10:09:34 AM UTC 25
Finished	Feb 08 10:10:02 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230488820 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.2230488820
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1488284828
Short name	T139
Test name
Test status
Simulation time	162070746147 ps
CPU time	121.16 seconds
Started	Feb 08 10:09:34 AM UTC 25
Finished	Feb 08 10:11:38 AM UTC 25
Peak memory	220440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1488284828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sy srst_ctrl_stress_all_with_rand_reset.1488284828
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.36737296
Short name	T116
Test name
Test status
Simulation time	5796997835 ps
CPU time	4.23 seconds
Started	Feb 08 10:09:31 AM UTC 25
Finished	Feb 08 10:09:37 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36737296 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.36737296
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1092258034
Short name	T195
Test name
Test status
Simulation time	2020272598 ps
CPU time	5.63 seconds
Started	Feb 08 10:10:01 AM UTC 25
Finished	Feb 08 10:10:08 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092258034 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.1092258034
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1978846015
Short name	T527
Test name
Test status
Simulation time	3585409066 ps
CPU time	4.81 seconds
Started	Feb 08 10:09:47 AM UTC 25
Finished	Feb 08 10:09:53 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978846015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1978846015
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3390703204
Short name	T453
Test name
Test status
Simulation time	112026947437 ps
CPU time	162.81 seconds
Started	Feb 08 10:09:53 AM UTC 25
Finished	Feb 08 10:12:39 AM UTC 25
Peak memory	210108 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390703204 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.3390703204
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1658091942
Short name	T325
Test name
Test status
Simulation time	29081884038 ps
CPU time	102.05 seconds
Started	Feb 08 10:09:54 AM UTC 25
Finished	Feb 08 10:11:39 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658091942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.1658091942
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2771429969
Short name	T528
Test name
Test status
Simulation time	2839375112 ps
CPU time	11.59 seconds
Started	Feb 08 10:09:46 AM UTC 25
Finished	Feb 08 10:09:59 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771429969 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.2771429969
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.579161467
Short name	T305
Test name
Test status
Simulation time	3921404631 ps
CPU time	10.72 seconds
Started	Feb 08 10:09:53 AM UTC 25
Finished	Feb 08 10:10:06 AM UTC 25
Peak memory	209936 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579161467 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.579161467
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.196367583
Short name	T525
Test name
Test status
Simulation time	2634483850 ps
CPU time	4.68 seconds
Started	Feb 08 10:09:46 AM UTC 25
Finished	Feb 08 10:09:52 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196367583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.196367583
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1724855628
Short name	T293
Test name
Test status
Simulation time	2448550894 ps
CPU time	4.16 seconds
Started	Feb 08 10:09:37 AM UTC 25
Finished	Feb 08 10:09:43 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724855628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.1724855628
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.924687832
Short name	T294
Test name
Test status
Simulation time	2175215433 ps
CPU time	3.5 seconds
Started	Feb 08 10:09:40 AM UTC 25
Finished	Feb 08 10:09:44 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924687832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.924687832
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2367656960
Short name	T526
Test name
Test status
Simulation time	2512517482 ps
CPU time	7.02 seconds
Started	Feb 08 10:09:44 AM UTC 25
Finished	Feb 08 10:09:52 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367656960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2367656960
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2612313933
Short name	T523
Test name
Test status
Simulation time	2110578574 ps
CPU time	7.01 seconds
Started	Feb 08 10:09:36 AM UTC 25
Finished	Feb 08 10:09:45 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612313933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2612313933
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1566484161
Short name	T531
Test name
Test status
Simulation time	12853301100 ps
CPU time	18.83 seconds
Started	Feb 08 10:10:00 AM UTC 25
Finished	Feb 08 10:10:21 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566484161 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.1566484161
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3619098464
Short name	T364
Test name
Test status
Simulation time	18114449297 ps
CPU time	84.67 seconds
Started	Feb 08 10:09:57 AM UTC 25
Finished	Feb 08 10:11:24 AM UTC 25
Peak memory	209872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3619098464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sy srst_ctrl_stress_all_with_rand_reset.3619098464
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.4211500534
Short name	T375
Test name
Test status
Simulation time	3667328171 ps
CPU time	6.18 seconds
Started	Feb 08 10:09:53 AM UTC 25
Finished	Feb 08 10:10:01 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211500534 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.4211500534
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1913717634
Short name	T532
Test name
Test status
Simulation time	2011009309 ps
CPU time	13.83 seconds
Started	Feb 08 10:10:14 AM UTC 25
Finished	Feb 08 10:10:30 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913717634 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.1913717634
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1126459145
Short name	T530
Test name
Test status
Simulation time	3630103973 ps
CPU time	10.12 seconds
Started	Feb 08 10:10:09 AM UTC 25
Finished	Feb 08 10:10:20 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126459145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1126459145
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.233951565
Short name	T469
Test name
Test status
Simulation time	55587170702 ps
CPU time	121.03 seconds
Started	Feb 08 10:10:12 AM UTC 25
Finished	Feb 08 10:12:16 AM UTC 25
Peak memory	209888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233951565 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.233951565
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3898216125
Short name	T201
Test name
Test status
Simulation time	3704722955 ps
CPU time	8.63 seconds
Started	Feb 08 10:10:08 AM UTC 25
Finished	Feb 08 10:10:18 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898216125 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.3898216125
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1220154891
Short name	T203
Test name
Test status
Simulation time	3832157123 ps
CPU time	10.49 seconds
Started	Feb 08 10:10:12 AM UTC 25
Finished	Feb 08 10:10:24 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220154891 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.1220154891
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.577975504
Short name	T200
Test name
Test status
Simulation time	2627522990 ps
CPU time	4.44 seconds
Started	Feb 08 10:10:07 AM UTC 25
Finished	Feb 08 10:10:13 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577975504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.577975504
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3080122626
Short name	T196
Test name
Test status
Simulation time	2467852869 ps
CPU time	5.93 seconds
Started	Feb 08 10:10:03 AM UTC 25
Finished	Feb 08 10:10:11 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080122626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3080122626
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.751610260
Short name	T198
Test name
Test status
Simulation time	2233202097 ps
CPU time	5.88 seconds
Started	Feb 08 10:10:05 AM UTC 25
Finished	Feb 08 10:10:12 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751610260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.751610260
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.3610302612
Short name	T289
Test name
Test status
Simulation time	2514762755 ps
CPU time	8.71 seconds
Started	Feb 08 10:10:05 AM UTC 25
Finished	Feb 08 10:10:15 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610302612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.3610302612
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2618540099
Short name	T197
Test name
Test status
Simulation time	2113630552 ps
CPU time	7.59 seconds
Started	Feb 08 10:10:02 AM UTC 25
Finished	Feb 08 10:10:12 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618540099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2618540099
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2413190772
Short name	T340
Test name
Test status
Simulation time	148157664333 ps
CPU time	59.94 seconds
Started	Feb 08 10:10:13 AM UTC 25
Finished	Feb 08 10:11:15 AM UTC 25
Peak memory	209864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413190772 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.2413190772
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.3702120152
Short name	T541
Test name
Test status
Simulation time	2012591807 ps
CPU time	6.5 seconds
Started	Feb 08 10:10:32 AM UTC 25
Finished	Feb 08 10:10:40 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702120152 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.3702120152
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.4192676160
Short name	T536
Test name
Test status
Simulation time	3978496581 ps
CPU time	8.46 seconds
Started	Feb 08 10:10:22 AM UTC 25
Finished	Feb 08 10:10:32 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192676160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.4192676160
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.533213704
Short name	T352
Test name
Test status
Simulation time	119501606258 ps
CPU time	65.25 seconds
Started	Feb 08 10:10:29 AM UTC 25
Finished	Feb 08 10:11:36 AM UTC 25
Peak memory	209888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533213704 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.533213704
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.422460844
Short name	T632
Test name
Test status
Simulation time	56808484360 ps
CPU time	178.25 seconds
Started	Feb 08 10:10:30 AM UTC 25
Finished	Feb 08 10:13:31 AM UTC 25
Peak memory	209920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422460844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_with_pre_cond.422460844
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.600890602
Short name	T539
Test name
Test status
Simulation time	2637541984 ps
CPU time	14.58 seconds
Started	Feb 08 10:10:22 AM UTC 25
Finished	Feb 08 10:10:38 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600890602 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.600890602
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.3772798052
Short name	T538
Test name
Test status
Simulation time	4864902351 ps
CPU time	2.48 seconds
Started	Feb 08 10:10:30 AM UTC 25
Finished	Feb 08 10:10:34 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772798052 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.3772798052
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.448853713
Short name	T534
Test name
Test status
Simulation time	2618259806 ps
CPU time	8.06 seconds
Started	Feb 08 10:10:21 AM UTC 25
Finished	Feb 08 10:10:30 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448853713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.448853713
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.1212528661
Short name	T537
Test name
Test status
Simulation time	2473906940 ps
CPU time	13.42 seconds
Started	Feb 08 10:10:18 AM UTC 25
Finished	Feb 08 10:10:33 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212528661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.1212528661
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.446249850
Short name	T535
Test name
Test status
Simulation time	2211156288 ps
CPU time	10.97 seconds
Started	Feb 08 10:10:19 AM UTC 25
Finished	Feb 08 10:10:31 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446249850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.446249850
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.1752560615
Short name	T533
Test name
Test status
Simulation time	2515362035 ps
CPU time	8.64 seconds
Started	Feb 08 10:10:20 AM UTC 25
Finished	Feb 08 10:10:30 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752560615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.1752560615
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3411307747
Short name	T202
Test name
Test status
Simulation time	2155488893 ps
CPU time	2.48 seconds
Started	Feb 08 10:10:16 AM UTC 25
Finished	Feb 08 10:10:19 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411307747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3411307747
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1994672103
Short name	T565
Test name
Test status
Simulation time	21015546088 ps
CPU time	67.96 seconds
Started	Feb 08 10:10:32 AM UTC 25
Finished	Feb 08 10:11:42 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994672103 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.1994672103
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3822179602
Short name	T376
Test name
Test status
Simulation time	4478972431 ps
CPU time	6.95 seconds
Started	Feb 08 10:10:25 AM UTC 25
Finished	Feb 08 10:10:33 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822179602 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.3822179602
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.285400960
Short name	T547
Test name
Test status
Simulation time	2052149313 ps
CPU time	3.37 seconds
Started	Feb 08 10:10:49 AM UTC 25
Finished	Feb 08 10:10:53 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285400960 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.285400960
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1725379792
Short name	T551
Test name
Test status
Simulation time	65908181758 ps
CPU time	24.15 seconds
Started	Feb 08 10:10:39 AM UTC 25
Finished	Feb 08 10:11:05 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725379792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.1725379792
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1242478689
Short name	T138
Test name
Test status
Simulation time	55051575758 ps
CPU time	51.1 seconds
Started	Feb 08 10:10:41 AM UTC 25
Finished	Feb 08 10:11:34 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242478689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.1242478689
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.879268137
Short name	T543
Test name
Test status
Simulation time	2856788577 ps
CPU time	4.06 seconds
Started	Feb 08 10:10:35 AM UTC 25
Finished	Feb 08 10:10:41 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879268137 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.879268137
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.48228088
Short name	T222
Test name
Test status
Simulation time	3685991024 ps
CPU time	21.54 seconds
Started	Feb 08 10:10:41 AM UTC 25
Finished	Feb 08 10:11:04 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48228088 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.48228088
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.489828578
Short name	T542
Test name
Test status
Simulation time	2638152731 ps
CPU time	3.88 seconds
Started	Feb 08 10:10:35 AM UTC 25
Finished	Feb 08 10:10:40 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489828578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.489828578
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.2668431925
Short name	T546
Test name
Test status
Simulation time	2445915070 ps
CPU time	13.74 seconds
Started	Feb 08 10:10:33 AM UTC 25
Finished	Feb 08 10:10:48 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668431925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.2668431925
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3237641569
Short name	T544
Test name
Test status
Simulation time	2075318580 ps
CPU time	5.7 seconds
Started	Feb 08 10:10:34 AM UTC 25
Finished	Feb 08 10:10:41 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237641569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3237641569
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.476523137
Short name	T540
Test name
Test status
Simulation time	2563431050 ps
CPU time	2.3 seconds
Started	Feb 08 10:10:35 AM UTC 25
Finished	Feb 08 10:10:39 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476523137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.476523137
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.704654272
Short name	T545
Test name
Test status
Simulation time	2113416221 ps
CPU time	14.33 seconds
Started	Feb 08 10:10:32 AM UTC 25
Finished	Feb 08 10:10:48 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704654272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.704654272
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.4216589438
Short name	T339
Test name
Test status
Simulation time	10402347323 ps
CPU time	28.24 seconds
Started	Feb 08 10:10:44 AM UTC 25
Finished	Feb 08 10:11:14 AM UTC 25
Peak memory	210120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216589438 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.4216589438
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2029281016
Short name	T553
Test name
Test status
Simulation time	2012623632 ps
CPU time	10.21 seconds
Started	Feb 08 10:11:11 AM UTC 25
Finished	Feb 08 10:11:22 AM UTC 25
Peak memory	209924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029281016 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.2029281016
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1651060357
Short name	T652
Test name
Test status
Simulation time	172253142611 ps
CPU time	174.48 seconds
Started	Feb 08 10:11:01 AM UTC 25
Finished	Feb 08 10:13:59 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651060357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1651060357
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3162261919
Short name	T451
Test name
Test status
Simulation time	86707689871 ps
CPU time	71.07 seconds
Started	Feb 08 10:11:05 AM UTC 25
Finished	Feb 08 10:12:19 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162261919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.3162261919
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3605437917
Short name	T336
Test name
Test status
Simulation time	4276061734 ps
CPU time	10.69 seconds
Started	Feb 08 10:10:59 AM UTC 25
Finished	Feb 08 10:11:11 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605437917 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.3605437917
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.2495919529
Short name	T476
Test name
Test status
Simulation time	50730943721 ps
CPU time	147.48 seconds
Started	Feb 08 10:11:04 AM UTC 25
Finished	Feb 08 10:13:34 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495919529 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.2495919529
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.320294091
Short name	T338
Test name
Test status
Simulation time	2612832190 ps
CPU time	12.42 seconds
Started	Feb 08 10:10:58 AM UTC 25
Finished	Feb 08 10:11:12 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320294091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.320294091
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3815549915
Short name	T548
Test name
Test status
Simulation time	2465821422 ps
CPU time	4.77 seconds
Started	Feb 08 10:10:51 AM UTC 25
Finished	Feb 08 10:10:57 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815549915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.3815549915
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.401134980
Short name	T335
Test name
Test status
Simulation time	2225104701 ps
CPU time	14.43 seconds
Started	Feb 08 10:10:54 AM UTC 25
Finished	Feb 08 10:11:10 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401134980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.401134980
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4133768487
Short name	T550
Test name
Test status
Simulation time	2515422534 ps
CPU time	8.08 seconds
Started	Feb 08 10:10:54 AM UTC 25
Finished	Feb 08 10:11:03 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133768487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.4133768487
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1166872180
Short name	T549
Test name
Test status
Simulation time	2108884711 ps
CPU time	12.74 seconds
Started	Feb 08 10:10:49 AM UTC 25
Finished	Feb 08 10:11:03 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166872180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1166872180
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3748408368
Short name	T369
Test name
Test status
Simulation time	9061030871 ps
CPU time	11.73 seconds
Started	Feb 08 10:11:09 AM UTC 25
Finished	Feb 08 10:11:23 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748408368 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.3748408368
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4064830166
Short name	T321
Test name
Test status
Simulation time	29834577754 ps
CPU time	88.38 seconds
Started	Feb 08 10:11:05 AM UTC 25
Finished	Feb 08 10:12:36 AM UTC 25
Peak memory	220492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4064830166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sy srst_ctrl_stress_all_with_rand_reset.4064830166
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3539676231
Short name	T337
Test name
Test status
Simulation time	374928710431 ps
CPU time	7.56 seconds
Started	Feb 08 10:11:02 AM UTC 25
Finished	Feb 08 10:11:11 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539676231 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.3539676231
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2453065608
Short name	T563
Test name
Test status
Simulation time	2014231162 ps
CPU time	10.19 seconds
Started	Feb 08 10:11:28 AM UTC 25
Finished	Feb 08 10:11:40 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453065608 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.2453065608
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2360403587
Short name	T557
Test name
Test status
Simulation time	3105380491 ps
CPU time	6.76 seconds
Started	Feb 08 10:11:21 AM UTC 25
Finished	Feb 08 10:11:29 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360403587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2360403587
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.402715522
Short name	T330
Test name
Test status
Simulation time	33503987780 ps
CPU time	16.69 seconds
Started	Feb 08 10:11:23 AM UTC 25
Finished	Feb 08 10:11:41 AM UTC 25
Peak memory	209820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402715522 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.402715522
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4168390404
Short name	T419
Test name
Test status
Simulation time	110873800694 ps
CPU time	348.9 seconds
Started	Feb 08 10:11:23 AM UTC 25
Finished	Feb 08 10:17:17 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168390404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.4168390404
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1982040996
Short name	T571
Test name
Test status
Simulation time	4381519577 ps
CPU time	25.83 seconds
Started	Feb 08 10:11:21 AM UTC 25
Finished	Feb 08 10:11:49 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982040996 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.1982040996
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1693176164
Short name	T260
Test name
Test status
Simulation time	3036279839 ps
CPU time	2.49 seconds
Started	Feb 08 10:11:23 AM UTC 25
Finished	Feb 08 10:11:27 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693176164 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.1693176164
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1899017962
Short name	T341
Test name
Test status
Simulation time	2650704324 ps
CPU time	2.54 seconds
Started	Feb 08 10:11:16 AM UTC 25
Finished	Feb 08 10:11:20 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899017962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1899017962
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4033607239
Short name	T343
Test name
Test status
Simulation time	2453274641 ps
CPU time	7.99 seconds
Started	Feb 08 10:11:12 AM UTC 25
Finished	Feb 08 10:11:21 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033607239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.4033607239
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.20998901
Short name	T342
Test name
Test status
Simulation time	2159149140 ps
CPU time	6.08 seconds
Started	Feb 08 10:11:13 AM UTC 25
Finished	Feb 08 10:11:20 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20998901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.20998901
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3940834165
Short name	T552
Test name
Test status
Simulation time	2519482975 ps
CPU time	5.58 seconds
Started	Feb 08 10:11:15 AM UTC 25
Finished	Feb 08 10:11:22 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940834165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3940834165
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2266524303
Short name	T554
Test name
Test status
Simulation time	2109886127 ps
CPU time	11.95 seconds
Started	Feb 08 10:11:12 AM UTC 25
Finished	Feb 08 10:11:25 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266524303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2266524303
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.399610489
Short name	T555
Test name
Test status
Simulation time	4746344268 ps
CPU time	3.65 seconds
Started	Feb 08 10:11:22 AM UTC 25
Finished	Feb 08 10:11:27 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399610489 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.399610489
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1647037214
Short name	T567
Test name
Test status
Simulation time	2021943926 ps
CPU time	5.79 seconds
Started	Feb 08 10:11:39 AM UTC 25
Finished	Feb 08 10:11:47 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647037214 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.1647037214
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2124718456
Short name	T573
Test name
Test status
Simulation time	3629145954 ps
CPU time	12.6 seconds
Started	Feb 08 10:11:35 AM UTC 25
Finished	Feb 08 10:11:49 AM UTC 25
Peak memory	210124 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124718456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2124718456
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1998775318
Short name	T354
Test name
Test status
Simulation time	97301950750 ps
CPU time	147.83 seconds
Started	Feb 08 10:11:35 AM UTC 25
Finished	Feb 08 10:14:06 AM UTC 25
Peak memory	209888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998775318 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.1998775318
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2149022556
Short name	T120
Test name
Test status
Simulation time	25078195076 ps
CPU time	107.26 seconds
Started	Feb 08 10:11:37 AM UTC 25
Finished	Feb 08 10:13:27 AM UTC 25
Peak memory	210224 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149022556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.2149022556
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2116946852
Short name	T564
Test name
Test status
Simulation time	2936359789 ps
CPU time	3.83 seconds
Started	Feb 08 10:11:34 AM UTC 25
Finished	Feb 08 10:11:40 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116946852 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.2116946852
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.2389393336
Short name	T230
Test name
Test status
Simulation time	2439870942 ps
CPU time	3.76 seconds
Started	Feb 08 10:11:35 AM UTC 25
Finished	Feb 08 10:11:40 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389393336 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.2389393336
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1090702465
Short name	T562
Test name
Test status
Simulation time	2613748985 ps
CPU time	5.13 seconds
Started	Feb 08 10:11:32 AM UTC 25
Finished	Feb 08 10:11:39 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090702465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.1090702465
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.345904183
Short name	T566
Test name
Test status
Simulation time	2445685402 ps
CPU time	15.76 seconds
Started	Feb 08 10:11:28 AM UTC 25
Finished	Feb 08 10:11:45 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345904183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.345904183
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.506863268
Short name	T559
Test name
Test status
Simulation time	2267943380 ps
CPU time	3.59 seconds
Started	Feb 08 10:11:29 AM UTC 25
Finished	Feb 08 10:11:34 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506863268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.506863268
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.364966847
Short name	T561
Test name
Test status
Simulation time	2548708767 ps
CPU time	2.92 seconds
Started	Feb 08 10:11:30 AM UTC 25
Finished	Feb 08 10:11:34 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364966847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.364966847
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.920606441
Short name	T558
Test name
Test status
Simulation time	2132086942 ps
CPU time	3.5 seconds
Started	Feb 08 10:11:28 AM UTC 25
Finished	Feb 08 10:11:33 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920606441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.920606441
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.2398735125
Short name	T235
Test name
Test status
Simulation time	14412389462 ps
CPU time	21.8 seconds
Started	Feb 08 10:11:39 AM UTC 25
Finished	Feb 08 10:12:03 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398735125 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.2398735125
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2835689755
Short name	T206
Test name
Test status
Simulation time	56049164434 ps
CPU time	60.7 seconds
Started	Feb 08 10:11:38 AM UTC 25
Finished	Feb 08 10:12:41 AM UTC 25
Peak memory	220132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2835689755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sy srst_ctrl_stress_all_with_rand_reset.2835689755
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3051551281
Short name	T570
Test name
Test status
Simulation time	4940852538 ps
CPU time	11.69 seconds
Started	Feb 08 10:11:35 AM UTC 25
Finished	Feb 08 10:11:48 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051551281 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.3051551281
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.11601288
Short name	T581
Test name
Test status
Simulation time	2020827581 ps
CPU time	5.35 seconds
Started	Feb 08 10:11:49 AM UTC 25
Finished	Feb 08 10:11:56 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11601288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.11601288
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.457942829
Short name	T577
Test name
Test status
Simulation time	3310172280 ps
CPU time	5.08 seconds
Started	Feb 08 10:11:46 AM UTC 25
Finished	Feb 08 10:11:53 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457942829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.457942829
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2888824102
Short name	T279
Test name
Test status
Simulation time	36111319918 ps
CPU time	65.94 seconds
Started	Feb 08 10:11:48 AM UTC 25
Finished	Feb 08 10:12:56 AM UTC 25
Peak memory	209952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888824102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.2888824102
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2600825762
Short name	T574
Test name
Test status
Simulation time	3142042454 ps
CPU time	3.48 seconds
Started	Feb 08 10:11:45 AM UTC 25
Finished	Feb 08 10:11:50 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600825762 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.2600825762
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3386563513
Short name	T572
Test name
Test status
Simulation time	2632722073 ps
CPU time	4.58 seconds
Started	Feb 08 10:11:43 AM UTC 25
Finished	Feb 08 10:11:49 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386563513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.3386563513
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.810859486
Short name	T569
Test name
Test status
Simulation time	2469686451 ps
CPU time	5.78 seconds
Started	Feb 08 10:11:41 AM UTC 25
Finished	Feb 08 10:11:48 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810859486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.810859486
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.1526359951
Short name	T568
Test name
Test status
Simulation time	2246374844 ps
CPU time	3.98 seconds
Started	Feb 08 10:11:42 AM UTC 25
Finished	Feb 08 10:11:47 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526359951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.1526359951
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3152076410
Short name	T575
Test name
Test status
Simulation time	2522162290 ps
CPU time	6.35 seconds
Started	Feb 08 10:11:43 AM UTC 25
Finished	Feb 08 10:11:50 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152076410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.3152076410
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.585172047
Short name	T560
Test name
Test status
Simulation time	2162309464 ps
CPU time	1.78 seconds
Started	Feb 08 10:11:41 AM UTC 25
Finished	Feb 08 10:11:44 AM UTC 25
Peak memory	208024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585172047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.585172047
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.361547423
Short name	T144
Test name
Test status
Simulation time	85085123037 ps
CPU time	253.11 seconds
Started	Feb 08 10:11:49 AM UTC 25
Finished	Feb 08 10:16:06 AM UTC 25
Peak memory	209832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361547423 -assert nopostproc +UVM_TESTNAME=sysrst_ ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.361547423
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3720636564
Short name	T259
Test name
Test status
Simulation time	29058436353 ps
CPU time	74.03 seconds
Started	Feb 08 10:11:49 AM UTC 25
Finished	Feb 08 10:13:05 AM UTC 25
Peak memory	210104 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3720636564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sy srst_ctrl_stress_all_with_rand_reset.3720636564
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1945416413
Short name	T579
Test name
Test status
Simulation time	9015969974 ps
CPU time	7.99 seconds
Started	Feb 08 10:11:46 AM UTC 25
Finished	Feb 08 10:11:55 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945416413 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.1945416413
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2006057288
Short name	T239
Test name
Test status
Simulation time	2037605958 ps
CPU time	3.85 seconds
Started	Feb 08 10:12:03 AM UTC 25
Finished	Feb 08 10:12:08 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006057288 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.2006057288
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3564088267
Short name	T240
Test name
Test status
Simulation time	3702013968 ps
CPU time	13.13 seconds
Started	Feb 08 10:11:55 AM UTC 25
Finished	Feb 08 10:12:10 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564088267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3564088267
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1537769987
Short name	T409
Test name
Test status
Simulation time	64195094132 ps
CPU time	197.87 seconds
Started	Feb 08 10:11:56 AM UTC 25
Finished	Feb 08 10:15:17 AM UTC 25
Peak memory	209904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537769987 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.1537769987
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.874853700
Short name	T265
Test name
Test status
Simulation time	46875804868 ps
CPU time	97.07 seconds
Started	Feb 08 10:11:57 AM UTC 25
Finished	Feb 08 10:13:37 AM UTC 25
Peak memory	210236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874853700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.874853700
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1503719203
Short name	T582
Test name
Test status
Simulation time	2807839231 ps
CPU time	16.66 seconds
Started	Feb 08 10:11:54 AM UTC 25
Finished	Feb 08 10:12:12 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503719203 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.1503719203
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1499996445
Short name	T234
Test name
Test status
Simulation time	3266190432 ps
CPU time	3.74 seconds
Started	Feb 08 10:11:57 AM UTC 25
Finished	Feb 08 10:12:02 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499996445 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.1499996445
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1566268532
Short name	T233
Test name
Test status
Simulation time	2614902838 ps
CPU time	6.15 seconds
Started	Feb 08 10:11:54 AM UTC 25
Finished	Feb 08 10:12:01 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566268532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1566268532
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.261267574
Short name	T578
Test name
Test status
Simulation time	2483129993 ps
CPU time	2.19 seconds
Started	Feb 08 10:11:51 AM UTC 25
Finished	Feb 08 10:11:54 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261267574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.261267574
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.2146648725
Short name	T580
Test name
Test status
Simulation time	2140692533 ps
CPU time	4.04 seconds
Started	Feb 08 10:11:51 AM UTC 25
Finished	Feb 08 10:11:56 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146648725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2146648725
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3238455264
Short name	T237
Test name
Test status
Simulation time	2510790451 ps
CPU time	10.94 seconds
Started	Feb 08 10:11:52 AM UTC 25
Finished	Feb 08 10:12:04 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238455264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3238455264
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2614625051
Short name	T576
Test name
Test status
Simulation time	2219032313 ps
CPU time	1.61 seconds
Started	Feb 08 10:11:49 AM UTC 25
Finished	Feb 08 10:11:52 AM UTC 25
Peak memory	208028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614625051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2614625051
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.911191085
Short name	T585
Test name
Test status
Simulation time	9198228860 ps
CPU time	13.74 seconds
Started	Feb 08 10:12:00 AM UTC 25
Finished	Feb 08 10:12:16 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911191085 -assert nopostproc +UVM_TESTNAME=sysrst_ ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.911191085
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3358897539
Short name	T619
Test name
Test status
Simulation time	18406978640 ps
CPU time	75.21 seconds
Started	Feb 08 10:11:57 AM UTC 25
Finished	Feb 08 10:13:15 AM UTC 25
Peak memory	209960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3358897539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sy srst_ctrl_stress_all_with_rand_reset.3358897539
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1358658473
Short name	T236
Test name
Test status
Simulation time	8976554890 ps
CPU time	7.39 seconds
Started	Feb 08 10:11:55 AM UTC 25
Finished	Feb 08 10:12:04 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358658473 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.1358658473
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.881592638
Short name	T282
Test name
Test status
Simulation time	2080940749 ps
CPU time	2.37 seconds
Started	Feb 08 10:05:12 AM UTC 25
Finished	Feb 08 10:05:16 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881592638 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.881592638
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3781881439
Short name	T60
Test name
Test status
Simulation time	3871293878 ps
CPU time	2.09 seconds
Started	Feb 08 10:05:03 AM UTC 25
Finished	Feb 08 10:05:07 AM UTC 25
Peak memory	209780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781881439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3781881439
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.2732387895
Short name	T43
Test name
Test status
Simulation time	59372623240 ps
CPU time	162.4 seconds
Started	Feb 08 10:05:04 AM UTC 25
Finished	Feb 08 10:07:50 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732387895 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.2732387895
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.173759483
Short name	T132
Test name
Test status
Simulation time	2433882823 ps
CPU time	12.26 seconds
Started	Feb 08 10:04:55 AM UTC 25
Finished	Feb 08 10:05:09 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173759483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.173759483
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2471347680
Short name	T59
Test name
Test status
Simulation time	2547659542 ps
CPU time	5.05 seconds
Started	Feb 08 10:04:57 AM UTC 25
Finished	Feb 08 10:05:04 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471347680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2471347680
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3180684791
Short name	T88
Test name
Test status
Simulation time	95569552670 ps
CPU time	100.94 seconds
Started	Feb 08 10:05:08 AM UTC 25
Finished	Feb 08 10:06:51 AM UTC 25
Peak memory	210048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180684791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.3180684791
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.349453619
Short name	T284
Test name
Test status
Simulation time	3777497186 ps
CPU time	16.2 seconds
Started	Feb 08 10:04:59 AM UTC 25
Finished	Feb 08 10:05:17 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349453619 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.349453619
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1720818392
Short name	T85
Test name
Test status
Simulation time	2609651506 ps
CPU time	15.14 seconds
Started	Feb 08 10:04:59 AM UTC 25
Finished	Feb 08 10:05:16 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720818392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.1720818392
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3004509989
Short name	T75
Test name
Test status
Simulation time	2459942874 ps
CPU time	14.17 seconds
Started	Feb 08 10:04:53 AM UTC 25
Finished	Feb 08 10:05:09 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004509989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.3004509989
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.1138418049
Short name	T95
Test name
Test status
Simulation time	2242518114 ps
CPU time	4.09 seconds
Started	Feb 08 10:04:57 AM UTC 25
Finished	Feb 08 10:05:03 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138418049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.1138418049
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1773919646
Short name	T84
Test name
Test status
Simulation time	2536257387 ps
CPU time	4.24 seconds
Started	Feb 08 10:04:57 AM UTC 25
Finished	Feb 08 10:05:03 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773919646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1773919646
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3837908386
Short name	T152
Test name
Test status
Simulation time	22012426478 ps
CPU time	85.81 seconds
Started	Feb 08 10:05:10 AM UTC 25
Finished	Feb 08 10:06:38 AM UTC 25
Peak memory	237488 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837908386 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3837908386
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.254135538
Short name	T93
Test name
Test status
Simulation time	2127530236 ps
CPU time	3.73 seconds
Started	Feb 08 10:04:53 AM UTC 25
Finished	Feb 08 10:04:58 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254135538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.254135538
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.2812614593
Short name	T72
Test name
Test status
Simulation time	8732361590 ps
CPU time	30.3 seconds
Started	Feb 08 10:05:10 AM UTC 25
Finished	Feb 08 10:05:42 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812614593 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.2812614593
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3928001080
Short name	T588
Test name
Test status
Simulation time	2160238639 ps
CPU time	1.69 seconds
Started	Feb 08 10:12:17 AM UTC 25
Finished	Feb 08 10:12:20 AM UTC 25
Peak memory	208092 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928001080 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.3928001080
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.887546292
Short name	T141
Test name
Test status
Simulation time	3779234371 ps
CPU time	4 seconds
Started	Feb 08 10:12:10 AM UTC 25
Finished	Feb 08 10:12:15 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887546292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.887546292
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.2774668247
Short name	T421
Test name
Test status
Simulation time	112892620078 ps
CPU time	315.43 seconds
Started	Feb 08 10:12:13 AM UTC 25
Finished	Feb 08 10:17:33 AM UTC 25
Peak memory	209904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774668247 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.2774668247
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.4155929538
Short name	T433
Test name
Test status
Simulation time	89587430544 ps
CPU time	328.76 seconds
Started	Feb 08 10:12:14 AM UTC 25
Finished	Feb 08 10:17:49 AM UTC 25
Peak memory	210048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155929538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.4155929538
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1158480118
Short name	T805
Test name
Test status
Simulation time	1023306499535 ps
CPU time	2846.87 seconds
Started	Feb 08 10:12:09 AM UTC 25
Finished	Feb 08 11:00:02 AM UTC 25
Peak memory	212396 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158480118 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.1158480118
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.2943140654
Short name	T205
Test name
Test status
Simulation time	3597499894 ps
CPU time	8.77 seconds
Started	Feb 08 10:12:13 AM UTC 25
Finished	Feb 08 10:12:24 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943140654 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.2943140654
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3475862989
Short name	T589
Test name
Test status
Simulation time	2610432898 ps
CPU time	13.43 seconds
Started	Feb 08 10:12:06 AM UTC 25
Finished	Feb 08 10:12:21 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475862989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.3475862989
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1166547564
Short name	T241
Test name
Test status
Simulation time	2469842857 ps
CPU time	6.87 seconds
Started	Feb 08 10:12:04 AM UTC 25
Finished	Feb 08 10:12:12 AM UTC 25
Peak memory	210056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166547564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1166547564
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.613964180
Short name	T586
Test name
Test status
Simulation time	2166622880 ps
CPU time	9.34 seconds
Started	Feb 08 10:12:05 AM UTC 25
Finished	Feb 08 10:12:16 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613964180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.613964180
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.697460875
Short name	T584
Test name
Test status
Simulation time	2521928932 ps
CPU time	7.03 seconds
Started	Feb 08 10:12:05 AM UTC 25
Finished	Feb 08 10:12:13 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697460875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.697460875
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.495733538
Short name	T587
Test name
Test status
Simulation time	2107560975 ps
CPU time	13.58 seconds
Started	Feb 08 10:12:04 AM UTC 25
Finished	Feb 08 10:12:19 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495733538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.495733538
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1731640921
Short name	T223
Test name
Test status
Simulation time	11700281003 ps
CPU time	8.17 seconds
Started	Feb 08 10:12:15 AM UTC 25
Finished	Feb 08 10:12:26 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731640921 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.1731640921
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1521918057
Short name	T288
Test name
Test status
Simulation time	26823133291 ps
CPU time	66.4 seconds
Started	Feb 08 10:12:14 AM UTC 25
Finished	Feb 08 10:13:23 AM UTC 25
Peak memory	220168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1521918057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sy srst_ctrl_stress_all_with_rand_reset.1521918057
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.531026256
Short name	T118
Test name
Test status
Simulation time	216557305167 ps
CPU time	78.12 seconds
Started	Feb 08 10:12:13 AM UTC 25
Finished	Feb 08 10:13:34 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531026256 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.531026256
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3669551316
Short name	T601
Test name
Test status
Simulation time	2023292511 ps
CPU time	7.38 seconds
Started	Feb 08 10:12:29 AM UTC 25
Finished	Feb 08 10:12:38 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669551316 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.3669551316
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2282987385
Short name	T594
Test name
Test status
Simulation time	3184169210 ps
CPU time	5.33 seconds
Started	Feb 08 10:12:21 AM UTC 25
Finished	Feb 08 10:12:28 AM UTC 25
Peak memory	210124 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282987385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2282987385
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1283851699
Short name	T412
Test name
Test status
Simulation time	46306374321 ps
CPU time	190.19 seconds
Started	Feb 08 10:12:23 AM UTC 25
Finished	Feb 08 10:15:37 AM UTC 25
Peak memory	209896 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283851699 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.1283851699
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.202265181
Short name	T666
Test name
Test status
Simulation time	25327880441 ps
CPU time	107.29 seconds
Started	Feb 08 10:12:24 AM UTC 25
Finished	Feb 08 10:14:14 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202265181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.202265181
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.783755480
Short name	T593
Test name
Test status
Simulation time	3573457638 ps
CPU time	5.81 seconds
Started	Feb 08 10:12:20 AM UTC 25
Finished	Feb 08 10:12:27 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783755480 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.783755480
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2902208333
Short name	T595
Test name
Test status
Simulation time	4582655409 ps
CPU time	3.17 seconds
Started	Feb 08 10:12:24 AM UTC 25
Finished	Feb 08 10:12:29 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902208333 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.2902208333
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3386663835
Short name	T592
Test name
Test status
Simulation time	2633629901 ps
CPU time	3.83 seconds
Started	Feb 08 10:12:20 AM UTC 25
Finished	Feb 08 10:12:25 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386663835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3386663835
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1502299807
Short name	T591
Test name
Test status
Simulation time	2489094418 ps
CPU time	4.33 seconds
Started	Feb 08 10:12:17 AM UTC 25
Finished	Feb 08 10:12:23 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502299807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1502299807
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1879462164
Short name	T590
Test name
Test status
Simulation time	2115696738 ps
CPU time	3.45 seconds
Started	Feb 08 10:12:17 AM UTC 25
Finished	Feb 08 10:12:22 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879462164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1879462164
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.607069501
Short name	T597
Test name
Test status
Simulation time	2511614202 ps
CPU time	10.35 seconds
Started	Feb 08 10:12:19 AM UTC 25
Finished	Feb 08 10:12:31 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607069501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.607069501
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.204748412
Short name	T598
Test name
Test status
Simulation time	2111328958 ps
CPU time	13.33 seconds
Started	Feb 08 10:12:17 AM UTC 25
Finished	Feb 08 10:12:32 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204748412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.204748412
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2369061665
Short name	T612
Test name
Test status
Simulation time	12707681091 ps
CPU time	38.57 seconds
Started	Feb 08 10:12:27 AM UTC 25
Finished	Feb 08 10:13:07 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369061665 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.2369061665
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3503185190
Short name	T142
Test name
Test status
Simulation time	565502278173 ps
CPU time	83.26 seconds
Started	Feb 08 10:12:26 AM UTC 25
Finished	Feb 08 10:13:53 AM UTC 25
Peak memory	226216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3503185190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sy srst_ctrl_stress_all_with_rand_reset.3503185190
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.220435998
Short name	T262
Test name
Test status
Simulation time	1129740029019 ps
CPU time	70.71 seconds
Started	Feb 08 10:12:22 AM UTC 25
Finished	Feb 08 10:13:35 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220435998 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.220435998
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.2457983488
Short name	T273
Test name
Test status
Simulation time	2033714260 ps
CPU time	3.55 seconds
Started	Feb 08 10:12:42 AM UTC 25
Finished	Feb 08 10:12:47 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457983488 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.2457983488
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.44251706
Short name	T605
Test name
Test status
Simulation time	3342828213 ps
CPU time	2.35 seconds
Started	Feb 08 10:12:37 AM UTC 25
Finished	Feb 08 10:12:41 AM UTC 25
Peak memory	209864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44251706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.44251706
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.3226049816
Short name	T418
Test name
Test status
Simulation time	105784950919 ps
CPU time	295.23 seconds
Started	Feb 08 10:12:38 AM UTC 25
Finished	Feb 08 10:17:38 AM UTC 25
Peak memory	209984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226049816 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.3226049816
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.579224180
Short name	T673
Test name
Test status
Simulation time	35832020527 ps
CPU time	108.47 seconds
Started	Feb 08 10:12:40 AM UTC 25
Finished	Feb 08 10:14:31 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579224180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.579224180
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1713469382
Short name	T606
Test name
Test status
Simulation time	2937560340 ps
CPU time	3.62 seconds
Started	Feb 08 10:12:36 AM UTC 25
Finished	Feb 08 10:12:41 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713469382 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.1713469382
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.97943629
Short name	T207
Test name
Test status
Simulation time	5337779238 ps
CPU time	2.89 seconds
Started	Feb 08 10:12:38 AM UTC 25
Finished	Feb 08 10:12:43 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97943629 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.97943629
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3472404751
Short name	T602
Test name
Test status
Simulation time	2628345916 ps
CPU time	4.06 seconds
Started	Feb 08 10:12:33 AM UTC 25
Finished	Feb 08 10:12:39 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472404751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3472404751
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2602561532
Short name	T600
Test name
Test status
Simulation time	2463692031 ps
CPU time	7.16 seconds
Started	Feb 08 10:12:29 AM UTC 25
Finished	Feb 08 10:12:38 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602561532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.2602561532
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2036055191
Short name	T603
Test name
Test status
Simulation time	2231057596 ps
CPU time	7 seconds
Started	Feb 08 10:12:30 AM UTC 25
Finished	Feb 08 10:12:39 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036055191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.2036055191
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2140799564
Short name	T604
Test name
Test status
Simulation time	2519448082 ps
CPU time	7.69 seconds
Started	Feb 08 10:12:32 AM UTC 25
Finished	Feb 08 10:12:41 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140799564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2140799564
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3328585123
Short name	T599
Test name
Test status
Simulation time	2115329529 ps
CPU time	5.8 seconds
Started	Feb 08 10:12:29 AM UTC 25
Finished	Feb 08 10:12:36 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328585123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3328585123
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.4135713105
Short name	T208
Test name
Test status
Simulation time	10468152049 ps
CPU time	4.53 seconds
Started	Feb 08 10:12:40 AM UTC 25
Finished	Feb 08 10:12:46 AM UTC 25
Peak memory	210056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135713105 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.4135713105
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2660272643
Short name	T379
Test name
Test status
Simulation time	44731240119 ps
CPU time	154.38 seconds
Started	Feb 08 10:12:40 AM UTC 25
Finished	Feb 08 10:15:17 AM UTC 25
Peak memory	224612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2660272643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sy srst_ctrl_stress_all_with_rand_reset.2660272643
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.163872211
Short name	T648
Test name
Test status
Simulation time	1284892009548 ps
CPU time	74.69 seconds
Started	Feb 08 10:12:37 AM UTC 25
Finished	Feb 08 10:13:54 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163872211 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.163872211
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.1033120751
Short name	T596
Test name
Test status
Simulation time	2022995446 ps
CPU time	6.32 seconds
Started	Feb 08 10:12:55 AM UTC 25
Finished	Feb 08 10:13:03 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033120751 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.1033120751
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1522486849
Short name	T280
Test name
Test status
Simulation time	2988435819 ps
CPU time	6.45 seconds
Started	Feb 08 10:12:48 AM UTC 25
Finished	Feb 08 10:12:57 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522486849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1522486849
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1685871034
Short name	T143
Test name
Test status
Simulation time	34900019842 ps
CPU time	109.69 seconds
Started	Feb 08 10:12:48 AM UTC 25
Finished	Feb 08 10:14:41 AM UTC 25
Peak memory	209828 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685871034 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.1685871034
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1200701670
Short name	T281
Test name
Test status
Simulation time	2598671145 ps
CPU time	11.62 seconds
Started	Feb 08 10:12:47 AM UTC 25
Finished	Feb 08 10:13:01 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200701670 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.1200701670
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.2942641832
Short name	T583
Test name
Test status
Simulation time	2538181419 ps
CPU time	3.99 seconds
Started	Feb 08 10:12:48 AM UTC 25
Finished	Feb 08 10:12:54 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942641832 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.2942641832
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1920201161
Short name	T609
Test name
Test status
Simulation time	2611763129 ps
CPU time	15.27 seconds
Started	Feb 08 10:12:47 AM UTC 25
Finished	Feb 08 10:13:04 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920201161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1920201161
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.2404514861
Short name	T278
Test name
Test status
Simulation time	2453067713 ps
CPU time	6.91 seconds
Started	Feb 08 10:12:42 AM UTC 25
Finished	Feb 08 10:12:50 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404514861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2404514861
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.248529203
Short name	T276
Test name
Test status
Simulation time	2083240332 ps
CPU time	3.96 seconds
Started	Feb 08 10:12:42 AM UTC 25
Finished	Feb 08 10:12:47 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248529203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.248529203
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.725160209
Short name	T277
Test name
Test status
Simulation time	2529038071 ps
CPU time	2.56 seconds
Started	Feb 08 10:12:44 AM UTC 25
Finished	Feb 08 10:12:48 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725160209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.725160209
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.850087366
Short name	T275
Test name
Test status
Simulation time	2136802195 ps
CPU time	3.79 seconds
Started	Feb 08 10:12:42 AM UTC 25
Finished	Feb 08 10:12:47 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850087366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.850087366
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3410997253
Short name	T347
Test name
Test status
Simulation time	83557488002 ps
CPU time	112.71 seconds
Started	Feb 08 10:12:53 AM UTC 25
Finished	Feb 08 10:14:48 AM UTC 25
Peak memory	210164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410997253 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.3410997253
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2147302025
Short name	T660
Test name
Test status
Simulation time	17078674399 ps
CPU time	73.13 seconds
Started	Feb 08 10:12:52 AM UTC 25
Finished	Feb 08 10:14:07 AM UTC 25
Peak memory	210064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2147302025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sy srst_ctrl_stress_all_with_rand_reset.2147302025
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2821443045
Short name	T617
Test name
Test status
Simulation time	2039167269 ps
CPU time	3.28 seconds
Started	Feb 08 10:13:08 AM UTC 25
Finished	Feb 08 10:13:13 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821443045 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.2821443045
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1515795761
Short name	T613
Test name
Test status
Simulation time	3556571460 ps
CPU time	4.18 seconds
Started	Feb 08 10:13:03 AM UTC 25
Finished	Feb 08 10:13:09 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515795761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1515795761
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.591895351
Short name	T348
Test name
Test status
Simulation time	129220456289 ps
CPU time	101.38 seconds
Started	Feb 08 10:13:05 AM UTC 25
Finished	Feb 08 10:14:49 AM UTC 25
Peak memory	209840 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591895351 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.591895351
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1346181519
Short name	T322
Test name
Test status
Simulation time	119171827428 ps
CPU time	301.5 seconds
Started	Feb 08 10:13:06 AM UTC 25
Finished	Feb 08 10:18:12 AM UTC 25
Peak memory	210172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346181519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.1346181519
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2561158658
Short name	T616
Test name
Test status
Simulation time	4373122501 ps
CPU time	5.77 seconds
Started	Feb 08 10:13:03 AM UTC 25
Finished	Feb 08 10:13:11 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561158658 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.2561158658
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.4294197035
Short name	T224
Test name
Test status
Simulation time	3375345412 ps
CPU time	11.65 seconds
Started	Feb 08 10:13:06 AM UTC 25
Finished	Feb 08 10:13:19 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294197035 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.4294197035
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3208632711
Short name	T615
Test name
Test status
Simulation time	2620734192 ps
CPU time	7.17 seconds
Started	Feb 08 10:13:02 AM UTC 25
Finished	Feb 08 10:13:11 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208632711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3208632711
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.868750970
Short name	T611
Test name
Test status
Simulation time	2487455025 ps
CPU time	6.7 seconds
Started	Feb 08 10:12:57 AM UTC 25
Finished	Feb 08 10:13:05 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868750970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.868750970
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.844637016
Short name	T610
Test name
Test status
Simulation time	2215454228 ps
CPU time	2.87 seconds
Started	Feb 08 10:13:00 AM UTC 25
Finished	Feb 08 10:13:05 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844637016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.844637016
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3308044449
Short name	T608
Test name
Test status
Simulation time	2544419463 ps
CPU time	1.96 seconds
Started	Feb 08 10:13:00 AM UTC 25
Finished	Feb 08 10:13:04 AM UTC 25
Peak memory	208084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308044449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3308044449
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.1630706215
Short name	T607
Test name
Test status
Simulation time	2115839739 ps
CPU time	4.43 seconds
Started	Feb 08 10:12:57 AM UTC 25
Finished	Feb 08 10:13:03 AM UTC 25
Peak memory	209932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630706215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.1630706215
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3462164367
Short name	T270
Test name
Test status
Simulation time	12628636972 ps
CPU time	32.3 seconds
Started	Feb 08 10:13:07 AM UTC 25
Finished	Feb 08 10:13:41 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462164367 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.3462164367
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1305383036
Short name	T367
Test name
Test status
Simulation time	111426420214 ps
CPU time	89.22 seconds
Started	Feb 08 10:13:06 AM UTC 25
Finished	Feb 08 10:14:37 AM UTC 25
Peak memory	220324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1305383036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sy srst_ctrl_stress_all_with_rand_reset.1305383036
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1339908537
Short name	T614
Test name
Test status
Simulation time	8282697810 ps
CPU time	4.26 seconds
Started	Feb 08 10:13:03 AM UTC 25
Finished	Feb 08 10:13:10 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339908537 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.1339908537
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.629858128
Short name	T631
Test name
Test status
Simulation time	2012172260 ps
CPU time	6.08 seconds
Started	Feb 08 10:13:24 AM UTC 25
Finished	Feb 08 10:13:31 AM UTC 25
Peak memory	209904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629858128 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.629858128
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1226592694
Short name	T622
Test name
Test status
Simulation time	3231654571 ps
CPU time	4.76 seconds
Started	Feb 08 10:13:15 AM UTC 25
Finished	Feb 08 10:13:22 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226592694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1226592694
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.630024031
Short name	T774
Test name
Test status
Simulation time	93607997670 ps
CPU time	290.79 seconds
Started	Feb 08 10:13:20 AM UTC 25
Finished	Feb 08 10:18:14 AM UTC 25
Peak memory	210216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630024031 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.630024031
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.4044537976
Short name	T442
Test name
Test status
Simulation time	42768286482 ps
CPU time	48.31 seconds
Started	Feb 08 10:13:23 AM UTC 25
Finished	Feb 08 10:14:13 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044537976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.4044537976
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3894784702
Short name	T624
Test name
Test status
Simulation time	4176496395 ps
CPU time	6.76 seconds
Started	Feb 08 10:13:14 AM UTC 25
Finished	Feb 08 10:13:22 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894784702 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.3894784702
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2111182076
Short name	T209
Test name
Test status
Simulation time	4879223923 ps
CPU time	2.09 seconds
Started	Feb 08 10:13:20 AM UTC 25
Finished	Feb 08 10:13:23 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111182076 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.2111182076
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3192143002
Short name	T620
Test name
Test status
Simulation time	2643707863 ps
CPU time	2.54 seconds
Started	Feb 08 10:13:13 AM UTC 25
Finished	Feb 08 10:13:17 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192143002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3192143002
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.568868015
Short name	T621
Test name
Test status
Simulation time	2464871373 ps
CPU time	7.82 seconds
Started	Feb 08 10:13:10 AM UTC 25
Finished	Feb 08 10:13:19 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568868015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.568868015
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.264835964
Short name	T625
Test name
Test status
Simulation time	2212754507 ps
CPU time	10.86 seconds
Started	Feb 08 10:13:12 AM UTC 25
Finished	Feb 08 10:13:24 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264835964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.264835964
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.4283195214
Short name	T626
Test name
Test status
Simulation time	2511647721 ps
CPU time	13.1 seconds
Started	Feb 08 10:13:12 AM UTC 25
Finished	Feb 08 10:13:27 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283195214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.4283195214
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.4234799282
Short name	T618
Test name
Test status
Simulation time	2153055225 ps
CPU time	2.06 seconds
Started	Feb 08 10:13:10 AM UTC 25
Finished	Feb 08 10:13:13 AM UTC 25
Peak memory	209864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234799282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.4234799282
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.813546451
Short name	T627
Test name
Test status
Simulation time	7501434774 ps
CPU time	2.32 seconds
Started	Feb 08 10:13:24 AM UTC 25
Finished	Feb 08 10:13:28 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813546451 -assert nopostproc +UVM_TESTNAME=sysrst_ ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.813546451
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2622494011
Short name	T331
Test name
Test status
Simulation time	1215103514769 ps
CPU time	76.01 seconds
Started	Feb 08 10:13:24 AM UTC 25
Finished	Feb 08 10:14:42 AM UTC 25
Peak memory	226340 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2622494011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sy srst_ctrl_stress_all_with_rand_reset.2622494011
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.149079156
Short name	T623
Test name
Test status
Simulation time	2560699589 ps
CPU time	2.59 seconds
Started	Feb 08 10:13:18 AM UTC 25
Finished	Feb 08 10:13:22 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149079156 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.149079156
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2990027439
Short name	T266
Test name
Test status
Simulation time	2090792280 ps
CPU time	2.02 seconds
Started	Feb 08 10:13:33 AM UTC 25
Finished	Feb 08 10:13:37 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990027439 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.2990027439
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3887101619
Short name	T634
Test name
Test status
Simulation time	3538843604 ps
CPU time	4.77 seconds
Started	Feb 08 10:13:27 AM UTC 25
Finished	Feb 08 10:13:34 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887101619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3887101619
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.2682265784
Short name	T767
Test name
Test status
Simulation time	72576615574 ps
CPU time	241.84 seconds
Started	Feb 08 10:13:29 AM UTC 25
Finished	Feb 08 10:17:34 AM UTC 25
Peak memory	210220 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682265784 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.2682265784
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2901788275
Short name	T420
Test name
Test status
Simulation time	51554679887 ps
CPU time	44.65 seconds
Started	Feb 08 10:13:31 AM UTC 25
Finished	Feb 08 10:14:17 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901788275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.2901788275
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3692627171
Short name	T635
Test name
Test status
Simulation time	4267901690 ps
CPU time	6.01 seconds
Started	Feb 08 10:13:26 AM UTC 25
Finished	Feb 08 10:13:34 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692627171 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.3692627171
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.673937490
Short name	T264
Test name
Test status
Simulation time	4562994472 ps
CPU time	6.11 seconds
Started	Feb 08 10:13:29 AM UTC 25
Finished	Feb 08 10:13:36 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673937490 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.673937490
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1646412412
Short name	T633
Test name
Test status
Simulation time	2618381731 ps
CPU time	6.46 seconds
Started	Feb 08 10:13:25 AM UTC 25
Finished	Feb 08 10:13:33 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646412412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1646412412
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3260968360
Short name	T263
Test name
Test status
Simulation time	2475313444 ps
CPU time	8.91 seconds
Started	Feb 08 10:13:25 AM UTC 25
Finished	Feb 08 10:13:36 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260968360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3260968360
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.674546117
Short name	T628
Test name
Test status
Simulation time	2351236189 ps
CPU time	1.22 seconds
Started	Feb 08 10:13:25 AM UTC 25
Finished	Feb 08 10:13:28 AM UTC 25
Peak memory	208024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674546117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.674546117
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.629242584
Short name	T629
Test name
Test status
Simulation time	2541112095 ps
CPU time	3.29 seconds
Started	Feb 08 10:13:25 AM UTC 25
Finished	Feb 08 10:13:30 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629242584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.629242584
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1932246121
Short name	T630
Test name
Test status
Simulation time	2113253579 ps
CPU time	5.7 seconds
Started	Feb 08 10:13:24 AM UTC 25
Finished	Feb 08 10:13:31 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932246121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1932246121
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.3761767308
Short name	T672
Test name
Test status
Simulation time	13836596694 ps
CPU time	55.31 seconds
Started	Feb 08 10:13:33 AM UTC 25
Finished	Feb 08 10:14:30 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761767308 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.3761767308
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3048470299
Short name	T269
Test name
Test status
Simulation time	3149909252 ps
CPU time	10.16 seconds
Started	Feb 08 10:13:27 AM UTC 25
Finished	Feb 08 10:13:40 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048470299 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.3048470299
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2726367570
Short name	T646
Test name
Test status
Simulation time	2010643568 ps
CPU time	10.66 seconds
Started	Feb 08 10:13:40 AM UTC 25
Finished	Feb 08 10:13:52 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726367570 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.2726367570
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.737363326
Short name	T639
Test name
Test status
Simulation time	3685021355 ps
CPU time	4.33 seconds
Started	Feb 08 10:13:37 AM UTC 25
Finished	Feb 08 10:13:42 AM UTC 25
Peak memory	209836 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737363326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.737363326
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.1150225298
Short name	T417
Test name
Test status
Simulation time	66988749527 ps
CPU time	193.35 seconds
Started	Feb 08 10:13:38 AM UTC 25
Finished	Feb 08 10:16:54 AM UTC 25
Peak memory	209904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150225298 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.1150225298
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4264533188
Short name	T470
Test name
Test status
Simulation time	28841327903 ps
CPU time	44 seconds
Started	Feb 08 10:13:38 AM UTC 25
Finished	Feb 08 10:14:24 AM UTC 25
Peak memory	210160 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264533188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.4264533188
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3088765035
Short name	T645
Test name
Test status
Simulation time	3694766984 ps
CPU time	13.81 seconds
Started	Feb 08 10:13:35 AM UTC 25
Finished	Feb 08 10:13:51 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088765035 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.3088765035
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.793697435
Short name	T250
Test name
Test status
Simulation time	3700384136 ps
CPU time	7.73 seconds
Started	Feb 08 10:13:38 AM UTC 25
Finished	Feb 08 10:13:47 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793697435 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.793697435
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2411326836
Short name	T636
Test name
Test status
Simulation time	2633822173 ps
CPU time	4.1 seconds
Started	Feb 08 10:13:35 AM UTC 25
Finished	Feb 08 10:13:41 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411326836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.2411326836
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1265143502
Short name	T267
Test name
Test status
Simulation time	2512611681 ps
CPU time	2.4 seconds
Started	Feb 08 10:13:34 AM UTC 25
Finished	Feb 08 10:13:38 AM UTC 25
Peak memory	209616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265143502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1265143502
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.372801668
Short name	T640
Test name
Test status
Simulation time	2091044712 ps
CPU time	6.82 seconds
Started	Feb 08 10:13:35 AM UTC 25
Finished	Feb 08 10:13:44 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372801668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.372801668
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.365879344
Short name	T637
Test name
Test status
Simulation time	2523822990 ps
CPU time	4.45 seconds
Started	Feb 08 10:13:35 AM UTC 25
Finished	Feb 08 10:13:41 AM UTC 25
Peak memory	209780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365879344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.365879344
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1603400618
Short name	T268
Test name
Test status
Simulation time	2128730985 ps
CPU time	3.68 seconds
Started	Feb 08 10:13:34 AM UTC 25
Finished	Feb 08 10:13:39 AM UTC 25
Peak memory	209576 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603400618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1603400618
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2757431536
Short name	T454
Test name
Test status
Simulation time	86313282018 ps
CPU time	67.66 seconds
Started	Feb 08 10:13:40 AM UTC 25
Finished	Feb 08 10:14:50 AM UTC 25
Peak memory	209980 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757431536 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.2757431536
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.884745956
Short name	T109
Test name
Test status
Simulation time	447919792590 ps
CPU time	235.39 seconds
Started	Feb 08 10:13:39 AM UTC 25
Finished	Feb 08 10:17:38 AM UTC 25
Peak memory	220200 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=884745956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sys rst_ctrl_stress_all_with_rand_reset.884745956
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4257279206
Short name	T638
Test name
Test status
Simulation time	8364077044 ps
CPU time	4.1 seconds
Started	Feb 08 10:13:37 AM UTC 25
Finished	Feb 08 10:13:42 AM UTC 25
Peak memory	209552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257279206 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.4257279206
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3746294507
Short name	T650
Test name
Test status
Simulation time	2052507264 ps
CPU time	2.71 seconds
Started	Feb 08 10:13:52 AM UTC 25
Finished	Feb 08 10:13:56 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746294507 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.3746294507
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2324696026
Short name	T649
Test name
Test status
Simulation time	3295563284 ps
CPU time	9.95 seconds
Started	Feb 08 10:13:45 AM UTC 25
Finished	Feb 08 10:13:56 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324696026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2324696026
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.435356167
Short name	T349
Test name
Test status
Simulation time	87067417067 ps
CPU time	62.5 seconds
Started	Feb 08 10:13:48 AM UTC 25
Finished	Feb 08 10:14:52 AM UTC 25
Peak memory	210152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435356167 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.435356167
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3883899691
Short name	T475
Test name
Test status
Simulation time	149680525715 ps
CPU time	110.95 seconds
Started	Feb 08 10:13:49 AM UTC 25
Finished	Feb 08 10:15:42 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883899691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.3883899691
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.773132793
Short name	T647
Test name
Test status
Simulation time	5164980995 ps
CPU time	6.4 seconds
Started	Feb 08 10:13:44 AM UTC 25
Finished	Feb 08 10:13:52 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773132793 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.773132793
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.3708001819
Short name	T657
Test name
Test status
Simulation time	4271458898 ps
CPU time	11.78 seconds
Started	Feb 08 10:13:49 AM UTC 25
Finished	Feb 08 10:14:02 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708001819 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.3708001819
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1777417000
Short name	T643
Test name
Test status
Simulation time	2638718212 ps
CPU time	3.73 seconds
Started	Feb 08 10:13:43 AM UTC 25
Finished	Feb 08 10:13:49 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777417000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1777417000
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3514454396
Short name	T651
Test name
Test status
Simulation time	2450393433 ps
CPU time	14.36 seconds
Started	Feb 08 10:13:42 AM UTC 25
Finished	Feb 08 10:13:58 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514454396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3514454396
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3192673108
Short name	T641
Test name
Test status
Simulation time	2100423602 ps
CPU time	4.03 seconds
Started	Feb 08 10:13:42 AM UTC 25
Finished	Feb 08 10:13:48 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192673108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3192673108
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1817754325
Short name	T644
Test name
Test status
Simulation time	2523160077 ps
CPU time	4.48 seconds
Started	Feb 08 10:13:43 AM UTC 25
Finished	Feb 08 10:13:49 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817754325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1817754325
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.1106495323
Short name	T642
Test name
Test status
Simulation time	2124792074 ps
CPU time	4.25 seconds
Started	Feb 08 10:13:42 AM UTC 25
Finished	Feb 08 10:13:48 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106495323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1106495323
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.1101138658
Short name	T655
Test name
Test status
Simulation time	10889546247 ps
CPU time	9.02 seconds
Started	Feb 08 10:13:50 AM UTC 25
Finished	Feb 08 10:14:00 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101138658 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.1101138658
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.4166463798
Short name	T380
Test name
Test status
Simulation time	35889989410 ps
CPU time	113.72 seconds
Started	Feb 08 10:13:50 AM UTC 25
Finished	Feb 08 10:15:46 AM UTC 25
Peak memory	226596 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4166463798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sy srst_ctrl_stress_all_with_rand_reset.4166463798
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3373876246
Short name	T119
Test name
Test status
Simulation time	7991380120 ps
CPU time	12.71 seconds
Started	Feb 08 10:13:47 AM UTC 25
Finished	Feb 08 10:14:01 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373876246 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.3373876246
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2366705896
Short name	T661
Test name
Test status
Simulation time	2013219455 ps
CPU time	5.61 seconds
Started	Feb 08 10:14:03 AM UTC 25
Finished	Feb 08 10:14:10 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366705896 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.2366705896
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1664062870
Short name	T801
Test name
Test status
Simulation time	328601148428 ps
CPU time	899.78 seconds
Started	Feb 08 10:13:59 AM UTC 25
Finished	Feb 08 10:29:09 AM UTC 25
Peak memory	212460 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664062870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1664062870
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2278263916
Short name	T455
Test name
Test status
Simulation time	179505293022 ps
CPU time	130.27 seconds
Started	Feb 08 10:14:00 AM UTC 25
Finished	Feb 08 10:16:13 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278263916 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.2278263916
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.4193235345
Short name	T304
Test name
Test status
Simulation time	25355721438 ps
CPU time	25.47 seconds
Started	Feb 08 10:14:02 AM UTC 25
Finished	Feb 08 10:14:29 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193235345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.4193235345
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3992299416
Short name	T300
Test name
Test status
Simulation time	4696967247 ps
CPU time	27.68 seconds
Started	Feb 08 10:13:58 AM UTC 25
Finished	Feb 08 10:14:27 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992299416 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.3992299416
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.286388898
Short name	T271
Test name
Test status
Simulation time	4899584722 ps
CPU time	18.07 seconds
Started	Feb 08 10:14:02 AM UTC 25
Finished	Feb 08 10:14:22 AM UTC 25
Peak memory	209172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286388898 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.286388898
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3581930171
Short name	T658
Test name
Test status
Simulation time	2612746541 ps
CPU time	5.86 seconds
Started	Feb 08 10:13:56 AM UTC 25
Finished	Feb 08 10:14:04 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581930171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3581930171
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3541391496
Short name	T653
Test name
Test status
Simulation time	2467970940 ps
CPU time	4 seconds
Started	Feb 08 10:13:53 AM UTC 25
Finished	Feb 08 10:13:59 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541391496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3541391496
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.3438236517
Short name	T654
Test name
Test status
Simulation time	2085614000 ps
CPU time	5.65 seconds
Started	Feb 08 10:13:53 AM UTC 25
Finished	Feb 08 10:14:00 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438236517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.3438236517
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.251071730
Short name	T656
Test name
Test status
Simulation time	2531614138 ps
CPU time	5.08 seconds
Started	Feb 08 10:13:55 AM UTC 25
Finished	Feb 08 10:14:02 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251071730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.251071730
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2844955033
Short name	T659
Test name
Test status
Simulation time	2109326515 ps
CPU time	10.12 seconds
Started	Feb 08 10:13:53 AM UTC 25
Finished	Feb 08 10:14:05 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844955033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.2844955033
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.3340142604
Short name	T687
Test name
Test status
Simulation time	11133357195 ps
CPU time	37.92 seconds
Started	Feb 08 10:14:03 AM UTC 25
Finished	Feb 08 10:14:43 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340142604 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.3340142604
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1229529253
Short name	T366
Test name
Test status
Simulation time	7744538050 ps
CPU time	11.08 seconds
Started	Feb 08 10:14:02 AM UTC 25
Finished	Feb 08 10:14:15 AM UTC 25
Peak memory	209252 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1229529253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sy srst_ctrl_stress_all_with_rand_reset.1229529253
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2268953705
Short name	T662
Test name
Test status
Simulation time	9310794923 ps
CPU time	11.63 seconds
Started	Feb 08 10:14:00 AM UTC 25
Finished	Feb 08 10:14:13 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268953705 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.2268953705
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.1686114155
Short name	T158
Test name
Test status
Simulation time	2021452618 ps
CPU time	6.18 seconds
Started	Feb 08 10:05:32 AM UTC 25
Finished	Feb 08 10:05:40 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686114155 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.1686114155
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.884645167
Short name	T61
Test name
Test status
Simulation time	3150812163 ps
CPU time	10.94 seconds
Started	Feb 08 10:05:19 AM UTC 25
Finished	Feb 08 10:05:32 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884645167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.884645167
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3708650072
Short name	T346
Test name
Test status
Simulation time	99839639979 ps
CPU time	376.04 seconds
Started	Feb 08 10:05:25 AM UTC 25
Finished	Feb 08 10:11:47 AM UTC 25
Peak memory	210172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708650072 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.3708650072
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4243572487
Short name	T286
Test name
Test status
Simulation time	2161098063 ps
CPU time	6.56 seconds
Started	Feb 08 10:05:17 AM UTC 25
Finished	Feb 08 10:05:25 AM UTC 25
Peak memory	209984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243572487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.4243572487
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2894833465
Short name	T87
Test name
Test status
Simulation time	2525329952 ps
CPU time	4.98 seconds
Started	Feb 08 10:05:17 AM UTC 25
Finished	Feb 08 10:05:24 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894833465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2894833465
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2277164549
Short name	T285
Test name
Test status
Simulation time	2736949847 ps
CPU time	3.24 seconds
Started	Feb 08 10:05:19 AM UTC 25
Finished	Feb 08 10:05:24 AM UTC 25
Peak memory	210000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277164549 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.2277164549
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1103099880
Short name	T49
Test name
Test status
Simulation time	3319619952 ps
CPU time	4.46 seconds
Started	Feb 08 10:05:26 AM UTC 25
Finished	Feb 08 10:05:32 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103099880 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.1103099880
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.72493382
Short name	T478
Test name
Test status
Simulation time	2613205295 ps
CPU time	10.05 seconds
Started	Feb 08 10:05:19 AM UTC 25
Finished	Feb 08 10:05:30 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72493382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.72493382
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.4253045439
Short name	T76
Test name
Test status
Simulation time	2443401672 ps
CPU time	13.74 seconds
Started	Feb 08 10:05:17 AM UTC 25
Finished	Feb 08 10:05:33 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253045439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.4253045439
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.2888235244
Short name	T477
Test name
Test status
Simulation time	2162847274 ps
CPU time	11.32 seconds
Started	Feb 08 10:05:17 AM UTC 25
Finished	Feb 08 10:05:30 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888235244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.2888235244
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2115716452
Short name	T86
Test name
Test status
Simulation time	2524755321 ps
CPU time	5.18 seconds
Started	Feb 08 10:05:19 AM UTC 25
Finished	Feb 08 10:05:26 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115716452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.2115716452
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3359749638
Short name	T356
Test name
Test status
Simulation time	42015092792 ps
CPU time	134.86 seconds
Started	Feb 08 10:05:31 AM UTC 25
Finished	Feb 08 10:07:49 AM UTC 25
Peak memory	239600 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359749638 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3359749638
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1965138751
Short name	T283
Test name
Test status
Simulation time	2125978774 ps
CPU time	3.35 seconds
Started	Feb 08 10:05:12 AM UTC 25
Finished	Feb 08 10:05:17 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965138751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1965138751
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2944947686
Short name	T232
Test name
Test status
Simulation time	51776645390 ps
CPU time	180.02 seconds
Started	Feb 08 10:05:30 AM UTC 25
Finished	Feb 08 10:08:33 AM UTC 25
Peak memory	220260 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2944947686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sys rst_ctrl_stress_all_with_rand_reset.2944947686
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3591593627
Short name	T71
Test name
Test status
Simulation time	4049887865 ps
CPU time	2.74 seconds
Started	Feb 08 10:05:25 AM UTC 25
Finished	Feb 08 10:05:30 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591593627 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.3591593627
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2897550048
Short name	T299
Test name
Test status
Simulation time	2011092590 ps
CPU time	8.6 seconds
Started	Feb 08 10:14:17 AM UTC 25
Finished	Feb 08 10:14:27 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897550048 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.2897550048
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3190321470
Short name	T670
Test name
Test status
Simulation time	3189121172 ps
CPU time	8.76 seconds
Started	Feb 08 10:14:14 AM UTC 25
Finished	Feb 08 10:14:24 AM UTC 25
Peak memory	210020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190321470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3190321470
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3611722033
Short name	T332
Test name
Test status
Simulation time	38031582200 ps
CPU time	32.66 seconds
Started	Feb 08 10:14:15 AM UTC 25
Finished	Feb 08 10:14:49 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611722033 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.3611722033
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4048022059
Short name	T677
Test name
Test status
Simulation time	3738200537 ps
CPU time	18.76 seconds
Started	Feb 08 10:14:13 AM UTC 25
Finished	Feb 08 10:14:34 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048022059 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.4048022059
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1081228422
Short name	T671
Test name
Test status
Simulation time	2945338167 ps
CPU time	7.79 seconds
Started	Feb 08 10:14:15 AM UTC 25
Finished	Feb 08 10:14:24 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081228422 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.1081228422
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2490057231
Short name	T667
Test name
Test status
Simulation time	2635537119 ps
CPU time	2.96 seconds
Started	Feb 08 10:14:11 AM UTC 25
Finished	Feb 08 10:14:16 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490057231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2490057231
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3284964121
Short name	T664
Test name
Test status
Simulation time	2459904105 ps
CPU time	7.01 seconds
Started	Feb 08 10:14:05 AM UTC 25
Finished	Feb 08 10:14:14 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284964121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3284964121
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2031057218
Short name	T663
Test name
Test status
Simulation time	2036156021 ps
CPU time	5.67 seconds
Started	Feb 08 10:14:06 AM UTC 25
Finished	Feb 08 10:14:13 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031057218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.2031057218
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.736036829
Short name	T668
Test name
Test status
Simulation time	2509895402 ps
CPU time	8.24 seconds
Started	Feb 08 10:14:08 AM UTC 25
Finished	Feb 08 10:14:18 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736036829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.736036829
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.3824040697
Short name	T665
Test name
Test status
Simulation time	2109943485 ps
CPU time	8.51 seconds
Started	Feb 08 10:14:04 AM UTC 25
Finished	Feb 08 10:14:14 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824040697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.3824040697
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2164122870
Short name	T706
Test name
Test status
Simulation time	15339015777 ps
CPU time	42.35 seconds
Started	Feb 08 10:14:16 AM UTC 25
Finished	Feb 08 10:15:00 AM UTC 25
Peak memory	210120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164122870 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.2164122870
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3454383236
Short name	T378
Test name
Test status
Simulation time	3057375890 ps
CPU time	12.2 seconds
Started	Feb 08 10:14:16 AM UTC 25
Finished	Feb 08 10:14:29 AM UTC 25
Peak memory	209872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3454383236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sy srst_ctrl_stress_all_with_rand_reset.3454383236
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.820134571
Short name	T676
Test name
Test status
Simulation time	2020760298 ps
CPU time	3.56 seconds
Started	Feb 08 10:14:28 AM UTC 25
Finished	Feb 08 10:14:33 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820134571 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.820134571
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.619030264
Short name	T802
Test name
Test status
Simulation time	290147411737 ps
CPU time	937.54 seconds
Started	Feb 08 10:14:24 AM UTC 25
Finished	Feb 08 10:30:13 AM UTC 25
Peak memory	212456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619030264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.619030264
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1250986
Short name	T333
Test name
Test status
Simulation time	33732469764 ps
CPU time	31.72 seconds
Started	Feb 08 10:14:26 AM UTC 25
Finished	Feb 08 10:14:59 AM UTC 25
Peak memory	210236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250986 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.1250986
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2551141865
Short name	T303
Test name
Test status
Simulation time	3262282230 ps
CPU time	3.14 seconds
Started	Feb 08 10:14:24 AM UTC 25
Finished	Feb 08 10:14:29 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551141865 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.2551141865
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.3914311365
Short name	T247
Test name
Test status
Simulation time	3298388746 ps
CPU time	11.96 seconds
Started	Feb 08 10:14:27 AM UTC 25
Finished	Feb 08 10:14:41 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914311365 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.3914311365
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3516104544
Short name	T674
Test name
Test status
Simulation time	2613806130 ps
CPU time	5.89 seconds
Started	Feb 08 10:14:24 AM UTC 25
Finished	Feb 08 10:14:32 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516104544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3516104544
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1419436703
Short name	T302
Test name
Test status
Simulation time	2460505132 ps
CPU time	7.27 seconds
Started	Feb 08 10:14:19 AM UTC 25
Finished	Feb 08 10:14:28 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419436703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1419436703
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.3475788601
Short name	T296
Test name
Test status
Simulation time	2125985012 ps
CPU time	2.88 seconds
Started	Feb 08 10:14:21 AM UTC 25
Finished	Feb 08 10:14:25 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475788601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.3475788601
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.3069145764
Short name	T298
Test name
Test status
Simulation time	2546429944 ps
CPU time	2.53 seconds
Started	Feb 08 10:14:22 AM UTC 25
Finished	Feb 08 10:14:26 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069145764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3069145764
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3494390751
Short name	T669
Test name
Test status
Simulation time	2134686083 ps
CPU time	3.71 seconds
Started	Feb 08 10:14:18 AM UTC 25
Finished	Feb 08 10:14:23 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494390751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3494390751
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3092020102
Short name	T682
Test name
Test status
Simulation time	7290945186 ps
CPU time	9.92 seconds
Started	Feb 08 10:14:28 AM UTC 25
Finished	Feb 08 10:14:40 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092020102 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.3092020102
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1497688627
Short name	T382
Test name
Test status
Simulation time	92598566384 ps
CPU time	346.1 seconds
Started	Feb 08 10:14:27 AM UTC 25
Finished	Feb 08 10:20:18 AM UTC 25
Peak memory	220196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1497688627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sy srst_ctrl_stress_all_with_rand_reset.1497688627
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3236292540
Short name	T130
Test name
Test status
Simulation time	6290332007 ps
CPU time	8.24 seconds
Started	Feb 08 10:14:26 AM UTC 25
Finished	Feb 08 10:14:35 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236292540 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.3236292540
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1821456471
Short name	T692
Test name
Test status
Simulation time	2015020547 ps
CPU time	10.65 seconds
Started	Feb 08 10:14:36 AM UTC 25
Finished	Feb 08 10:14:48 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821456471 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.1821456471
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3974014080
Short name	T690
Test name
Test status
Simulation time	3266282483 ps
CPU time	14.37 seconds
Started	Feb 08 10:14:31 AM UTC 25
Finished	Feb 08 10:14:47 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974014080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3974014080
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.537970931
Short name	T122
Test name
Test status
Simulation time	30078113612 ps
CPU time	10.24 seconds
Started	Feb 08 10:14:35 AM UTC 25
Finished	Feb 08 10:14:46 AM UTC 25
Peak memory	210228 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537970931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.537970931
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1578366585
Short name	T804
Test name
Test status
Simulation time	616505701001 ps
CPU time	1767.3 seconds
Started	Feb 08 10:14:31 AM UTC 25
Finished	Feb 08 10:44:16 AM UTC 25
Peak memory	212396 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578366585 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.1578366585
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1824315366
Short name	T684
Test name
Test status
Simulation time	3535849256 ps
CPU time	4.89 seconds
Started	Feb 08 10:14:35 AM UTC 25
Finished	Feb 08 10:14:41 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824315366 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.1824315366
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2057332375
Short name	T683
Test name
Test status
Simulation time	2617663926 ps
CPU time	8.01 seconds
Started	Feb 08 10:14:30 AM UTC 25
Finished	Feb 08 10:14:40 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057332375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2057332375
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1003465603
Short name	T678
Test name
Test status
Simulation time	2486998969 ps
CPU time	3.86 seconds
Started	Feb 08 10:14:29 AM UTC 25
Finished	Feb 08 10:14:34 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003465603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1003465603
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1289145451
Short name	T680
Test name
Test status
Simulation time	2100652513 ps
CPU time	4.41 seconds
Started	Feb 08 10:14:30 AM UTC 25
Finished	Feb 08 10:14:36 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289145451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1289145451
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.1143138029
Short name	T679
Test name
Test status
Simulation time	2538387332 ps
CPU time	2.8 seconds
Started	Feb 08 10:14:30 AM UTC 25
Finished	Feb 08 10:14:34 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143138029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.1143138029
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2598499106
Short name	T675
Test name
Test status
Simulation time	2199435037 ps
CPU time	1.38 seconds
Started	Feb 08 10:14:29 AM UTC 25
Finished	Feb 08 10:14:32 AM UTC 25
Peak memory	208028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598499106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2598499106
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3644048641
Short name	T681
Test name
Test status
Simulation time	7954524194 ps
CPU time	4.26 seconds
Started	Feb 08 10:14:32 AM UTC 25
Finished	Feb 08 10:14:38 AM UTC 25
Peak memory	209680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644048641 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.3644048641
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.97700810
Short name	T694
Test name
Test status
Simulation time	2031889143 ps
CPU time	2.01 seconds
Started	Feb 08 10:14:48 AM UTC 25
Finished	Feb 08 10:14:51 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97700810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl _base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.97700810
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3673768102
Short name	T688
Test name
Test status
Simulation time	3448740531 ps
CPU time	3.93 seconds
Started	Feb 08 10:14:41 AM UTC 25
Finished	Feb 08 10:14:47 AM UTC 25
Peak memory	210044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673768102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3673768102
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.435343914
Short name	T416
Test name
Test status
Simulation time	160710738326 ps
CPU time	123.14 seconds
Started	Feb 08 10:14:42 AM UTC 25
Finished	Feb 08 10:16:48 AM UTC 25
Peak memory	209900 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435343914 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.435343914
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1648953917
Short name	T761
Test name
Test status
Simulation time	81333562769 ps
CPU time	116.71 seconds
Started	Feb 08 10:14:44 AM UTC 25
Finished	Feb 08 10:16:43 AM UTC 25
Peak memory	209896 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648953917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.1648953917
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1366705731
Short name	T698
Test name
Test status
Simulation time	2885325688 ps
CPU time	11.39 seconds
Started	Feb 08 10:14:41 AM UTC 25
Finished	Feb 08 10:14:54 AM UTC 25
Peak memory	209692 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366705731 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.1366705731
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3792501214
Short name	T759
Test name
Test status
Simulation time	942735501634 ps
CPU time	84.71 seconds
Started	Feb 08 10:14:42 AM UTC 25
Finished	Feb 08 10:16:09 AM UTC 25
Peak memory	209688 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792501214 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.3792501214
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.886790721
Short name	T693
Test name
Test status
Simulation time	2614904762 ps
CPU time	7.15 seconds
Started	Feb 08 10:14:40 AM UTC 25
Finished	Feb 08 10:14:49 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886790721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.886790721
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3419681649
Short name	T685
Test name
Test status
Simulation time	2489705723 ps
CPU time	2.6 seconds
Started	Feb 08 10:14:38 AM UTC 25
Finished	Feb 08 10:14:42 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419681649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3419681649
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.692676442
Short name	T686
Test name
Test status
Simulation time	2092610467 ps
CPU time	2.53 seconds
Started	Feb 08 10:14:39 AM UTC 25
Finished	Feb 08 10:14:43 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692676442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.692676442
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3799626356
Short name	T695
Test name
Test status
Simulation time	2510098152 ps
CPU time	10.46 seconds
Started	Feb 08 10:14:40 AM UTC 25
Finished	Feb 08 10:14:52 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799626356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3799626356
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.1875559509
Short name	T691
Test name
Test status
Simulation time	2113017489 ps
CPU time	9.49 seconds
Started	Feb 08 10:14:37 AM UTC 25
Finished	Feb 08 10:14:48 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875559509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.1875559509
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.80824953
Short name	T703
Test name
Test status
Simulation time	16433512402 ps
CPU time	10.74 seconds
Started	Feb 08 10:14:47 AM UTC 25
Finished	Feb 08 10:14:59 AM UTC 25
Peak memory	209716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80824953 -assert nopostproc +UVM_TESTNAME=sysrst_c trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.80824953
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1814197100
Short name	T689
Test name
Test status
Simulation time	7249586568 ps
CPU time	2.96 seconds
Started	Feb 08 10:14:42 AM UTC 25
Finished	Feb 08 10:14:47 AM UTC 25
Peak memory	209684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814197100 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.1814197100
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.587844755
Short name	T705
Test name
Test status
Simulation time	2016093965 ps
CPU time	4.63 seconds
Started	Feb 08 10:14:54 AM UTC 25
Finished	Feb 08 10:15:00 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587844755 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.587844755
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4005074822
Short name	T700
Test name
Test status
Simulation time	2803612440 ps
CPU time	5.86 seconds
Started	Feb 08 10:14:49 AM UTC 25
Finished	Feb 08 10:14:57 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005074822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.4005074822
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3271449763
Short name	T423
Test name
Test status
Simulation time	138368479347 ps
CPU time	423.71 seconds
Started	Feb 08 10:14:50 AM UTC 25
Finished	Feb 08 10:21:59 AM UTC 25
Peak memory	212480 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271449763 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.3271449763
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.843576764
Short name	T428
Test name
Test status
Simulation time	182178585398 ps
CPU time	153.88 seconds
Started	Feb 08 10:14:51 AM UTC 25
Finished	Feb 08 10:17:28 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843576764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.843576764
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1445137796
Short name	T699
Test name
Test status
Simulation time	4949846099 ps
CPU time	4.73 seconds
Started	Feb 08 10:14:49 AM UTC 25
Finished	Feb 08 10:14:56 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445137796 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.1445137796
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.1722729801
Short name	T242
Test name
Test status
Simulation time	3209653710 ps
CPU time	3.12 seconds
Started	Feb 08 10:14:50 AM UTC 25
Finished	Feb 08 10:14:55 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722729801 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.1722729801
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.86456662
Short name	T711
Test name
Test status
Simulation time	2609046534 ps
CPU time	13.17 seconds
Started	Feb 08 10:14:49 AM UTC 25
Finished	Feb 08 10:15:04 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86456662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.86456662
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.228213993
Short name	T697
Test name
Test status
Simulation time	2482890660 ps
CPU time	3.98 seconds
Started	Feb 08 10:14:48 AM UTC 25
Finished	Feb 08 10:14:54 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228213993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.228213993
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2834904296
Short name	T701
Test name
Test status
Simulation time	2136128084 ps
CPU time	7.03 seconds
Started	Feb 08 10:14:49 AM UTC 25
Finished	Feb 08 10:14:58 AM UTC 25
Peak memory	209620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834904296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.2834904296
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3023320456
Short name	T702
Test name
Test status
Simulation time	2517159117 ps
CPU time	7.18 seconds
Started	Feb 08 10:14:49 AM UTC 25
Finished	Feb 08 10:14:58 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023320456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3023320456
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.1001007873
Short name	T696
Test name
Test status
Simulation time	2137857866 ps
CPU time	2.68 seconds
Started	Feb 08 10:14:48 AM UTC 25
Finished	Feb 08 10:14:52 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001007873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.1001007873
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.1199143875
Short name	T752
Test name
Test status
Simulation time	13869866481 ps
CPU time	57.92 seconds
Started	Feb 08 10:14:54 AM UTC 25
Finished	Feb 08 10:15:54 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199143875 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.1199143875
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2901504593
Short name	T166
Test name
Test status
Simulation time	12459188931 ps
CPU time	14.11 seconds
Started	Feb 08 10:14:50 AM UTC 25
Finished	Feb 08 10:15:06 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901504593 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.2901504593
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.3358223398
Short name	T713
Test name
Test status
Simulation time	2036590327 ps
CPU time	4.52 seconds
Started	Feb 08 10:15:01 AM UTC 25
Finished	Feb 08 10:15:07 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358223398 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.3358223398
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4012902746
Short name	T718
Test name
Test status
Simulation time	3435145812 ps
CPU time	9.5 seconds
Started	Feb 08 10:14:59 AM UTC 25
Finished	Feb 08 10:15:10 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012902746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.4012902746
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.836969184
Short name	T452
Test name
Test status
Simulation time	125817872432 ps
CPU time	101.89 seconds
Started	Feb 08 10:15:00 AM UTC 25
Finished	Feb 08 10:16:45 AM UTC 25
Peak memory	210152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836969184 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.836969184
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3247755709
Short name	T434
Test name
Test status
Simulation time	124976776421 ps
CPU time	115.54 seconds
Started	Feb 08 10:15:00 AM UTC 25
Finished	Feb 08 10:16:58 AM UTC 25
Peak memory	210176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247755709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.3247755709
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1099999905
Short name	T710
Test name
Test status
Simulation time	3613601860 ps
CPU time	3.82 seconds
Started	Feb 08 10:14:58 AM UTC 25
Finished	Feb 08 10:15:03 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099999905 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.1099999905
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2970722514
Short name	T715
Test name
Test status
Simulation time	2643343091 ps
CPU time	6.23 seconds
Started	Feb 08 10:15:00 AM UTC 25
Finished	Feb 08 10:15:08 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970722514 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.2970722514
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3857311921
Short name	T712
Test name
Test status
Simulation time	2615075762 ps
CPU time	8.38 seconds
Started	Feb 08 10:14:57 AM UTC 25
Finished	Feb 08 10:15:07 AM UTC 25
Peak memory	209932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857311921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3857311921
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.447020963
Short name	T707
Test name
Test status
Simulation time	2492209932 ps
CPU time	4.32 seconds
Started	Feb 08 10:14:55 AM UTC 25
Finished	Feb 08 10:15:01 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447020963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.447020963
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2853847285
Short name	T709
Test name
Test status
Simulation time	2254807354 ps
CPU time	5.95 seconds
Started	Feb 08 10:14:55 AM UTC 25
Finished	Feb 08 10:15:02 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853847285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2853847285
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.316374635
Short name	T708
Test name
Test status
Simulation time	2517474495 ps
CPU time	4.61 seconds
Started	Feb 08 10:14:56 AM UTC 25
Finished	Feb 08 10:15:02 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316374635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.316374635
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2756973413
Short name	T704
Test name
Test status
Simulation time	2126471154 ps
CPU time	4.28 seconds
Started	Feb 08 10:14:54 AM UTC 25
Finished	Feb 08 10:14:59 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756973413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2756973413
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.3306371506
Short name	T735
Test name
Test status
Simulation time	9078391519 ps
CPU time	22.63 seconds
Started	Feb 08 10:15:01 AM UTC 25
Finished	Feb 08 10:15:26 AM UTC 25
Peak memory	209864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306371506 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.3306371506
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4033308032
Short name	T381
Test name
Test status
Simulation time	49940460009 ps
CPU time	106.41 seconds
Started	Feb 08 10:15:00 AM UTC 25
Finished	Feb 08 10:16:49 AM UTC 25
Peak memory	226480 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4033308032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sy srst_ctrl_stress_all_with_rand_reset.4033308032
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.388200823
Short name	T714
Test name
Test status
Simulation time	7611016438 ps
CPU time	7.31 seconds
Started	Feb 08 10:14:59 AM UTC 25
Finished	Feb 08 10:15:08 AM UTC 25
Peak memory	210056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388200823 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.388200823
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3677402385
Short name	T723
Test name
Test status
Simulation time	2017368655 ps
CPU time	5.26 seconds
Started	Feb 08 10:15:11 AM UTC 25
Finished	Feb 08 10:15:18 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677402385 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.3677402385
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3024131115
Short name	T720
Test name
Test status
Simulation time	4041874596 ps
CPU time	3.93 seconds
Started	Feb 08 10:15:07 AM UTC 25
Finished	Feb 08 10:15:12 AM UTC 25
Peak memory	209932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024131115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3024131115
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.668186974
Short name	T797
Test name
Test status
Simulation time	125058487534 ps
CPU time	462.58 seconds
Started	Feb 08 10:15:08 AM UTC 25
Finished	Feb 08 10:22:57 AM UTC 25
Peak memory	212760 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668186974 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.668186974
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1739091644
Short name	T427
Test name
Test status
Simulation time	52480304510 ps
CPU time	103.26 seconds
Started	Feb 08 10:15:09 AM UTC 25
Finished	Feb 08 10:16:55 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739091644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.1739091644
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2358122183
Short name	T729
Test name
Test status
Simulation time	3285528473 ps
CPU time	15.42 seconds
Started	Feb 08 10:15:07 AM UTC 25
Finished	Feb 08 10:15:24 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358122183 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.2358122183
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.648341723
Short name	T733
Test name
Test status
Simulation time	3879083982 ps
CPU time	14.59 seconds
Started	Feb 08 10:15:09 AM UTC 25
Finished	Feb 08 10:15:25 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648341723 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.648341723
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1671649957
Short name	T719
Test name
Test status
Simulation time	2634679894 ps
CPU time	2.09 seconds
Started	Feb 08 10:15:07 AM UTC 25
Finished	Feb 08 10:15:10 AM UTC 25
Peak memory	209996 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671649957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1671649957
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1052624772
Short name	T721
Test name
Test status
Simulation time	2456091452 ps
CPU time	10.19 seconds
Started	Feb 08 10:15:03 AM UTC 25
Finished	Feb 08 10:15:14 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052624772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1052624772
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.749998224
Short name	T716
Test name
Test status
Simulation time	2078783781 ps
CPU time	3.49 seconds
Started	Feb 08 10:15:04 AM UTC 25
Finished	Feb 08 10:15:09 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749998224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.749998224
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1460671110
Short name	T722
Test name
Test status
Simulation time	2511764648 ps
CPU time	11.29 seconds
Started	Feb 08 10:15:05 AM UTC 25
Finished	Feb 08 10:15:18 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460671110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.1460671110
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.3090695404
Short name	T717
Test name
Test status
Simulation time	2119850402 ps
CPU time	5.51 seconds
Started	Feb 08 10:15:03 AM UTC 25
Finished	Feb 08 10:15:10 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090695404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3090695404
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.1553525846
Short name	T727
Test name
Test status
Simulation time	12014136380 ps
CPU time	10 seconds
Started	Feb 08 10:15:10 AM UTC 25
Finished	Feb 08 10:15:22 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553525846 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.1553525846
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1980825660
Short name	T128
Test name
Test status
Simulation time	85719827244 ps
CPU time	56.87 seconds
Started	Feb 08 10:15:09 AM UTC 25
Finished	Feb 08 10:16:08 AM UTC 25
Peak memory	220248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1980825660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sy srst_ctrl_stress_all_with_rand_reset.1980825660
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3680619428
Short name	T726
Test name
Test status
Simulation time	3588713800 ps
CPU time	12.02 seconds
Started	Feb 08 10:15:08 AM UTC 25
Finished	Feb 08 10:15:21 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680619428 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.3680619428
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.299492960
Short name	T739
Test name
Test status
Simulation time	2014052670 ps
CPU time	10.59 seconds
Started	Feb 08 10:15:24 AM UTC 25
Finished	Feb 08 10:15:36 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299492960 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.299492960
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2783907772
Short name	T732
Test name
Test status
Simulation time	3767859857 ps
CPU time	4 seconds
Started	Feb 08 10:15:19 AM UTC 25
Finished	Feb 08 10:15:24 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783907772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2783907772
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.581427157
Short name	T788
Test name
Test status
Simulation time	76478046859 ps
CPU time	230.59 seconds
Started	Feb 08 10:15:21 AM UTC 25
Finished	Feb 08 10:19:16 AM UTC 25
Peak memory	210112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581427157 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.581427157
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3235710964
Short name	T471
Test name
Test status
Simulation time	123145256483 ps
CPU time	139.12 seconds
Started	Feb 08 10:15:22 AM UTC 25
Finished	Feb 08 10:17:45 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235710964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.3235710964
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2166045690
Short name	T734
Test name
Test status
Simulation time	3568714737 ps
CPU time	4.87 seconds
Started	Feb 08 10:15:19 AM UTC 25
Finished	Feb 08 10:15:25 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166045690 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.2166045690
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1458051177
Short name	T225
Test name
Test status
Simulation time	2947052999 ps
CPU time	4.69 seconds
Started	Feb 08 10:15:22 AM UTC 25
Finished	Feb 08 10:15:29 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458051177 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.1458051177
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3764857959
Short name	T736
Test name
Test status
Simulation time	2617345789 ps
CPU time	7.38 seconds
Started	Feb 08 10:15:18 AM UTC 25
Finished	Feb 08 10:15:27 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764857959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3764857959
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.631658526
Short name	T731
Test name
Test status
Simulation time	2479301010 ps
CPU time	8.93 seconds
Started	Feb 08 10:15:14 AM UTC 25
Finished	Feb 08 10:15:24 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631658526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.631658526
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.701284035
Short name	T724
Test name
Test status
Simulation time	2186545391 ps
CPU time	1.63 seconds
Started	Feb 08 10:15:16 AM UTC 25
Finished	Feb 08 10:15:19 AM UTC 25
Peak memory	208024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701284035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.701284035
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.3241546255
Short name	T728
Test name
Test status
Simulation time	2530681793 ps
CPU time	2.85 seconds
Started	Feb 08 10:15:18 AM UTC 25
Finished	Feb 08 10:15:22 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241546255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.3241546255
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3893234032
Short name	T725
Test name
Test status
Simulation time	2110896669 ps
CPU time	7.59 seconds
Started	Feb 08 10:15:11 AM UTC 25
Finished	Feb 08 10:15:21 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893234032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3893234032
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1837036370
Short name	T746
Test name
Test status
Simulation time	11089970752 ps
CPU time	19.31 seconds
Started	Feb 08 10:15:24 AM UTC 25
Finished	Feb 08 10:15:45 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837036370 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.1837036370
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1471176821
Short name	T766
Test name
Test status
Simulation time	47908621145 ps
CPU time	125.45 seconds
Started	Feb 08 10:15:23 AM UTC 25
Finished	Feb 08 10:17:31 AM UTC 25
Peak memory	220268 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1471176821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sy srst_ctrl_stress_all_with_rand_reset.1471176821
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3392498913
Short name	T730
Test name
Test status
Simulation time	4491643769 ps
CPU time	2.42 seconds
Started	Feb 08 10:15:20 AM UTC 25
Finished	Feb 08 10:15:24 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392498913 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.3392498913
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1660995163
Short name	T751
Test name
Test status
Simulation time	2010267418 ps
CPU time	11.11 seconds
Started	Feb 08 10:15:39 AM UTC 25
Finished	Feb 08 10:15:52 AM UTC 25
Peak memory	209924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660995163 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.1660995163
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2288773621
Short name	T740
Test name
Test status
Simulation time	3696228034 ps
CPU time	5.5 seconds
Started	Feb 08 10:15:30 AM UTC 25
Finished	Feb 08 10:15:37 AM UTC 25
Peak memory	209868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288773621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2288773621
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3945910844
Short name	T408
Test name
Test status
Simulation time	31025944406 ps
CPU time	14.25 seconds
Started	Feb 08 10:15:37 AM UTC 25
Finished	Feb 08 10:15:53 AM UTC 25
Peak memory	210176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945910844 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.3945910844
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4015976664
Short name	T448
Test name
Test status
Simulation time	37141617058 ps
CPU time	107.08 seconds
Started	Feb 08 10:15:38 AM UTC 25
Finished	Feb 08 10:17:28 AM UTC 25
Peak memory	210048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015976664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.4015976664
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3158227971
Short name	T738
Test name
Test status
Simulation time	4615324462 ps
CPU time	6.54 seconds
Started	Feb 08 10:15:28 AM UTC 25
Finished	Feb 08 10:15:36 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158227971 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.3158227971
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.1648898031
Short name	T295
Test name
Test status
Simulation time	3560589666 ps
CPU time	7.13 seconds
Started	Feb 08 10:15:38 AM UTC 25
Finished	Feb 08 10:15:47 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648898031 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.1648898031
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2489892767
Short name	T745
Test name
Test status
Simulation time	2610371737 ps
CPU time	16.07 seconds
Started	Feb 08 10:15:27 AM UTC 25
Finished	Feb 08 10:15:44 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489892767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2489892767
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3688293263
Short name	T737
Test name
Test status
Simulation time	2489668244 ps
CPU time	3.51 seconds
Started	Feb 08 10:15:25 AM UTC 25
Finished	Feb 08 10:15:30 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688293263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3688293263
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4041210833
Short name	T743
Test name
Test status
Simulation time	2174739935 ps
CPU time	11.49 seconds
Started	Feb 08 10:15:27 AM UTC 25
Finished	Feb 08 10:15:40 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041210833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.4041210833
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3388559013
Short name	T744
Test name
Test status
Simulation time	2512421099 ps
CPU time	13.02 seconds
Started	Feb 08 10:15:27 AM UTC 25
Finished	Feb 08 10:15:41 AM UTC 25
Peak memory	209776 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388559013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3388559013
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2414549229
Short name	T741
Test name
Test status
Simulation time	2112574623 ps
CPU time	10.55 seconds
Started	Feb 08 10:15:25 AM UTC 25
Finished	Feb 08 10:15:37 AM UTC 25
Peak memory	209784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414549229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2414549229
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.428501936
Short name	T799
Test name
Test status
Simulation time	173831361653 ps
CPU time	538.72 seconds
Started	Feb 08 10:15:38 AM UTC 25
Finished	Feb 08 10:24:44 AM UTC 25
Peak memory	212572 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428501936 -assert nopostproc +UVM_TESTNAME=sysrst_ ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.428501936
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.874713478
Short name	T765
Test name
Test status
Simulation time	44877988161 ps
CPU time	110.1 seconds
Started	Feb 08 10:15:38 AM UTC 25
Finished	Feb 08 10:17:31 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=874713478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sys rst_ctrl_stress_all_with_rand_reset.874713478
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4013996363
Short name	T742
Test name
Test status
Simulation time	6574572499 ps
CPU time	5.88 seconds
Started	Feb 08 10:15:31 AM UTC 25
Finished	Feb 08 10:15:39 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013996363 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.4013996363
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2366305628
Short name	T756
Test name
Test status
Simulation time	2096028264 ps
CPU time	1.89 seconds
Started	Feb 08 10:15:55 AM UTC 25
Finished	Feb 08 10:15:58 AM UTC 25
Peak memory	208092 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366305628 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.2366305628
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2069835774
Short name	T758
Test name
Test status
Simulation time	3870472152 ps
CPU time	19.72 seconds
Started	Feb 08 10:15:47 AM UTC 25
Finished	Feb 08 10:16:08 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069835774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2069835774
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2602481591
Short name	T792
Test name
Test status
Simulation time	113253437744 ps
CPU time	236.23 seconds
Started	Feb 08 10:15:48 AM UTC 25
Finished	Feb 08 10:19:48 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602481591 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.2602481591
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3845079203
Short name	T430
Test name
Test status
Simulation time	80331182656 ps
CPU time	36.14 seconds
Started	Feb 08 10:15:51 AM UTC 25
Finished	Feb 08 10:16:29 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845079203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.3845079203
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1783938885
Short name	T754
Test name
Test status
Simulation time	3869042576 ps
CPU time	6.23 seconds
Started	Feb 08 10:15:46 AM UTC 25
Finished	Feb 08 10:15:54 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783938885 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.1783938885
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3284974041
Short name	T757
Test name
Test status
Simulation time	4956949220 ps
CPU time	14.78 seconds
Started	Feb 08 10:15:50 AM UTC 25
Finished	Feb 08 10:16:07 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284974041 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.3284974041
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.990473578
Short name	T749
Test name
Test status
Simulation time	2635667701 ps
CPU time	4.24 seconds
Started	Feb 08 10:15:45 AM UTC 25
Finished	Feb 08 10:15:51 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990473578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.990473578
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3525906550
Short name	T747
Test name
Test status
Simulation time	2486576929 ps
CPU time	3.94 seconds
Started	Feb 08 10:15:42 AM UTC 25
Finished	Feb 08 10:15:47 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525906550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3525906550
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.1573744763
Short name	T755
Test name
Test status
Simulation time	2076400575 ps
CPU time	12.64 seconds
Started	Feb 08 10:15:43 AM UTC 25
Finished	Feb 08 10:15:57 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573744763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1573744763
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.2407694440
Short name	T748
Test name
Test status
Simulation time	2528376085 ps
CPU time	4.04 seconds
Started	Feb 08 10:15:44 AM UTC 25
Finished	Feb 08 10:15:49 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407694440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2407694440
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2691193915
Short name	T753
Test name
Test status
Simulation time	2108556052 ps
CPU time	11.54 seconds
Started	Feb 08 10:15:40 AM UTC 25
Finished	Feb 08 10:15:54 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691193915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2691193915
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2640798648
Short name	T760
Test name
Test status
Simulation time	7798299834 ps
CPU time	16.85 seconds
Started	Feb 08 10:15:53 AM UTC 25
Finished	Feb 08 10:16:12 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640798648 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.2640798648
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.33715971
Short name	T306
Test name
Test status
Simulation time	42949634714 ps
CPU time	41.83 seconds
Started	Feb 08 10:15:52 AM UTC 25
Finished	Feb 08 10:16:36 AM UTC 25
Peak memory	226404 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=33715971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysr st_ctrl_stress_all_with_rand_reset.33715971
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2277527385
Short name	T750
Test name
Test status
Simulation time	3008722920 ps
CPU time	2.02 seconds
Started	Feb 08 10:15:48 AM UTC 25
Finished	Feb 08 10:15:52 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277527385 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.2277527385
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.872878066
Short name	T167
Test name
Test status
Simulation time	2045247216 ps
CPU time	3.58 seconds
Started	Feb 08 10:05:47 AM UTC 25
Finished	Feb 08 10:05:52 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872878066 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.872878066
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2792859780
Short name	T62
Test name
Test status
Simulation time	3538521471 ps
CPU time	17.83 seconds
Started	Feb 08 10:05:41 AM UTC 25
Finished	Feb 08 10:06:00 AM UTC 25
Peak memory	210020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792859780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2792859780
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2179412647
Short name	T42
Test name
Test status
Simulation time	54828539922 ps
CPU time	51.51 seconds
Started	Feb 08 10:05:43 AM UTC 25
Finished	Feb 08 10:06:37 AM UTC 25
Peak memory	209720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179412647 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.2179412647
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2261499749
Short name	T89
Test name
Test status
Simulation time	31587772496 ps
CPU time	72.15 seconds
Started	Feb 08 10:05:44 AM UTC 25
Finished	Feb 08 10:06:59 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261499749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.2261499749
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3923952611
Short name	T248
Test name
Test status
Simulation time	4170023423 ps
CPU time	6.03 seconds
Started	Feb 08 10:05:39 AM UTC 25
Finished	Feb 08 10:05:46 AM UTC 25
Peak memory	210000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923952611 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.3923952611
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.7707735
Short name	T53
Test name
Test status
Simulation time	4030912535 ps
CPU time	8.82 seconds
Started	Feb 08 10:05:43 AM UTC 25
Finished	Feb 08 10:05:53 AM UTC 25
Peak memory	209656 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7707735 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.7707735
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2728880660
Short name	T160
Test name
Test status
Simulation time	2623227276 ps
CPU time	4.6 seconds
Started	Feb 08 10:05:39 AM UTC 25
Finished	Feb 08 10:05:45 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728880660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2728880660
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3491608673
Short name	T77
Test name
Test status
Simulation time	2622403959 ps
CPU time	1.56 seconds
Started	Feb 08 10:05:33 AM UTC 25
Finished	Feb 08 10:05:37 AM UTC 25
Peak memory	208080 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491608673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3491608673
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2794802972
Short name	T157
Test name
Test status
Simulation time	2137613963 ps
CPU time	3.03 seconds
Started	Feb 08 10:05:34 AM UTC 25
Finished	Feb 08 10:05:38 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794802972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2794802972
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2561298049
Short name	T159
Test name
Test status
Simulation time	2538303907 ps
CPU time	3.97 seconds
Started	Feb 08 10:05:38 AM UTC 25
Finished	Feb 08 10:05:43 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561298049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2561298049
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1460450821
Short name	T161
Test name
Test status
Simulation time	2114389441 ps
CPU time	10.16 seconds
Started	Feb 08 10:05:33 AM UTC 25
Finished	Feb 08 10:05:45 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460450821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1460450821
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3722897264
Short name	T147
Test name
Test status
Simulation time	7300546239 ps
CPU time	32.17 seconds
Started	Feb 08 10:05:46 AM UTC 25
Finished	Feb 08 10:06:20 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722897264 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.3722897264
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1992069803
Short name	T436
Test name
Test status
Simulation time	142851728137 ps
CPU time	129.9 seconds
Started	Feb 08 10:15:55 AM UTC 25
Finished	Feb 08 10:18:07 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992069803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.1992069803
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3815606940
Short name	T424
Test name
Test status
Simulation time	76791265966 ps
CPU time	255.5 seconds
Started	Feb 08 10:15:55 AM UTC 25
Finished	Feb 08 10:20:14 AM UTC 25
Peak memory	209956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815606940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.3815606940
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2602061061
Short name	T437
Test name
Test status
Simulation time	85181044583 ps
CPU time	66.23 seconds
Started	Feb 08 10:15:58 AM UTC 25
Finished	Feb 08 10:17:06 AM UTC 25
Peak memory	209980 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602061061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.2602061061
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3588530917
Short name	T438
Test name
Test status
Simulation time	100376762112 ps
CPU time	135.93 seconds
Started	Feb 08 10:15:59 AM UTC 25
Finished	Feb 08 10:18:17 AM UTC 25
Peak memory	210236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588530917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.3588530917
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2740251937
Short name	T443
Test name
Test status
Simulation time	144415820551 ps
CPU time	139.22 seconds
Started	Feb 08 10:16:08 AM UTC 25
Finished	Feb 08 10:18:31 AM UTC 25
Peak memory	210116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740251937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.2740251937
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.219388431
Short name	T415
Test name
Test status
Simulation time	71969407953 ps
CPU time	108.02 seconds
Started	Feb 08 10:16:09 AM UTC 25
Finished	Feb 08 10:18:00 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219388431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.219388431
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2041518442
Short name	T773
Test name
Test status
Simulation time	58941896002 ps
CPU time	113.17 seconds
Started	Feb 08 10:16:09 AM UTC 25
Finished	Feb 08 10:18:05 AM UTC 25
Peak memory	210296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041518442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.2041518442
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3975193265
Short name	T146
Test name
Test status
Simulation time	2011783045 ps
CPU time	12.18 seconds
Started	Feb 08 10:06:06 AM UTC 25
Finished	Feb 08 10:06:20 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975193265 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.3975193265
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2486377155
Short name	T63
Test name
Test status
Simulation time	3826075573 ps
CPU time	6.69 seconds
Started	Feb 08 10:06:00 AM UTC 25
Finished	Feb 08 10:06:08 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486377155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2486377155
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.530123257
Short name	T251
Test name
Test status
Simulation time	64539939986 ps
CPU time	94.16 seconds
Started	Feb 08 10:06:03 AM UTC 25
Finished	Feb 08 10:07:39 AM UTC 25
Peak memory	209844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530123257 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.530123257
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3781209354
Short name	T479
Test name
Test status
Simulation time	2623408812 ps
CPU time	5.09 seconds
Started	Feb 08 10:05:59 AM UTC 25
Finished	Feb 08 10:06:06 AM UTC 25
Peak memory	210000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781209354 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.3781209354
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2303706774
Short name	T52
Test name
Test status
Simulation time	2476615295 ps
CPU time	8.09 seconds
Started	Feb 08 10:06:04 AM UTC 25
Finished	Feb 08 10:06:14 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303706774 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.2303706774
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.107246871
Short name	T145
Test name
Test status
Simulation time	2610283108 ps
CPU time	11.25 seconds
Started	Feb 08 10:05:57 AM UTC 25
Finished	Feb 08 10:06:10 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107246871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.107246871
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.855892837
Short name	T78
Test name
Test status
Simulation time	2497710524 ps
CPU time	3.94 seconds
Started	Feb 08 10:05:51 AM UTC 25
Finished	Feb 08 10:05:56 AM UTC 25
Peak memory	209724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855892837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.855892837
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.4245523757
Short name	T169
Test name
Test status
Simulation time	2200351025 ps
CPU time	6.56 seconds
Started	Feb 08 10:05:54 AM UTC 25
Finished	Feb 08 10:06:02 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245523757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.4245523757
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.530701657
Short name	T170
Test name
Test status
Simulation time	2518541165 ps
CPU time	7.28 seconds
Started	Feb 08 10:05:55 AM UTC 25
Finished	Feb 08 10:06:03 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530701657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.530701657
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.1958919982
Short name	T168
Test name
Test status
Simulation time	2108648098 ps
CPU time	10.43 seconds
Started	Feb 08 10:05:47 AM UTC 25
Finished	Feb 08 10:05:59 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958919982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1958919982
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.4109232442
Short name	T217
Test name
Test status
Simulation time	15610920020 ps
CPU time	59.17 seconds
Started	Feb 08 10:06:06 AM UTC 25
Finished	Feb 08 10:07:08 AM UTC 25
Peak memory	210000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109232442 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.4109232442
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.728271915
Short name	T70
Test name
Test status
Simulation time	4132369004 ps
CPU time	3.22 seconds
Started	Feb 08 10:06:01 AM UTC 25
Finished	Feb 08 10:06:06 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728271915 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.728271915
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1142055358
Short name	T762
Test name
Test status
Simulation time	39376520272 ps
CPU time	48.44 seconds
Started	Feb 08 10:16:09 AM UTC 25
Finished	Feb 08 10:17:00 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142055358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.1142055358
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2816374092
Short name	T768
Test name
Test status
Simulation time	25831826768 ps
CPU time	83.24 seconds
Started	Feb 08 10:16:10 AM UTC 25
Finished	Feb 08 10:17:36 AM UTC 25
Peak memory	210160 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816374092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.2816374092
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.699429591
Short name	T449
Test name
Test status
Simulation time	115649657706 ps
CPU time	84.03 seconds
Started	Feb 08 10:16:10 AM UTC 25
Finished	Feb 08 10:17:37 AM UTC 25
Peak memory	210024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699429591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.699429591
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2888057335
Short name	T791
Test name
Test status
Simulation time	42358826896 ps
CPU time	205.63 seconds
Started	Feb 08 10:16:13 AM UTC 25
Finished	Feb 08 10:19:43 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888057335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.2888057335
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.614130733
Short name	T776
Test name
Test status
Simulation time	26332438325 ps
CPU time	107.89 seconds
Started	Feb 08 10:16:28 AM UTC 25
Finished	Feb 08 10:18:18 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614130733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.614130733
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1715304222
Short name	T763
Test name
Test status
Simulation time	22334480723 ps
CPU time	40.48 seconds
Started	Feb 08 10:16:31 AM UTC 25
Finished	Feb 08 10:17:13 AM UTC 25
Peak memory	210232 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715304222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.1715304222
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3055934058
Short name	T781
Test name
Test status
Simulation time	99363598998 ps
CPU time	119.4 seconds
Started	Feb 08 10:16:37 AM UTC 25
Finished	Feb 08 10:18:39 AM UTC 25
Peak memory	210296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055934058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.3055934058
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1535235405
Short name	T764
Test name
Test status
Simulation time	24593891992 ps
CPU time	33.44 seconds
Started	Feb 08 10:16:44 AM UTC 25
Finished	Feb 08 10:17:19 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535235405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.1535235405
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2983444448
Short name	T445
Test name
Test status
Simulation time	54627482527 ps
CPU time	19.46 seconds
Started	Feb 08 10:16:46 AM UTC 25
Finished	Feb 08 10:17:07 AM UTC 25
Peak memory	209960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983444448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.2983444448
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.2218408203
Short name	T153
Test name
Test status
Simulation time	2017085320 ps
CPU time	5.99 seconds
Started	Feb 08 10:06:35 AM UTC 25
Finished	Feb 08 10:06:42 AM UTC 25
Peak memory	209740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218408203 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.2218408203
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.778679471
Short name	T64
Test name
Test status
Simulation time	3563560754 ps
CPU time	9.08 seconds
Started	Feb 08 10:06:24 AM UTC 25
Finished	Feb 08 10:06:34 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778679471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.778679471
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.4222990453
Short name	T318
Test name
Test status
Simulation time	112979823932 ps
CPU time	95.73 seconds
Started	Feb 08 10:06:28 AM UTC 25
Finished	Feb 08 10:08:06 AM UTC 25
Peak memory	209960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222990453 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.4222990453
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.221609788
Short name	T90
Test name
Test status
Simulation time	24091361910 ps
CPU time	36.94 seconds
Started	Feb 08 10:06:30 AM UTC 25
Finished	Feb 08 10:07:09 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221609788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.221609788
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3632467930
Short name	T151
Test name
Test status
Simulation time	3551737870 ps
CPU time	5.67 seconds
Started	Feb 08 10:06:23 AM UTC 25
Finished	Feb 08 10:06:30 AM UTC 25
Peak memory	210000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632467930 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.3632467930
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.267686389
Short name	T48
Test name
Test status
Simulation time	2755240236 ps
CPU time	4.45 seconds
Started	Feb 08 10:06:30 AM UTC 25
Finished	Feb 08 10:06:36 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267686389 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.267686389
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.933692812
Short name	T480
Test name
Test status
Simulation time	2610533981 ps
CPU time	11.19 seconds
Started	Feb 08 10:06:21 AM UTC 25
Finished	Feb 08 10:06:34 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933692812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.933692812
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.449416124
Short name	T79
Test name
Test status
Simulation time	2469864656 ps
CPU time	16.83 seconds
Started	Feb 08 10:06:11 AM UTC 25
Finished	Feb 08 10:06:29 AM UTC 25
Peak memory	209924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449416124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.449416124
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2037266785
Short name	T149
Test name
Test status
Simulation time	2094552793 ps
CPU time	9.86 seconds
Started	Feb 08 10:06:15 AM UTC 25
Finished	Feb 08 10:06:26 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037266785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2037266785
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.2714051619
Short name	T150
Test name
Test status
Simulation time	2538045358 ps
CPU time	5.03 seconds
Started	Feb 08 10:06:21 AM UTC 25
Finished	Feb 08 10:06:27 AM UTC 25
Peak memory	210116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714051619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2714051619
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.199060412
Short name	T148
Test name
Test status
Simulation time	2110217604 ps
CPU time	12.5 seconds
Started	Feb 08 10:06:08 AM UTC 25
Finished	Feb 08 10:06:22 AM UTC 25
Peak memory	209660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199060412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.199060412
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.444431553
Short name	T73
Test name
Test status
Simulation time	743158578630 ps
CPU time	17.09 seconds
Started	Feb 08 10:06:27 AM UTC 25
Finished	Feb 08 10:06:46 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444431553 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.444431553
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3277494576
Short name	T771
Test name
Test status
Simulation time	28584284267 ps
CPU time	55.84 seconds
Started	Feb 08 10:16:49 AM UTC 25
Finished	Feb 08 10:17:47 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277494576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.3277494576
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1518430709
Short name	T795
Test name
Test status
Simulation time	76176185621 ps
CPU time	216.11 seconds
Started	Feb 08 10:16:50 AM UTC 25
Finished	Feb 08 10:20:30 AM UTC 25
Peak memory	209980 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518430709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.1518430709
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3687466809
Short name	T784
Test name
Test status
Simulation time	67918072998 ps
CPU time	110.93 seconds
Started	Feb 08 10:16:55 AM UTC 25
Finished	Feb 08 10:18:49 AM UTC 25
Peak memory	210048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687466809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.3687466809
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3568156759
Short name	T323
Test name
Test status
Simulation time	69257055165 ps
CPU time	120.49 seconds
Started	Feb 08 10:16:55 AM UTC 25
Finished	Feb 08 10:18:59 AM UTC 25
Peak memory	210304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568156759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.3568156759
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1204496928
Short name	T796
Test name
Test status
Simulation time	72732615148 ps
CPU time	235.79 seconds
Started	Feb 08 10:16:59 AM UTC 25
Finished	Feb 08 10:20:59 AM UTC 25
Peak memory	210304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204496928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.1204496928
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2136463937
Short name	T778
Test name
Test status
Simulation time	84983389703 ps
CPU time	79.07 seconds
Started	Feb 08 10:17:01 AM UTC 25
Finished	Feb 08 10:18:23 AM UTC 25
Peak memory	209956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136463937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.2136463937
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1863744077
Short name	T785
Test name
Test status
Simulation time	95303073456 ps
CPU time	110.45 seconds
Started	Feb 08 10:17:06 AM UTC 25
Finished	Feb 08 10:19:00 AM UTC 25
Peak memory	209956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863744077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.1863744077
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1199821914
Short name	T770
Test name
Test status
Simulation time	63048148122 ps
CPU time	32.33 seconds
Started	Feb 08 10:17:08 AM UTC 25
Finished	Feb 08 10:17:43 AM UTC 25
Peak memory	210232 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199821914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.1199821914
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3395989364
Short name	T789
Test name
Test status
Simulation time	37525283213 ps
CPU time	122.93 seconds
Started	Feb 08 10:17:14 AM UTC 25
Finished	Feb 08 10:19:19 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395989364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.3395989364
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3503387715
Short name	T435
Test name
Test status
Simulation time	84230723860 ps
CPU time	34.94 seconds
Started	Feb 08 10:17:18 AM UTC 25
Finished	Feb 08 10:17:54 AM UTC 25
Peak memory	209884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503387715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.3503387715
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2441868319
Short name	T485
Test name
Test status
Simulation time	2011109747 ps
CPU time	8.73 seconds
Started	Feb 08 10:06:54 AM UTC 25
Finished	Feb 08 10:07:04 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441868319 -assert nopostproc +UVM_TESTNAME=sysrst_ct rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.2441868319
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.925175164
Short name	T133
Test name
Test status
Simulation time	3284519545 ps
CPU time	11.25 seconds
Started	Feb 08 10:06:43 AM UTC 25
Finished	Feb 08 10:06:56 AM UTC 25
Peak memory	210056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925175164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.925175164
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2910494394
Short name	T91
Test name
Test status
Simulation time	92664328361 ps
CPU time	67.12 seconds
Started	Feb 08 10:06:47 AM UTC 25
Finished	Feb 08 10:07:56 AM UTC 25
Peak memory	209892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910494394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.2910494394
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1575631372
Short name	T228
Test name
Test status
Simulation time	2774260421 ps
CPU time	10.32 seconds
Started	Feb 08 10:06:43 AM UTC 25
Finished	Feb 08 10:06:55 AM UTC 25
Peak memory	209736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575631372 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.1575631372
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.4160361011
Short name	T50
Test name
Test status
Simulation time	4281112722 ps
CPU time	6.32 seconds
Started	Feb 08 10:06:47 AM UTC 25
Finished	Feb 08 10:06:55 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160361011 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.4160361011
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.252921031
Short name	T155
Test name
Test status
Simulation time	2631278857 ps
CPU time	4.08 seconds
Started	Feb 08 10:06:39 AM UTC 25
Finished	Feb 08 10:06:45 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252921031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.252921031
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.98105896
Short name	T80
Test name
Test status
Simulation time	2486017619 ps
CPU time	3.67 seconds
Started	Feb 08 10:06:37 AM UTC 25
Finished	Feb 08 10:06:42 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98105896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.98105896
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.3341442151
Short name	T226
Test name
Test status
Simulation time	2226370900 ps
CPU time	14.32 seconds
Started	Feb 08 10:06:37 AM UTC 25
Finished	Feb 08 10:06:53 AM UTC 25
Peak memory	209728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341442151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3341442151
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1644822976
Short name	T227
Test name
Test status
Simulation time	2513285784 ps
CPU time	14.8 seconds
Started	Feb 08 10:06:38 AM UTC 25
Finished	Feb 08 10:06:55 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644822976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1644822976
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.116444968
Short name	T154
Test name
Test status
Simulation time	2122431746 ps
CPU time	6.12 seconds
Started	Feb 08 10:06:36 AM UTC 25
Finished	Feb 08 10:06:44 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116444968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.116444968
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2197714748
Short name	T175
Test name
Test status
Simulation time	15136671384 ps
CPU time	28.33 seconds
Started	Feb 08 10:06:52 AM UTC 25
Finished	Feb 08 10:07:22 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197714748 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.2197714748
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1843622759
Short name	T193
Test name
Test status
Simulation time	40611053464 ps
CPU time	127.49 seconds
Started	Feb 08 10:06:51 AM UTC 25
Finished	Feb 08 10:09:01 AM UTC 25
Peak memory	222416 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrs t_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1843622759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sys rst_ctrl_stress_all_with_rand_reset.1843622759
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2261889761
Short name	T96
Test name
Test status
Simulation time	4874150178 ps
CPU time	8.32 seconds
Started	Feb 08 10:06:44 AM UTC 25
Finished	Feb 08 10:06:55 AM UTC 25
Peak memory	209808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261889761 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.2261889761
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3976058015
Short name	T447
Test name
Test status
Simulation time	55218866551 ps
CPU time	45.2 seconds
Started	Feb 08 10:17:20 AM UTC 25
Finished	Feb 08 10:18:07 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976058015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.3976058015
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3513489044
Short name	T779
Test name
Test status
Simulation time	28086098081 ps
CPU time	59.2 seconds
Started	Feb 08 10:17:29 AM UTC 25
Finished	Feb 08 10:18:30 AM UTC 25
Peak memory	210232 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513489044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.3513489044
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3689215284
Short name	T432
Test name
Test status
Simulation time	26353939792 ps
CPU time	10.43 seconds
Started	Feb 08 10:17:29 AM UTC 25
Finished	Feb 08 10:17:41 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689215284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.3689215284
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1388692577
Short name	T472
Test name
Test status
Simulation time	53594770618 ps
CPU time	32.2 seconds
Started	Feb 08 10:17:29 AM UTC 25
Finished	Feb 08 10:18:03 AM UTC 25
Peak memory	210296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388692577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.1388692577
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1140644811
Short name	T793
Test name
Test status
Simulation time	177428577308 ps
CPU time	138.97 seconds
Started	Feb 08 10:17:32 AM UTC 25
Finished	Feb 08 10:19:54 AM UTC 25
Peak memory	210304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140644811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.1140644811
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2115860633
Short name	T775
Test name
Test status
Simulation time	25833334709 ps
CPU time	41.18 seconds
Started	Feb 08 10:17:34 AM UTC 25
Finished	Feb 08 10:18:17 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115860633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.2115860633
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.43747656
Short name	T786
Test name
Test status
Simulation time	67953683450 ps
CPU time	83.84 seconds
Started	Feb 08 10:17:35 AM UTC 25
Finished	Feb 08 10:19:02 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43747656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.43747656
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.848084338
Short name	T772
Test name
Test status
Simulation time	43862261057 ps
CPU time	27.4 seconds
Started	Feb 08 10:17:36 AM UTC 25
Finished	Feb 08 10:18:05 AM UTC 25
Peak memory	210228 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848084338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.848084338
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.280847798
Short name	T787
Test name
Test status
Simulation time	50434877502 ps
CPU time	88.24 seconds
Started	Feb 08 10:17:37 AM UTC 25
Finished	Feb 08 10:19:08 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280847798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.280847798
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.596181375
Short name	T309
Test name
Test status
Simulation time	2011241011 ps
CPU time	6.79 seconds
Started	Feb 08 10:07:04 AM UTC 25
Finished	Feb 08 10:07:12 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596181375 -assert nopostproc +UVM_TESTNAME=sysrst_ctr l_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.596181375
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3755508054
Short name	T156
Test name
Test status
Simulation time	3704127635 ps
CPU time	3.44 seconds
Started	Feb 08 10:06:57 AM UTC 25
Finished	Feb 08 10:07:02 AM UTC 25
Peak memory	210048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755508054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3755508054
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.4005860126
Short name	T410
Test name
Test status
Simulation time	170993337108 ps
CPU time	261.2 seconds
Started	Feb 08 10:07:01 AM UTC 25
Finished	Feb 08 10:11:26 AM UTC 25
Peak memory	210164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005860126 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.4005860126
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3157007830
Short name	T124
Test name
Test status
Simulation time	88279836928 ps
CPU time	101.4 seconds
Started	Feb 08 10:07:03 AM UTC 25
Finished	Feb 08 10:08:46 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157007830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.3157007830
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1758892522
Short name	T368
Test name
Test status
Simulation time	3129364547 ps
CPU time	7.65 seconds
Started	Feb 08 10:06:56 AM UTC 25
Finished	Feb 08 10:07:05 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758892522 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.1758892522
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.166450791
Short name	T46
Test name
Test status
Simulation time	5818492329 ps
CPU time	5.13 seconds
Started	Feb 08 10:07:03 AM UTC 25
Finished	Feb 08 10:07:09 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166450791 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.166450791
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.822832151
Short name	T484
Test name
Test status
Simulation time	2625250061 ps
CPU time	5.59 seconds
Started	Feb 08 10:06:56 AM UTC 25
Finished	Feb 08 10:07:03 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822832151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.822832151
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2534673429
Short name	T481
Test name
Test status
Simulation time	2479158924 ps
CPU time	4.35 seconds
Started	Feb 08 10:06:55 AM UTC 25
Finished	Feb 08 10:07:01 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534673429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.2534673429
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.148034507
Short name	T482
Test name
Test status
Simulation time	2158948828 ps
CPU time	3.91 seconds
Started	Feb 08 10:06:56 AM UTC 25
Finished	Feb 08 10:07:01 AM UTC 25
Peak memory	210052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148034507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.148034507
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1766471768
Short name	T307
Test name
Test status
Simulation time	2508388296 ps
CPU time	11.9 seconds
Started	Feb 08 10:06:56 AM UTC 25
Finished	Feb 08 10:07:09 AM UTC 25
Peak memory	209860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766471768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.1766471768
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2393031786
Short name	T483
Test name
Test status
Simulation time	2121301069 ps
CPU time	6.16 seconds
Started	Feb 08 10:06:55 AM UTC 25
Finished	Feb 08 10:07:03 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393031786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.2393031786
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1119563628
Short name	T126
Test name
Test status
Simulation time	13625962434 ps
CPU time	53 seconds
Started	Feb 08 10:07:04 AM UTC 25
Finished	Feb 08 10:07:59 AM UTC 25
Peak memory	210056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119563628 -assert nopostproc +UVM_TESTNAME=sysrst _ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.1119563628
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2620297909
Short name	T162
Test name
Test status
Simulation time	5908866057 ps
CPU time	18.06 seconds
Started	Feb 08 10:06:59 AM UTC 25
Finished	Feb 08 10:07:19 AM UTC 25
Peak memory	210064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620297909 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.2620297909
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3010012028
Short name	T780
Test name
Test status
Simulation time	67448483940 ps
CPU time	55.92 seconds
Started	Feb 08 10:17:38 AM UTC 25
Finished	Feb 08 10:18:36 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010012028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.3010012028
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.249115518
Short name	T783
Test name
Test status
Simulation time	65859743956 ps
CPU time	64.64 seconds
Started	Feb 08 10:17:38 AM UTC 25
Finished	Feb 08 10:18:45 AM UTC 25
Peak memory	209892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249115518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.249115518
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1892736564
Short name	T429
Test name
Test status
Simulation time	61620037831 ps
CPU time	108.23 seconds
Started	Feb 08 10:17:42 AM UTC 25
Finished	Feb 08 10:19:32 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892736564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.1892736564
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3991176906
Short name	T440
Test name
Test status
Simulation time	55682756133 ps
CPU time	169.66 seconds
Started	Feb 08 10:17:43 AM UTC 25
Finished	Feb 08 10:20:35 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991176906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.3991176906
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2380482967
Short name	T790
Test name
Test status
Simulation time	38146776773 ps
CPU time	114.18 seconds
Started	Feb 08 10:17:46 AM UTC 25
Finished	Feb 08 10:19:42 AM UTC 25
Peak memory	209884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380482967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.2380482967
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.978067839
Short name	T446
Test name
Test status
Simulation time	44378042658 ps
CPU time	34.9 seconds
Started	Feb 08 10:17:48 AM UTC 25
Finished	Feb 08 10:18:24 AM UTC 25
Peak memory	209892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978067839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.978067839
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2614965513
Short name	T794
Test name
Test status
Simulation time	98029729990 ps
CPU time	154.82 seconds
Started	Feb 08 10:17:48 AM UTC 25
Finished	Feb 08 10:20:25 AM UTC 25
Peak memory	209988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614965513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.2614965513
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.829657751
Short name	T782
Test name
Test status
Simulation time	90442149468 ps
CPU time	49.32 seconds
Started	Feb 08 10:17:49 AM UTC 25
Finished	Feb 08 10:18:40 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829657751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ= sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.829657751
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.48313100
Short name	T777
Test name
Test status
Simulation time	36720037847 ps
CPU time	23.67 seconds
Started	Feb 08 10:17:55 AM UTC 25
Finished	Feb 08 10:18:20 AM UTC 25
Peak memory	209904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48313100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s ysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sysrst_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.48313100
Directory	/workspaces/repo/scratch/os_regression/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest