| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.27 | 99.03 | 97.85 | 100.00 | 92.31 | 99.26 | 98.84 | 86.61 |
| T33 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3995127925 | Oct 14 11:41:00 PM UTC 24 | Oct 14 11:41:12 PM UTC 24 | 2041933274 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3575849828 | Oct 14 11:41:07 PM UTC 24 | Oct 14 11:41:14 PM UTC 24 | 2025946602 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2793352959 | Oct 14 11:41:12 PM UTC 24 | Oct 14 11:41:19 PM UTC 24 | 4028256195 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3140075486 | Oct 14 11:41:12 PM UTC 24 | Oct 14 11:41:23 PM UTC 24 | 2015982948 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2212878052 | Oct 14 11:41:20 PM UTC 24 | Oct 14 11:41:24 PM UTC 24 | 2196571517 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3285728783 | Oct 14 11:41:14 PM UTC 24 | Oct 14 11:41:24 PM UTC 24 | 2880931267 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1918648987 | Oct 14 11:41:24 PM UTC 24 | Oct 14 11:41:26 PM UTC 24 | 2163585747 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2448840312 | Oct 14 11:41:22 PM UTC 24 | Oct 14 11:41:28 PM UTC 24 | 2636223113 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1548605388 | Oct 14 11:41:18 PM UTC 24 | Oct 14 11:41:29 PM UTC 24 | 10110568879 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3501269237 | Oct 14 11:41:25 PM UTC 24 | Oct 14 11:41:38 PM UTC 24 | 2060317069 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3040150704 | Oct 14 11:41:25 PM UTC 24 | Oct 14 11:41:46 PM UTC 24 | 4031242040 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1983032340 | Oct 14 11:41:35 PM UTC 24 | Oct 14 11:41:48 PM UTC 24 | 2038033560 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.578546256 | Oct 14 11:41:39 PM UTC 24 | Oct 14 11:41:48 PM UTC 24 | 2044634180 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2943100328 | Oct 14 11:41:28 PM UTC 24 | Oct 14 11:41:48 PM UTC 24 | 2920015778 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1569140929 | Oct 14 11:41:27 PM UTC 24 | Oct 14 11:41:50 PM UTC 24 | 35548261032 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.349574754 | Oct 14 11:41:49 PM UTC 24 | Oct 14 11:41:56 PM UTC 24 | 2059661475 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2251043748 | Oct 14 11:41:49 PM UTC 24 | Oct 14 11:41:56 PM UTC 24 | 2012933507 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4271200902 | Oct 14 11:41:30 PM UTC 24 | Oct 14 11:42:00 PM UTC 24 | 5312368133 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2808614775 | Oct 14 11:41:58 PM UTC 24 | Oct 14 11:42:03 PM UTC 24 | 2044665442 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1060022512 | Oct 14 11:42:00 PM UTC 24 | Oct 14 11:42:04 PM UTC 24 | 2271492361 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.858255254 | Oct 14 11:42:06 PM UTC 24 | Oct 14 11:42:09 PM UTC 24 | 6206604071 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3459181740 | Oct 14 11:41:49 PM UTC 24 | Oct 14 11:42:11 PM UTC 24 | 6013460519 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.225079463 | Oct 14 11:41:56 PM UTC 24 | Oct 14 11:42:14 PM UTC 24 | 2510224224 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.479676388 | Oct 14 11:41:57 PM UTC 24 | Oct 14 11:42:15 PM UTC 24 | 4672813209 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.733398281 | Oct 14 11:41:13 PM UTC 24 | Oct 14 11:42:17 PM UTC 24 | 42237520382 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3943002473 | Oct 14 11:42:04 PM UTC 24 | Oct 14 11:42:17 PM UTC 24 | 2012794568 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1202116431 | Oct 14 11:42:16 PM UTC 24 | Oct 14 11:42:21 PM UTC 24 | 2107249260 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1699189278 | Oct 14 11:42:17 PM UTC 24 | Oct 14 11:42:22 PM UTC 24 | 2594977909 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3503149454 | Oct 14 11:41:22 PM UTC 24 | Oct 14 11:42:22 PM UTC 24 | 42466136498 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.256330110 | Oct 14 11:42:11 PM UTC 24 | Oct 14 11:42:24 PM UTC 24 | 2036248372 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2502596197 | Oct 14 11:42:21 PM UTC 24 | Oct 14 11:42:25 PM UTC 24 | 2025036615 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3172513433 | Oct 14 11:42:22 PM UTC 24 | Oct 14 11:42:27 PM UTC 24 | 2113173609 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.296687690 | Oct 14 11:42:15 PM UTC 24 | Oct 14 11:42:27 PM UTC 24 | 7270504645 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1549607809 | Oct 14 11:42:22 PM UTC 24 | Oct 14 11:42:29 PM UTC 24 | 4038069088 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3840933403 | Oct 14 11:42:12 PM UTC 24 | Oct 14 11:42:30 PM UTC 24 | 3078960573 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3285815172 | Oct 14 11:41:48 PM UTC 24 | Oct 14 11:42:31 PM UTC 24 | 42508046353 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3071942546 | Oct 14 11:42:18 PM UTC 24 | Oct 14 11:42:34 PM UTC 24 | 45370215433 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.152111552 | Oct 14 11:42:30 PM UTC 24 | Oct 14 11:42:34 PM UTC 24 | 3577807630 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2529080317 | Oct 14 11:42:31 PM UTC 24 | Oct 14 11:42:36 PM UTC 24 | 2040919903 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1231258347 | Oct 14 11:42:28 PM UTC 24 | Oct 14 11:42:40 PM UTC 24 | 2036253257 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.4134591793 | Oct 14 11:42:35 PM UTC 24 | Oct 14 11:42:43 PM UTC 24 | 2047429104 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2056325204 | Oct 14 11:42:32 PM UTC 24 | Oct 14 11:42:44 PM UTC 24 | 2030903306 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2187096508 | Oct 14 11:42:42 PM UTC 24 | Oct 14 11:42:45 PM UTC 24 | 2032350683 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1625105181 | Oct 14 11:42:35 PM UTC 24 | Oct 14 11:42:46 PM UTC 24 | 5189394106 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3236206292 | Oct 14 11:42:27 PM UTC 24 | Oct 14 11:42:46 PM UTC 24 | 2924269567 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3163097975 | Oct 14 11:42:46 PM UTC 24 | Oct 14 11:42:49 PM UTC 24 | 2477661772 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1192432716 | Oct 14 11:42:44 PM UTC 24 | Oct 14 11:42:50 PM UTC 24 | 2036922209 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1090337380 | Oct 14 11:42:36 PM UTC 24 | Oct 14 11:42:50 PM UTC 24 | 2154297854 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3127170844 | Oct 14 11:42:47 PM UTC 24 | Oct 14 11:42:54 PM UTC 24 | 2025002958 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1315852810 | Oct 14 11:42:28 PM UTC 24 | Oct 14 11:42:54 PM UTC 24 | 9723784403 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2199726459 | Oct 14 11:42:31 PM UTC 24 | Oct 14 11:42:55 PM UTC 24 | 22546874667 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3021504350 | Oct 14 11:42:46 PM UTC 24 | Oct 14 11:42:56 PM UTC 24 | 2057801316 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4283286598 | Oct 14 11:42:50 PM UTC 24 | Oct 14 11:42:59 PM UTC 24 | 2049217966 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2630753860 | Oct 14 11:42:45 PM UTC 24 | Oct 14 11:42:59 PM UTC 24 | 8429322438 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2337934548 | Oct 14 11:42:56 PM UTC 24 | Oct 14 11:43:00 PM UTC 24 | 2033458129 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3473226272 | Oct 14 11:42:51 PM UTC 24 | Oct 14 11:43:01 PM UTC 24 | 2070366820 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.336623388 | Oct 14 11:42:54 PM UTC 24 | Oct 14 11:43:02 PM UTC 24 | 2084569324 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3234385329 | Oct 14 11:43:00 PM UTC 24 | Oct 14 11:43:03 PM UTC 24 | 2095669416 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3263871907 | Oct 14 11:42:57 PM UTC 24 | Oct 14 11:43:04 PM UTC 24 | 2031932268 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.832738442 | Oct 14 11:43:02 PM UTC 24 | Oct 14 11:43:05 PM UTC 24 | 2098524679 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2447796143 | Oct 14 11:43:00 PM UTC 24 | Oct 14 11:43:07 PM UTC 24 | 2418157568 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2492962069 | Oct 14 11:42:50 PM UTC 24 | Oct 14 11:43:07 PM UTC 24 | 5377822281 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2780861011 | Oct 14 11:43:04 PM UTC 24 | Oct 14 11:43:10 PM UTC 24 | 2194257767 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1200012862 | Oct 14 11:42:57 PM UTC 24 | Oct 14 11:43:10 PM UTC 24 | 10687127087 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2458900307 | Oct 14 11:43:04 PM UTC 24 | Oct 14 11:43:11 PM UTC 24 | 2076511940 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1130856145 | Oct 14 11:43:09 PM UTC 24 | Oct 14 11:43:13 PM UTC 24 | 2142706898 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.563685430 | Oct 14 11:43:03 PM UTC 24 | Oct 14 11:43:13 PM UTC 24 | 2038860799 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1335743490 | Oct 14 11:43:03 PM UTC 24 | Oct 14 11:43:13 PM UTC 24 | 5118725964 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.657063840 | Oct 14 11:43:11 PM UTC 24 | Oct 14 11:43:15 PM UTC 24 | 2210796530 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3975339717 | Oct 14 11:43:09 PM UTC 24 | Oct 14 11:43:16 PM UTC 24 | 2018091417 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1025560208 | Oct 14 11:41:04 PM UTC 24 | Oct 14 11:43:17 PM UTC 24 | 42431391579 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3908446484 | Oct 14 11:43:14 PM UTC 24 | Oct 14 11:43:19 PM UTC 24 | 2046882966 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.593643725 | Oct 14 11:43:11 PM UTC 24 | Oct 14 11:43:20 PM UTC 24 | 2034667932 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2335164646 | Oct 14 11:43:14 PM UTC 24 | Oct 14 11:43:21 PM UTC 24 | 2064896322 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3834151602 | Oct 14 11:43:17 PM UTC 24 | Oct 14 11:43:22 PM UTC 24 | 2606148880 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2341057555 | Oct 14 11:42:03 PM UTC 24 | Oct 14 11:43:23 PM UTC 24 | 42572393650 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4124000339 | Oct 14 11:43:10 PM UTC 24 | Oct 14 11:43:26 PM UTC 24 | 4997383214 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1287354091 | Oct 14 11:43:20 PM UTC 24 | Oct 14 11:43:28 PM UTC 24 | 2013526491 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1453726007 | Oct 14 11:43:16 PM UTC 24 | Oct 14 11:43:29 PM UTC 24 | 2041026847 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3502547829 | Oct 14 11:43:06 PM UTC 24 | Oct 14 11:43:30 PM UTC 24 | 22488047761 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4075041345 | Oct 14 11:43:23 PM UTC 24 | Oct 14 11:43:30 PM UTC 24 | 2051125838 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.526124430 | Oct 14 11:43:24 PM UTC 24 | Oct 14 11:43:31 PM UTC 24 | 2180369604 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3576826245 | Oct 14 11:43:21 PM UTC 24 | Oct 14 11:43:34 PM UTC 24 | 2035636766 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2267701390 | Oct 14 11:43:31 PM UTC 24 | Oct 14 11:43:35 PM UTC 24 | 2086929636 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2236941909 | Oct 14 11:43:31 PM UTC 24 | Oct 14 11:43:36 PM UTC 24 | 2060980801 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.4255422931 | Oct 14 11:43:19 PM UTC 24 | Oct 14 11:43:36 PM UTC 24 | 46432406782 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1353445871 | Oct 14 11:43:29 PM UTC 24 | Oct 14 11:43:36 PM UTC 24 | 2014498924 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3216148823 | Oct 14 11:44:24 PM UTC 24 | Oct 14 11:44:30 PM UTC 24 | 2022133008 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1652205300 | Oct 14 11:44:23 PM UTC 24 | Oct 14 11:44:32 PM UTC 24 | 2014948304 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1794936173 | Oct 14 11:43:32 PM UTC 24 | Oct 14 11:43:38 PM UTC 24 | 2095514620 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.641569355 | Oct 14 11:42:47 PM UTC 24 | Oct 14 11:43:41 PM UTC 24 | 22187742150 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.98064534 | Oct 14 11:43:37 PM UTC 24 | Oct 14 11:43:41 PM UTC 24 | 2370090827 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2840606243 | Oct 14 11:43:39 PM UTC 24 | Oct 14 11:43:42 PM UTC 24 | 2246670775 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.756745539 | Oct 14 11:43:36 PM UTC 24 | Oct 14 11:43:43 PM UTC 24 | 2018702292 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2930617610 | Oct 14 11:43:36 PM UTC 24 | Oct 14 11:43:43 PM UTC 24 | 2046050271 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.4131698186 | Oct 14 11:44:26 PM UTC 24 | Oct 14 11:44:32 PM UTC 24 | 2010941525 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2712210971 | Oct 14 11:43:37 PM UTC 24 | Oct 14 11:43:46 PM UTC 24 | 4873682971 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1950292391 | Oct 14 11:43:42 PM UTC 24 | Oct 14 11:43:46 PM UTC 24 | 2030360845 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4191763343 | Oct 14 11:41:51 PM UTC 24 | Oct 14 11:43:47 PM UTC 24 | 39165344903 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.931686032 | Oct 14 11:43:14 PM UTC 24 | Oct 14 11:43:49 PM UTC 24 | 7663889034 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2603617739 | Oct 14 11:43:48 PM UTC 24 | Oct 14 11:43:52 PM UTC 24 | 2039305749 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1972484326 | Oct 14 11:43:44 PM UTC 24 | Oct 14 11:43:53 PM UTC 24 | 10583142052 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1196404308 | Oct 14 11:43:43 PM UTC 24 | Oct 14 11:43:55 PM UTC 24 | 2060985788 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2119506561 | Oct 14 11:43:44 PM UTC 24 | Oct 14 11:43:55 PM UTC 24 | 2038393628 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.4014395526 | Oct 14 11:43:01 PM UTC 24 | Oct 14 11:43:56 PM UTC 24 | 42616214321 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3876144916 | Oct 14 11:43:54 PM UTC 24 | Oct 14 11:43:59 PM UTC 24 | 2106852812 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4041331824 | Oct 14 11:43:46 PM UTC 24 | Oct 14 11:43:59 PM UTC 24 | 2047023007 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.838156816 | Oct 14 11:43:21 PM UTC 24 | Oct 14 11:44:00 PM UTC 24 | 10042717423 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2442832538 | Oct 14 11:43:50 PM UTC 24 | Oct 14 11:44:01 PM UTC 24 | 2055863504 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.357384905 | Oct 14 11:43:31 PM UTC 24 | Oct 14 11:44:02 PM UTC 24 | 4903202653 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1273355337 | Oct 14 11:43:56 PM UTC 24 | Oct 14 11:44:03 PM UTC 24 | 2252534469 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1939895810 | Oct 14 11:43:59 PM UTC 24 | Oct 14 11:44:03 PM UTC 24 | 2107542494 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1594215865 | Oct 14 11:43:57 PM UTC 24 | Oct 14 11:44:05 PM UTC 24 | 2012778149 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3930929015 | Oct 14 11:43:53 PM UTC 24 | Oct 14 11:44:05 PM UTC 24 | 4396599570 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3061008681 | Oct 14 11:44:03 PM UTC 24 | Oct 14 11:44:06 PM UTC 24 | 2029815983 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2754525953 | Oct 14 11:44:05 PM UTC 24 | Oct 14 11:44:10 PM UTC 24 | 10061690048 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3205383065 | Oct 14 11:44:02 PM UTC 24 | Oct 14 11:44:11 PM UTC 24 | 2231041537 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3278383016 | Oct 14 11:43:42 PM UTC 24 | Oct 14 11:44:11 PM UTC 24 | 22270700710 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3447555285 | Oct 14 11:43:12 PM UTC 24 | Oct 14 11:44:12 PM UTC 24 | 22249975789 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.958792403 | Oct 14 11:44:07 PM UTC 24 | Oct 14 11:44:14 PM UTC 24 | 2047678291 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3709396014 | Oct 14 11:44:07 PM UTC 24 | Oct 14 11:44:14 PM UTC 24 | 2122830728 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.760433618 | Oct 14 11:44:01 PM UTC 24 | Oct 14 11:44:14 PM UTC 24 | 2069686356 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.564014484 | Oct 14 11:44:04 PM UTC 24 | Oct 14 11:44:16 PM UTC 24 | 2035773933 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3829718482 | Oct 14 11:43:27 PM UTC 24 | Oct 14 11:44:16 PM UTC 24 | 42753693299 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2953129861 | Oct 14 11:44:12 PM UTC 24 | Oct 14 11:44:17 PM UTC 24 | 2053844793 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3397425738 | Oct 14 11:44:14 PM UTC 24 | Oct 14 11:44:19 PM UTC 24 | 2034231368 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.753631591 | Oct 14 11:44:17 PM UTC 24 | Oct 14 11:44:20 PM UTC 24 | 2047180165 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2688535946 | Oct 14 11:44:16 PM UTC 24 | Oct 14 11:44:20 PM UTC 24 | 2028454243 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1335564947 | Oct 14 11:44:13 PM UTC 24 | Oct 14 11:44:20 PM UTC 24 | 2107865292 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.858891412 | Oct 14 11:44:18 PM UTC 24 | Oct 14 11:44:21 PM UTC 24 | 2056689981 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3299529653 | Oct 14 11:44:18 PM UTC 24 | Oct 14 11:44:21 PM UTC 24 | 2050974455 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2118830044 | Oct 14 11:42:56 PM UTC 24 | Oct 14 11:44:21 PM UTC 24 | 42587538907 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.200358143 | Oct 14 11:44:13 PM UTC 24 | Oct 14 11:44:22 PM UTC 24 | 4727187881 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3799158249 | Oct 14 11:44:12 PM UTC 24 | Oct 14 11:44:23 PM UTC 24 | 2015284469 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2902989738 | Oct 14 11:44:20 PM UTC 24 | Oct 14 11:44:23 PM UTC 24 | 2091350291 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.309859913 | Oct 14 11:44:20 PM UTC 24 | Oct 14 11:44:23 PM UTC 24 | 2076563263 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3361502316 | Oct 14 11:44:03 PM UTC 24 | Oct 14 11:44:23 PM UTC 24 | 22626980004 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1101364696 | Oct 14 11:44:20 PM UTC 24 | Oct 14 11:44:25 PM UTC 24 | 2032649056 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.285884689 | Oct 14 11:44:14 PM UTC 24 | Oct 14 11:44:25 PM UTC 24 | 2015106868 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3123266693 | Oct 14 11:44:18 PM UTC 24 | Oct 14 11:44:25 PM UTC 24 | 2020175674 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1975072022 | Oct 14 11:43:35 PM UTC 24 | Oct 14 11:44:25 PM UTC 24 | 42954434559 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1431459211 | Oct 14 11:44:24 PM UTC 24 | Oct 14 11:44:27 PM UTC 24 | 2061646148 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1594654951 | Oct 14 11:44:22 PM UTC 24 | Oct 14 11:44:27 PM UTC 24 | 2025003380 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3024563051 | Oct 14 11:44:01 PM UTC 24 | Oct 14 11:44:27 PM UTC 24 | 5304094030 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1207259663 | Oct 14 11:44:23 PM UTC 24 | Oct 14 11:44:27 PM UTC 24 | 2035032902 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1336977621 | Oct 14 11:44:22 PM UTC 24 | Oct 14 11:44:32 PM UTC 24 | 2009768311 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3595666360 | Oct 14 11:44:24 PM UTC 24 | Oct 14 11:44:27 PM UTC 24 | 2043444370 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.894016658 | Oct 14 11:44:23 PM UTC 24 | Oct 14 11:44:28 PM UTC 24 | 2015487378 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.4061141327 | Oct 14 11:44:24 PM UTC 24 | Oct 14 11:44:28 PM UTC 24 | 2042565284 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2398385691 | Oct 14 11:44:26 PM UTC 24 | Oct 14 11:44:31 PM UTC 24 | 2014805565 ps | ||
| T901 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3944053102 | Oct 14 11:44:29 PM UTC 24 | Oct 14 11:44:35 PM UTC 24 | 2014878739 ps | ||
| T902 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.718639706 | Oct 14 11:44:29 PM UTC 24 | Oct 14 11:44:35 PM UTC 24 | 2022638658 ps | ||
| T903 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.4152297028 | Oct 14 11:44:29 PM UTC 24 | Oct 14 11:44:36 PM UTC 24 | 2013835367 ps | ||
| T904 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1632016443 | Oct 14 11:44:27 PM UTC 24 | Oct 14 11:44:37 PM UTC 24 | 2018208452 ps | ||
| T905 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2904881678 | Oct 14 11:44:29 PM UTC 24 | Oct 14 11:44:37 PM UTC 24 | 2013884170 ps | ||
| T906 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2519080082 | Oct 14 11:44:11 PM UTC 24 | Oct 14 11:44:37 PM UTC 24 | 22338394102 ps | ||
| T907 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.233293610 | Oct 14 11:44:26 PM UTC 24 | Oct 14 11:44:37 PM UTC 24 | 2015613870 ps | ||
| T908 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1628504406 | Oct 14 11:44:27 PM UTC 24 | Oct 14 11:44:37 PM UTC 24 | 2015410515 ps | ||
| T909 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2868194482 | Oct 14 11:44:26 PM UTC 24 | Oct 14 11:44:38 PM UTC 24 | 2008012983 ps | ||
| T910 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.433612044 | Oct 14 11:44:29 PM UTC 24 | Oct 14 11:44:39 PM UTC 24 | 2013168456 ps | ||
| T911 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3222689894 | Oct 14 11:43:56 PM UTC 24 | Oct 14 11:44:47 PM UTC 24 | 42522278539 ps | ||
| T912 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1076069097 | Oct 14 11:43:47 PM UTC 24 | Oct 14 11:44:56 PM UTC 24 | 22183436950 ps | ||
| T913 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3771949685 | Oct 14 11:42:41 PM UTC 24 | Oct 14 11:45:19 PM UTC 24 | 42415756881 ps | ||
| T914 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1931657836 | Oct 14 11:42:25 PM UTC 24 | Oct 14 11:45:20 PM UTC 24 | 37838654143 ps | ||
| T915 | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2835533234 | Oct 14 11:42:12 PM UTC 24 | Oct 14 11:46:45 PM UTC 24 | 40165424010 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2559007234 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7614784845 ps |
| CPU time | 5.96 seconds |
| Started | Oct 14 10:12:23 PM UTC 24 |
| Finished | Oct 14 10:12:30 PM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2559007234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2559007234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.1221151344 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 36343184158 ps |
| CPU time | 35.04 seconds |
| Started | Oct 14 10:12:21 PM UTC 24 |
| Finished | Oct 14 10:12:57 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221151344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1221151344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.842770191 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2483158280 ps |
| CPU time | 10.79 seconds |
| Started | Oct 14 10:12:08 PM UTC 24 |
| Finished | Oct 14 10:12:20 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842770191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.842770191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.899186097 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 42730424706 ps |
| CPU time | 24.99 seconds |
| Started | Oct 14 10:12:33 PM UTC 24 |
| Finished | Oct 14 10:12:59 PM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899186097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.899186097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1427560171 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2270225927271 ps |
| CPU time | 28.05 seconds |
| Started | Oct 14 10:12:32 PM UTC 24 |
| Finished | Oct 14 10:13:01 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427560171 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.1427560171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1307214762 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 34416452853 ps |
| CPU time | 88.82 seconds |
| Started | Oct 14 10:12:35 PM UTC 24 |
| Finished | Oct 14 10:14:06 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307214762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1307214762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3503149454 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 42466136498 ps |
| CPU time | 58.78 seconds |
| Started | Oct 14 11:41:22 PM UTC 24 |
| Finished | Oct 14 11:42:22 PM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503149454 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.3503149454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2371969372 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 11879315308 ps |
| CPU time | 10.14 seconds |
| Started | Oct 14 10:12:36 PM UTC 24 |
| Finished | Oct 14 10:12:47 PM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371969372 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.2371969372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2143253305 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 119380468685 ps |
| CPU time | 120.45 seconds |
| Started | Oct 14 10:14:27 PM UTC 24 |
| Finished | Oct 14 10:16:31 PM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143253305 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.2143253305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.903978723 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 290563921872 ps |
| CPU time | 697.58 seconds |
| Started | Oct 14 10:14:08 PM UTC 24 |
| Finished | Oct 14 10:25:53 PM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903978723 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.903978723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.51694209 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 84023230938 ps |
| CPU time | 50.72 seconds |
| Started | Oct 14 10:15:53 PM UTC 24 |
| Finished | Oct 14 10:16:46 PM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51694209 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.51694209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.456706244 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3472868895 ps |
| CPU time | 3.62 seconds |
| Started | Oct 14 10:12:45 PM UTC 24 |
| Finished | Oct 14 10:12:50 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456706244 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.456706244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3621452415 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8838007393 ps |
| CPU time | 9.89 seconds |
| Started | Oct 14 10:17:09 PM UTC 24 |
| Finished | Oct 14 10:17:21 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3621452415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3621452415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.1422526474 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 139655857877 ps |
| CPU time | 229.99 seconds |
| Started | Oct 14 10:14:57 PM UTC 24 |
| Finished | Oct 14 10:18:50 PM UTC 24 |
| Peak memory | 209724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422526474 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.1422526474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3964804115 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10589891379 ps |
| CPU time | 44.4 seconds |
| Started | Oct 14 10:12:25 PM UTC 24 |
| Finished | Oct 14 10:13:11 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964804115 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.3964804115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.583564652 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 148699762107 ps |
| CPU time | 261.18 seconds |
| Started | Oct 14 10:13:39 PM UTC 24 |
| Finished | Oct 14 10:18:03 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583564652 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.583564652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3715719340 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 42019146720 ps |
| CPU time | 63.49 seconds |
| Started | Oct 14 10:12:37 PM UTC 24 |
| Finished | Oct 14 10:13:43 PM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715719340 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3715719340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4196742745 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 7037666275 ps |
| CPU time | 11.23 seconds |
| Started | Oct 14 10:18:10 PM UTC 24 |
| Finished | Oct 14 10:18:22 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196742745 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.4196742745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.202928468 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 118255779013 ps |
| CPU time | 28.1 seconds |
| Started | Oct 14 10:20:19 PM UTC 24 |
| Finished | Oct 14 10:20:49 PM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202928468 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.202928468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1490768042 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 130856476342 ps |
| CPU time | 393.8 seconds |
| Started | Oct 14 10:17:08 PM UTC 24 |
| Finished | Oct 14 10:23:48 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490768042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.1490768042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3995127925 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2041933274 ps |
| CPU time | 10.94 seconds |
| Started | Oct 14 11:41:00 PM UTC 24 |
| Finished | Oct 14 11:41:12 PM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995127925 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.3995127925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.349574754 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2059661475 ps |
| CPU time | 5.67 seconds |
| Started | Oct 14 11:41:49 PM UTC 24 |
| Finished | Oct 14 11:41:56 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349574754 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.349574754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1735238661 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3308766523 ps |
| CPU time | 3.65 seconds |
| Started | Oct 14 10:14:17 PM UTC 24 |
| Finished | Oct 14 10:14:22 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735238661 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.1735238661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.1527154259 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 15105754589 ps |
| CPU time | 53.11 seconds |
| Started | Oct 14 10:21:12 PM UTC 24 |
| Finished | Oct 14 10:22:06 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527154259 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.1527154259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1135120743 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 72215975064 ps |
| CPU time | 216.25 seconds |
| Started | Oct 14 10:12:21 PM UTC 24 |
| Finished | Oct 14 10:16:00 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135120743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.1135120743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4035605069 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3040538288 ps |
| CPU time | 4.5 seconds |
| Started | Oct 14 10:13:54 PM UTC 24 |
| Finished | Oct 14 10:13:59 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035605069 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.4035605069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3706186195 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 89423328002 ps |
| CPU time | 237.68 seconds |
| Started | Oct 14 10:19:51 PM UTC 24 |
| Finished | Oct 14 10:23:52 PM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706186195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.3706186195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1074400184 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3111979543 ps |
| CPU time | 8.33 seconds |
| Started | Oct 14 10:14:38 PM UTC 24 |
| Finished | Oct 14 10:14:48 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074400184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1074400184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3667750333 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2555904693 ps |
| CPU time | 2.96 seconds |
| Started | Oct 14 10:14:23 PM UTC 24 |
| Finished | Oct 14 10:14:27 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667750333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3667750333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1222775905 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 66952119021 ps |
| CPU time | 269.35 seconds |
| Started | Oct 14 10:13:04 PM UTC 24 |
| Finished | Oct 14 10:17:37 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222775905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.1222775905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1502255052 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 157444181574 ps |
| CPU time | 141.9 seconds |
| Started | Oct 14 10:12:18 PM UTC 24 |
| Finished | Oct 14 10:14:43 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502255052 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.1502255052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4011153431 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 161292989282 ps |
| CPU time | 501.71 seconds |
| Started | Oct 14 10:13:19 PM UTC 24 |
| Finished | Oct 14 10:21:46 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011153431 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.4011153431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.585974051 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5879706814 ps |
| CPU time | 6.25 seconds |
| Started | Oct 14 10:13:04 PM UTC 24 |
| Finished | Oct 14 10:13:11 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585974051 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.585974051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.225176810 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2010153322 ps |
| CPU time | 7.81 seconds |
| Started | Oct 14 10:12:26 PM UTC 24 |
| Finished | Oct 14 10:12:35 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225176810 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.225176810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1044928680 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2510586543 ps |
| CPU time | 16.22 seconds |
| Started | Oct 14 10:12:17 PM UTC 24 |
| Finished | Oct 14 10:12:34 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044928680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1044928680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1618692249 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 115370546064 ps |
| CPU time | 172.46 seconds |
| Started | Oct 14 10:20:03 PM UTC 24 |
| Finished | Oct 14 10:22:58 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618692249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.1618692249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2344515100 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 18826954852 ps |
| CPU time | 74.17 seconds |
| Started | Oct 14 10:21:43 PM UTC 24 |
| Finished | Oct 14 10:22:59 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344515100 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.2344515100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1831377135 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 58217569181 ps |
| CPU time | 106.1 seconds |
| Started | Oct 14 10:20:49 PM UTC 24 |
| Finished | Oct 14 10:22:37 PM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831377135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.1831377135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.310071825 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 77364042703 ps |
| CPU time | 299.85 seconds |
| Started | Oct 14 10:13:28 PM UTC 24 |
| Finished | Oct 14 10:18:32 PM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310071825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.310071825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3285728783 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2880931267 ps |
| CPU time | 8.45 seconds |
| Started | Oct 14 11:41:14 PM UTC 24 |
| Finished | Oct 14 11:41:24 PM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285728783 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.3285728783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1784617522 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 68022118577 ps |
| CPU time | 64.12 seconds |
| Started | Oct 14 10:19:18 PM UTC 24 |
| Finished | Oct 14 10:20:24 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784617522 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.1784617522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.892693910 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3419365342 ps |
| CPU time | 21.54 seconds |
| Started | Oct 14 10:12:31 PM UTC 24 |
| Finished | Oct 14 10:12:53 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892693910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.892693910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3555246331 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2538621480 ps |
| CPU time | 3.08 seconds |
| Started | Oct 14 10:14:36 PM UTC 24 |
| Finished | Oct 14 10:14:40 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555246331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3555246331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.320411179 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 119179673200 ps |
| CPU time | 211.98 seconds |
| Started | Oct 14 10:23:05 PM UTC 24 |
| Finished | Oct 14 10:26:40 PM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320411179 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.320411179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2857677027 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 4814062017 ps |
| CPU time | 9.03 seconds |
| Started | Oct 14 10:18:32 PM UTC 24 |
| Finished | Oct 14 10:18:42 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857677027 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.2857677027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1699189278 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2594977909 ps |
| CPU time | 3.75 seconds |
| Started | Oct 14 11:42:17 PM UTC 24 |
| Finished | Oct 14 11:42:22 PM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699189278 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.1699189278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3890620846 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 68012804436 ps |
| CPU time | 199.42 seconds |
| Started | Oct 14 10:17:07 PM UTC 24 |
| Finished | Oct 14 10:20:30 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890620846 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.3890620846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.320850822 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 104323078791 ps |
| CPU time | 87.7 seconds |
| Started | Oct 14 10:24:15 PM UTC 24 |
| Finished | Oct 14 10:25:45 PM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320850822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.320850822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1474228812 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 780661190323 ps |
| CPU time | 97.03 seconds |
| Started | Oct 14 10:13:55 PM UTC 24 |
| Finished | Oct 14 10:15:34 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474228812 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.1474228812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.493746009 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 110062868256 ps |
| CPU time | 211.12 seconds |
| Started | Oct 14 10:12:44 PM UTC 24 |
| Finished | Oct 14 10:16:18 PM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493746009 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.493746009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3285815172 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 42508046353 ps |
| CPU time | 41.61 seconds |
| Started | Oct 14 11:41:48 PM UTC 24 |
| Finished | Oct 14 11:42:31 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285815172 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.3285815172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.73207015 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2534489485 ps |
| CPU time | 2.27 seconds |
| Started | Oct 14 10:12:40 PM UTC 24 |
| Finished | Oct 14 10:12:43 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73207015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.73207015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1920219921 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 86345917696 ps |
| CPU time | 240.51 seconds |
| Started | Oct 14 10:17:28 PM UTC 24 |
| Finished | Oct 14 10:21:32 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920219921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.1920219921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2934535082 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 66270099013 ps |
| CPU time | 69.12 seconds |
| Started | Oct 14 10:18:15 PM UTC 24 |
| Finished | Oct 14 10:19:26 PM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934535082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.2934535082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.1895912324 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 119750086421 ps |
| CPU time | 181.87 seconds |
| Started | Oct 14 10:22:54 PM UTC 24 |
| Finished | Oct 14 10:25:58 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895912324 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.1895912324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3428439877 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 141860144497 ps |
| CPU time | 530.71 seconds |
| Started | Oct 14 10:24:41 PM UTC 24 |
| Finished | Oct 14 10:33:38 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428439877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.3428439877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2534349858 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8434554874 ps |
| CPU time | 14.19 seconds |
| Started | Oct 14 10:12:44 PM UTC 24 |
| Finished | Oct 14 10:13:00 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534349858 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.2534349858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3003896791 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3520198877 ps |
| CPU time | 4.23 seconds |
| Started | Oct 14 10:23:05 PM UTC 24 |
| Finished | Oct 14 10:23:10 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003896791 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.3003896791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1141757929 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 50257918793 ps |
| CPU time | 182.79 seconds |
| Started | Oct 14 10:23:58 PM UTC 24 |
| Finished | Oct 14 10:27:03 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141757929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.1141757929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1908597495 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2420015680 ps |
| CPU time | 13.7 seconds |
| Started | Oct 14 10:12:09 PM UTC 24 |
| Finished | Oct 14 10:12:24 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908597495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1908597495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1975072022 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 42954434559 ps |
| CPU time | 48.15 seconds |
| Started | Oct 14 11:43:35 PM UTC 24 |
| Finished | Oct 14 11:44:25 PM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975072022 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.1975072022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.963461190 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3542762541 ps |
| CPU time | 8.88 seconds |
| Started | Oct 14 10:12:18 PM UTC 24 |
| Finished | Oct 14 10:12:28 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963461190 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.963461190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3255213688 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 513605748306 ps |
| CPU time | 43.37 seconds |
| Started | Oct 14 10:15:57 PM UTC 24 |
| Finished | Oct 14 10:16:43 PM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3255213688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3255213688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1966580016 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 152781745738 ps |
| CPU time | 455.21 seconds |
| Started | Oct 14 10:17:58 PM UTC 24 |
| Finished | Oct 14 10:25:39 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966580016 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.1966580016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3232010227 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 47367728102 ps |
| CPU time | 181.85 seconds |
| Started | Oct 14 10:18:33 PM UTC 24 |
| Finished | Oct 14 10:21:38 PM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232010227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.3232010227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.421199457 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 61680384120 ps |
| CPU time | 231.25 seconds |
| Started | Oct 14 10:18:53 PM UTC 24 |
| Finished | Oct 14 10:22:47 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421199457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.421199457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2813045940 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 54884474610 ps |
| CPU time | 147.51 seconds |
| Started | Oct 14 10:22:46 PM UTC 24 |
| Finished | Oct 14 10:25:16 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813045940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.2813045940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2729548379 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 71483954211 ps |
| CPU time | 188.35 seconds |
| Started | Oct 14 10:22:55 PM UTC 24 |
| Finished | Oct 14 10:26:06 PM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729548379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.2729548379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1591718770 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 43947572077 ps |
| CPU time | 130.19 seconds |
| Started | Oct 14 10:25:01 PM UTC 24 |
| Finished | Oct 14 10:27:14 PM UTC 24 |
| Peak memory | 209152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591718770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.1591718770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1785587529 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 79117536218 ps |
| CPU time | 65.2 seconds |
| Started | Oct 14 10:25:02 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 209400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785587529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.1785587529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.4249522773 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4431432050 ps |
| CPU time | 15.22 seconds |
| Started | Oct 14 10:17:07 PM UTC 24 |
| Finished | Oct 14 10:17:24 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249522773 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.4249522773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3667593714 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 14371658152 ps |
| CPU time | 16.08 seconds |
| Started | Oct 14 10:20:23 PM UTC 24 |
| Finished | Oct 14 10:20:41 PM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3667593714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3667593714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.746182414 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3403176617 ps |
| CPU time | 16.25 seconds |
| Started | Oct 14 10:21:27 PM UTC 24 |
| Finished | Oct 14 10:21:44 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746182414 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.746182414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1548605388 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10110568879 ps |
| CPU time | 9.59 seconds |
| Started | Oct 14 11:41:18 PM UTC 24 |
| Finished | Oct 14 11:41:29 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548605388 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.1548605388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2212878052 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2196571517 ps |
| CPU time | 3.39 seconds |
| Started | Oct 14 11:41:20 PM UTC 24 |
| Finished | Oct 14 11:41:24 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2212878052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2212878052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3439333975 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 37936809339 ps |
| CPU time | 108.93 seconds |
| Started | Oct 14 10:19:06 PM UTC 24 |
| Finished | Oct 14 10:20:57 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439333975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.3439333975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3186193318 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 26078108463 ps |
| CPU time | 80.08 seconds |
| Started | Oct 14 10:14:08 PM UTC 24 |
| Finished | Oct 14 10:15:30 PM UTC 24 |
| Peak memory | 209060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186193318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.3186193318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.733398281 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 42237520382 ps |
| CPU time | 61.54 seconds |
| Started | Oct 14 11:41:13 PM UTC 24 |
| Finished | Oct 14 11:42:17 PM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733398281 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.733398281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2793352959 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4028256195 ps |
| CPU time | 5.91 seconds |
| Started | Oct 14 11:41:12 PM UTC 24 |
| Finished | Oct 14 11:41:19 PM UTC 24 |
| Peak memory | 209516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793352959 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.2793352959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3140075486 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2015982948 ps |
| CPU time | 9.91 seconds |
| Started | Oct 14 11:41:12 PM UTC 24 |
| Finished | Oct 14 11:41:23 PM UTC 24 |
| Peak memory | 209392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140075486 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.3140075486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3575849828 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2025946602 ps |
| CPU time | 5.7 seconds |
| Started | Oct 14 11:41:07 PM UTC 24 |
| Finished | Oct 14 11:41:14 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575849828 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.3575849828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1025560208 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 42431391579 ps |
| CPU time | 130.97 seconds |
| Started | Oct 14 11:41:04 PM UTC 24 |
| Finished | Oct 14 11:43:17 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025560208 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.1025560208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2943100328 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2920015778 ps |
| CPU time | 18.81 seconds |
| Started | Oct 14 11:41:28 PM UTC 24 |
| Finished | Oct 14 11:41:48 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943100328 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.2943100328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1569140929 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 35548261032 ps |
| CPU time | 21.33 seconds |
| Started | Oct 14 11:41:27 PM UTC 24 |
| Finished | Oct 14 11:41:50 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569140929 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.1569140929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3040150704 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4031242040 ps |
| CPU time | 19.9 seconds |
| Started | Oct 14 11:41:25 PM UTC 24 |
| Finished | Oct 14 11:41:46 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040150704 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.3040150704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1983032340 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2038033560 ps |
| CPU time | 11.51 seconds |
| Started | Oct 14 11:41:35 PM UTC 24 |
| Finished | Oct 14 11:41:48 PM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1983032340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .sysrst_ctrl_csr_mem_rw_with_rand_reset.1983032340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3501269237 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2060317069 ps |
| CPU time | 11.71 seconds |
| Started | Oct 14 11:41:25 PM UTC 24 |
| Finished | Oct 14 11:41:38 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501269237 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.3501269237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1918648987 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2163585747 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 11:41:24 PM UTC 24 |
| Finished | Oct 14 11:41:26 PM UTC 24 |
| Peak memory | 207980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918648987 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.1918648987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4271200902 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5312368133 ps |
| CPU time | 27.94 seconds |
| Started | Oct 14 11:41:30 PM UTC 24 |
| Finished | Oct 14 11:42:00 PM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271200902 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.4271200902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2448840312 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2636223113 ps |
| CPU time | 5.08 seconds |
| Started | Oct 14 11:41:22 PM UTC 24 |
| Finished | Oct 14 11:41:28 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448840312 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.2448840312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.593643725 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2034667932 ps |
| CPU time | 7.48 seconds |
| Started | Oct 14 11:43:11 PM UTC 24 |
| Finished | Oct 14 11:43:20 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=593643725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .sysrst_ctrl_csr_mem_rw_with_rand_reset.593643725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1130856145 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2142706898 ps |
| CPU time | 3.12 seconds |
| Started | Oct 14 11:43:09 PM UTC 24 |
| Finished | Oct 14 11:43:13 PM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130856145 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.1130856145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3975339717 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2018091417 ps |
| CPU time | 6.53 seconds |
| Started | Oct 14 11:43:09 PM UTC 24 |
| Finished | Oct 14 11:43:16 PM UTC 24 |
| Peak memory | 209392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975339717 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.3975339717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4124000339 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 4997383214 ps |
| CPU time | 15.38 seconds |
| Started | Oct 14 11:43:10 PM UTC 24 |
| Finished | Oct 14 11:43:26 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124000339 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.4124000339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2780861011 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2194257767 ps |
| CPU time | 4.39 seconds |
| Started | Oct 14 11:43:04 PM UTC 24 |
| Finished | Oct 14 11:43:10 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780861011 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.2780861011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3502547829 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 22488047761 ps |
| CPU time | 21.87 seconds |
| Started | Oct 14 11:43:06 PM UTC 24 |
| Finished | Oct 14 11:43:30 PM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502547829 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.3502547829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1453726007 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2041026847 ps |
| CPU time | 11.07 seconds |
| Started | Oct 14 11:43:16 PM UTC 24 |
| Finished | Oct 14 11:43:29 PM UTC 24 |
| Peak memory | 209712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1453726007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1453726007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2335164646 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2064896322 ps |
| CPU time | 4.64 seconds |
| Started | Oct 14 11:43:14 PM UTC 24 |
| Finished | Oct 14 11:43:21 PM UTC 24 |
| Peak memory | 209388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335164646 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.2335164646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3908446484 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2046882966 ps |
| CPU time | 3.22 seconds |
| Started | Oct 14 11:43:14 PM UTC 24 |
| Finished | Oct 14 11:43:19 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908446484 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.3908446484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.931686032 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 7663889034 ps |
| CPU time | 33.01 seconds |
| Started | Oct 14 11:43:14 PM UTC 24 |
| Finished | Oct 14 11:43:49 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931686032 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.931686032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.657063840 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2210796530 ps |
| CPU time | 3.25 seconds |
| Started | Oct 14 11:43:11 PM UTC 24 |
| Finished | Oct 14 11:43:15 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657063840 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.657063840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3447555285 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 22249975789 ps |
| CPU time | 58.66 seconds |
| Started | Oct 14 11:43:12 PM UTC 24 |
| Finished | Oct 14 11:44:12 PM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447555285 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.3447555285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4075041345 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2051125838 ps |
| CPU time | 5.67 seconds |
| Started | Oct 14 11:43:23 PM UTC 24 |
| Finished | Oct 14 11:43:30 PM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4075041345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.4075041345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3576826245 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2035636766 ps |
| CPU time | 11.36 seconds |
| Started | Oct 14 11:43:21 PM UTC 24 |
| Finished | Oct 14 11:43:34 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576826245 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.3576826245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1287354091 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2013526491 ps |
| CPU time | 7.21 seconds |
| Started | Oct 14 11:43:20 PM UTC 24 |
| Finished | Oct 14 11:43:28 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287354091 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.1287354091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.838156816 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 10042717423 ps |
| CPU time | 37.59 seconds |
| Started | Oct 14 11:43:21 PM UTC 24 |
| Finished | Oct 14 11:44:00 PM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838156816 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.838156816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3834151602 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2606148880 ps |
| CPU time | 3.09 seconds |
| Started | Oct 14 11:43:17 PM UTC 24 |
| Finished | Oct 14 11:43:22 PM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834151602 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.3834151602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.4255422931 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 46432406782 ps |
| CPU time | 16.17 seconds |
| Started | Oct 14 11:43:19 PM UTC 24 |
| Finished | Oct 14 11:43:36 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255422931 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.4255422931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2267701390 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2086929636 ps |
| CPU time | 3.39 seconds |
| Started | Oct 14 11:43:31 PM UTC 24 |
| Finished | Oct 14 11:43:35 PM UTC 24 |
| Peak memory | 209584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2267701390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2267701390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2236941909 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2060980801 ps |
| CPU time | 3.65 seconds |
| Started | Oct 14 11:43:31 PM UTC 24 |
| Finished | Oct 14 11:43:36 PM UTC 24 |
| Peak memory | 209720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236941909 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.2236941909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1353445871 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2014498924 ps |
| CPU time | 5.59 seconds |
| Started | Oct 14 11:43:29 PM UTC 24 |
| Finished | Oct 14 11:43:36 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353445871 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.1353445871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.357384905 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4903202653 ps |
| CPU time | 29.96 seconds |
| Started | Oct 14 11:43:31 PM UTC 24 |
| Finished | Oct 14 11:44:02 PM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357384905 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.357384905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.526124430 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2180369604 ps |
| CPU time | 5.38 seconds |
| Started | Oct 14 11:43:24 PM UTC 24 |
| Finished | Oct 14 11:43:31 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526124430 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.526124430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3829718482 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 42753693299 ps |
| CPU time | 47.54 seconds |
| Started | Oct 14 11:43:27 PM UTC 24 |
| Finished | Oct 14 11:44:16 PM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829718482 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.3829718482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.98064534 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2370090827 ps |
| CPU time | 2.42 seconds |
| Started | Oct 14 11:43:37 PM UTC 24 |
| Finished | Oct 14 11:43:41 PM UTC 24 |
| Peak memory | 209640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=98064534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. sysrst_ctrl_csr_mem_rw_with_rand_reset.98064534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2930617610 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2046050271 ps |
| CPU time | 6.25 seconds |
| Started | Oct 14 11:43:36 PM UTC 24 |
| Finished | Oct 14 11:43:43 PM UTC 24 |
| Peak memory | 209452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930617610 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.2930617610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.756745539 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2018702292 ps |
| CPU time | 6.08 seconds |
| Started | Oct 14 11:43:36 PM UTC 24 |
| Finished | Oct 14 11:43:43 PM UTC 24 |
| Peak memory | 209356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756745539 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.756745539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2712210971 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4873682971 ps |
| CPU time | 7.25 seconds |
| Started | Oct 14 11:43:37 PM UTC 24 |
| Finished | Oct 14 11:43:46 PM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712210971 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.2712210971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1794936173 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2095514620 ps |
| CPU time | 4.64 seconds |
| Started | Oct 14 11:43:32 PM UTC 24 |
| Finished | Oct 14 11:43:38 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794936173 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.1794936173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2119506561 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2038393628 ps |
| CPU time | 9.97 seconds |
| Started | Oct 14 11:43:44 PM UTC 24 |
| Finished | Oct 14 11:43:55 PM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2119506561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2119506561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1196404308 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2060985788 ps |
| CPU time | 11.07 seconds |
| Started | Oct 14 11:43:43 PM UTC 24 |
| Finished | Oct 14 11:43:55 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196404308 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.1196404308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1950292391 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2030360845 ps |
| CPU time | 3.6 seconds |
| Started | Oct 14 11:43:42 PM UTC 24 |
| Finished | Oct 14 11:43:46 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950292391 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.1950292391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1972484326 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 10583142052 ps |
| CPU time | 7.63 seconds |
| Started | Oct 14 11:43:44 PM UTC 24 |
| Finished | Oct 14 11:43:53 PM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972484326 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.1972484326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2840606243 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2246670775 ps |
| CPU time | 2.93 seconds |
| Started | Oct 14 11:43:39 PM UTC 24 |
| Finished | Oct 14 11:43:42 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840606243 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.2840606243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3278383016 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 22270700710 ps |
| CPU time | 28.13 seconds |
| Started | Oct 14 11:43:42 PM UTC 24 |
| Finished | Oct 14 11:44:11 PM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278383016 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.3278383016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3876144916 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2106852812 ps |
| CPU time | 3.98 seconds |
| Started | Oct 14 11:43:54 PM UTC 24 |
| Finished | Oct 14 11:43:59 PM UTC 24 |
| Peak memory | 209840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3876144916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3876144916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2442832538 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2055863504 ps |
| CPU time | 10 seconds |
| Started | Oct 14 11:43:50 PM UTC 24 |
| Finished | Oct 14 11:44:01 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442832538 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.2442832538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2603617739 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2039305749 ps |
| CPU time | 3.21 seconds |
| Started | Oct 14 11:43:48 PM UTC 24 |
| Finished | Oct 14 11:43:52 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603617739 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.2603617739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3930929015 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 4396599570 ps |
| CPU time | 11.38 seconds |
| Started | Oct 14 11:43:53 PM UTC 24 |
| Finished | Oct 14 11:44:05 PM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930929015 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.3930929015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4041331824 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2047023007 ps |
| CPU time | 11.85 seconds |
| Started | Oct 14 11:43:46 PM UTC 24 |
| Finished | Oct 14 11:43:59 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041331824 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.4041331824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1076069097 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 22183436950 ps |
| CPU time | 66.64 seconds |
| Started | Oct 14 11:43:47 PM UTC 24 |
| Finished | Oct 14 11:44:56 PM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076069097 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.1076069097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.760433618 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2069686356 ps |
| CPU time | 12.53 seconds |
| Started | Oct 14 11:44:01 PM UTC 24 |
| Finished | Oct 14 11:44:14 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=760433618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .sysrst_ctrl_csr_mem_rw_with_rand_reset.760433618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1939895810 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2107542494 ps |
| CPU time | 2.71 seconds |
| Started | Oct 14 11:43:59 PM UTC 24 |
| Finished | Oct 14 11:44:03 PM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939895810 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.1939895810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1594215865 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 2012778149 ps |
| CPU time | 6.36 seconds |
| Started | Oct 14 11:43:57 PM UTC 24 |
| Finished | Oct 14 11:44:05 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594215865 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.1594215865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3024563051 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 5304094030 ps |
| CPU time | 24.95 seconds |
| Started | Oct 14 11:44:01 PM UTC 24 |
| Finished | Oct 14 11:44:27 PM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024563051 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.3024563051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1273355337 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2252534469 ps |
| CPU time | 5.35 seconds |
| Started | Oct 14 11:43:56 PM UTC 24 |
| Finished | Oct 14 11:44:03 PM UTC 24 |
| Peak memory | 219904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273355337 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.1273355337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3222689894 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 42522278539 ps |
| CPU time | 49.4 seconds |
| Started | Oct 14 11:43:56 PM UTC 24 |
| Finished | Oct 14 11:44:47 PM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222689894 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.3222689894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.958792403 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2047678291 ps |
| CPU time | 6.07 seconds |
| Started | Oct 14 11:44:07 PM UTC 24 |
| Finished | Oct 14 11:44:14 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=958792403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .sysrst_ctrl_csr_mem_rw_with_rand_reset.958792403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.564014484 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2035773933 ps |
| CPU time | 10.54 seconds |
| Started | Oct 14 11:44:04 PM UTC 24 |
| Finished | Oct 14 11:44:16 PM UTC 24 |
| Peak memory | 209448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564014484 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.564014484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3061008681 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2029815983 ps |
| CPU time | 2.14 seconds |
| Started | Oct 14 11:44:03 PM UTC 24 |
| Finished | Oct 14 11:44:06 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061008681 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.3061008681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2754525953 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 10061690048 ps |
| CPU time | 3.93 seconds |
| Started | Oct 14 11:44:05 PM UTC 24 |
| Finished | Oct 14 11:44:10 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754525953 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.2754525953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3205383065 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2231041537 ps |
| CPU time | 7.71 seconds |
| Started | Oct 14 11:44:02 PM UTC 24 |
| Finished | Oct 14 11:44:11 PM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205383065 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.3205383065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3361502316 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 22626980004 ps |
| CPU time | 19.11 seconds |
| Started | Oct 14 11:44:03 PM UTC 24 |
| Finished | Oct 14 11:44:23 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361502316 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.3361502316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1335564947 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2107865292 ps |
| CPU time | 5.84 seconds |
| Started | Oct 14 11:44:13 PM UTC 24 |
| Finished | Oct 14 11:44:20 PM UTC 24 |
| Peak memory | 209520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1335564947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1335564947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2953129861 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2053844793 ps |
| CPU time | 3.82 seconds |
| Started | Oct 14 11:44:12 PM UTC 24 |
| Finished | Oct 14 11:44:17 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953129861 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.2953129861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3799158249 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2015284469 ps |
| CPU time | 9.53 seconds |
| Started | Oct 14 11:44:12 PM UTC 24 |
| Finished | Oct 14 11:44:23 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799158249 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.3799158249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.200358143 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4727187881 ps |
| CPU time | 7.9 seconds |
| Started | Oct 14 11:44:13 PM UTC 24 |
| Finished | Oct 14 11:44:22 PM UTC 24 |
| Peak memory | 209936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200358143 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.200358143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3709396014 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2122830728 ps |
| CPU time | 6.39 seconds |
| Started | Oct 14 11:44:07 PM UTC 24 |
| Finished | Oct 14 11:44:14 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709396014 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.3709396014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2519080082 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 22338394102 ps |
| CPU time | 24.97 seconds |
| Started | Oct 14 11:44:11 PM UTC 24 |
| Finished | Oct 14 11:44:37 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519080082 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.2519080082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.225079463 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2510224224 ps |
| CPU time | 16.78 seconds |
| Started | Oct 14 11:41:56 PM UTC 24 |
| Finished | Oct 14 11:42:14 PM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225079463 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.225079463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4191763343 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 39165344903 ps |
| CPU time | 113.55 seconds |
| Started | Oct 14 11:41:51 PM UTC 24 |
| Finished | Oct 14 11:43:47 PM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191763343 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.4191763343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3459181740 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 6013460519 ps |
| CPU time | 21.24 seconds |
| Started | Oct 14 11:41:49 PM UTC 24 |
| Finished | Oct 14 11:42:11 PM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459181740 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.3459181740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2808614775 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2044665442 ps |
| CPU time | 3.32 seconds |
| Started | Oct 14 11:41:58 PM UTC 24 |
| Finished | Oct 14 11:42:03 PM UTC 24 |
| Peak memory | 209840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2808614775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2808614775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2251043748 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2012933507 ps |
| CPU time | 6.43 seconds |
| Started | Oct 14 11:41:49 PM UTC 24 |
| Finished | Oct 14 11:41:56 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251043748 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.2251043748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.479676388 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4672813209 ps |
| CPU time | 16.7 seconds |
| Started | Oct 14 11:41:57 PM UTC 24 |
| Finished | Oct 14 11:42:15 PM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479676388 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.479676388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.578546256 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2044634180 ps |
| CPU time | 7.45 seconds |
| Started | Oct 14 11:41:39 PM UTC 24 |
| Finished | Oct 14 11:41:48 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578546256 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.578546256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.285884689 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2015106868 ps |
| CPU time | 9.24 seconds |
| Started | Oct 14 11:44:14 PM UTC 24 |
| Finished | Oct 14 11:44:25 PM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285884689 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.285884689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3397425738 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2034231368 ps |
| CPU time | 3.47 seconds |
| Started | Oct 14 11:44:14 PM UTC 24 |
| Finished | Oct 14 11:44:19 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397425738 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.3397425738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2688535946 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2028454243 ps |
| CPU time | 3.14 seconds |
| Started | Oct 14 11:44:16 PM UTC 24 |
| Finished | Oct 14 11:44:20 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688535946 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.2688535946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.753631591 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2047180165 ps |
| CPU time | 1.89 seconds |
| Started | Oct 14 11:44:17 PM UTC 24 |
| Finished | Oct 14 11:44:20 PM UTC 24 |
| Peak memory | 208584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753631591 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.753631591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.858891412 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2056689981 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 11:44:18 PM UTC 24 |
| Finished | Oct 14 11:44:21 PM UTC 24 |
| Peak memory | 207988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858891412 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.858891412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3123266693 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2020175674 ps |
| CPU time | 5.87 seconds |
| Started | Oct 14 11:44:18 PM UTC 24 |
| Finished | Oct 14 11:44:25 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123266693 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.3123266693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3299529653 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2050974455 ps |
| CPU time | 2.35 seconds |
| Started | Oct 14 11:44:18 PM UTC 24 |
| Finished | Oct 14 11:44:21 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299529653 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.3299529653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1101364696 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2032649056 ps |
| CPU time | 3.26 seconds |
| Started | Oct 14 11:44:20 PM UTC 24 |
| Finished | Oct 14 11:44:25 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101364696 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.1101364696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2902989738 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2091350291 ps |
| CPU time | 1.47 seconds |
| Started | Oct 14 11:44:20 PM UTC 24 |
| Finished | Oct 14 11:44:23 PM UTC 24 |
| Peak memory | 207980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902989738 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.2902989738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.309859913 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2076563263 ps |
| CPU time | 1.89 seconds |
| Started | Oct 14 11:44:20 PM UTC 24 |
| Finished | Oct 14 11:44:23 PM UTC 24 |
| Peak memory | 208584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309859913 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.309859913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3840933403 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3078960573 ps |
| CPU time | 16.93 seconds |
| Started | Oct 14 11:42:12 PM UTC 24 |
| Finished | Oct 14 11:42:30 PM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840933403 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.3840933403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2835533234 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 40165424010 ps |
| CPU time | 268.88 seconds |
| Started | Oct 14 11:42:12 PM UTC 24 |
| Finished | Oct 14 11:46:45 PM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835533234 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.2835533234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.858255254 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 6206604071 ps |
| CPU time | 2.81 seconds |
| Started | Oct 14 11:42:06 PM UTC 24 |
| Finished | Oct 14 11:42:09 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858255254 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.858255254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1202116431 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2107249260 ps |
| CPU time | 3.64 seconds |
| Started | Oct 14 11:42:16 PM UTC 24 |
| Finished | Oct 14 11:42:21 PM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1202116431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3 .sysrst_ctrl_csr_mem_rw_with_rand_reset.1202116431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.256330110 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2036248372 ps |
| CPU time | 11.92 seconds |
| Started | Oct 14 11:42:11 PM UTC 24 |
| Finished | Oct 14 11:42:24 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256330110 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.256330110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3943002473 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 2012794568 ps |
| CPU time | 11.68 seconds |
| Started | Oct 14 11:42:04 PM UTC 24 |
| Finished | Oct 14 11:42:17 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943002473 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.3943002473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.296687690 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 7270504645 ps |
| CPU time | 11.01 seconds |
| Started | Oct 14 11:42:15 PM UTC 24 |
| Finished | Oct 14 11:42:27 PM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296687690 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.296687690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1060022512 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2271492361 ps |
| CPU time | 3.02 seconds |
| Started | Oct 14 11:42:00 PM UTC 24 |
| Finished | Oct 14 11:42:04 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060022512 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.1060022512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2341057555 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 42572393650 ps |
| CPU time | 78.08 seconds |
| Started | Oct 14 11:42:03 PM UTC 24 |
| Finished | Oct 14 11:43:23 PM UTC 24 |
| Peak memory | 209768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341057555 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.2341057555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1594654951 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2025003380 ps |
| CPU time | 4.18 seconds |
| Started | Oct 14 11:44:22 PM UTC 24 |
| Finished | Oct 14 11:44:27 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594654951 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.1594654951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1336977621 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2009768311 ps |
| CPU time | 9.48 seconds |
| Started | Oct 14 11:44:22 PM UTC 24 |
| Finished | Oct 14 11:44:32 PM UTC 24 |
| Peak memory | 209396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336977621 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.1336977621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1207259663 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2035032902 ps |
| CPU time | 3.12 seconds |
| Started | Oct 14 11:44:23 PM UTC 24 |
| Finished | Oct 14 11:44:27 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207259663 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.1207259663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1652205300 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2014948304 ps |
| CPU time | 8.14 seconds |
| Started | Oct 14 11:44:23 PM UTC 24 |
| Finished | Oct 14 11:44:32 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652205300 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.1652205300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.894016658 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 2015487378 ps |
| CPU time | 3.79 seconds |
| Started | Oct 14 11:44:23 PM UTC 24 |
| Finished | Oct 14 11:44:28 PM UTC 24 |
| Peak memory | 209356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894016658 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.894016658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3216148823 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2022133008 ps |
| CPU time | 4.55 seconds |
| Started | Oct 14 11:44:24 PM UTC 24 |
| Finished | Oct 14 11:44:30 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216148823 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.3216148823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1431459211 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2061646148 ps |
| CPU time | 1.35 seconds |
| Started | Oct 14 11:44:24 PM UTC 24 |
| Finished | Oct 14 11:44:27 PM UTC 24 |
| Peak memory | 208576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431459211 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.1431459211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.4061141327 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2042565284 ps |
| CPU time | 2.57 seconds |
| Started | Oct 14 11:44:24 PM UTC 24 |
| Finished | Oct 14 11:44:28 PM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061141327 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.4061141327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3595666360 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2043444370 ps |
| CPU time | 1.98 seconds |
| Started | Oct 14 11:44:24 PM UTC 24 |
| Finished | Oct 14 11:44:27 PM UTC 24 |
| Peak memory | 207980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595666360 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.3595666360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2868194482 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2008012983 ps |
| CPU time | 10.86 seconds |
| Started | Oct 14 11:44:26 PM UTC 24 |
| Finished | Oct 14 11:44:38 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868194482 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.2868194482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3236206292 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2924269567 ps |
| CPU time | 17.9 seconds |
| Started | Oct 14 11:42:27 PM UTC 24 |
| Finished | Oct 14 11:42:46 PM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236206292 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.3236206292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1931657836 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 37838654143 ps |
| CPU time | 172.61 seconds |
| Started | Oct 14 11:42:25 PM UTC 24 |
| Finished | Oct 14 11:45:20 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931657836 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.1931657836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1549607809 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4038069088 ps |
| CPU time | 5.12 seconds |
| Started | Oct 14 11:42:22 PM UTC 24 |
| Finished | Oct 14 11:42:29 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549607809 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.1549607809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1231258347 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2036253257 ps |
| CPU time | 11.08 seconds |
| Started | Oct 14 11:42:28 PM UTC 24 |
| Finished | Oct 14 11:42:40 PM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1231258347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .sysrst_ctrl_csr_mem_rw_with_rand_reset.1231258347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3172513433 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2113173609 ps |
| CPU time | 3.6 seconds |
| Started | Oct 14 11:42:22 PM UTC 24 |
| Finished | Oct 14 11:42:27 PM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172513433 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.3172513433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2502596197 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2025036615 ps |
| CPU time | 3.03 seconds |
| Started | Oct 14 11:42:21 PM UTC 24 |
| Finished | Oct 14 11:42:25 PM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502596197 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.2502596197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1315852810 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 9723784403 ps |
| CPU time | 25.02 seconds |
| Started | Oct 14 11:42:28 PM UTC 24 |
| Finished | Oct 14 11:42:54 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315852810 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.1315852810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3071942546 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 45370215433 ps |
| CPU time | 14.75 seconds |
| Started | Oct 14 11:42:18 PM UTC 24 |
| Finished | Oct 14 11:42:34 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071942546 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.3071942546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2398385691 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2014805565 ps |
| CPU time | 3.8 seconds |
| Started | Oct 14 11:44:26 PM UTC 24 |
| Finished | Oct 14 11:44:31 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398385691 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.2398385691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.4131698186 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2010941525 ps |
| CPU time | 5.03 seconds |
| Started | Oct 14 11:44:26 PM UTC 24 |
| Finished | Oct 14 11:44:32 PM UTC 24 |
| Peak memory | 209716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131698186 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.4131698186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.233293610 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2015613870 ps |
| CPU time | 10.18 seconds |
| Started | Oct 14 11:44:26 PM UTC 24 |
| Finished | Oct 14 11:44:37 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233293610 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.233293610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1632016443 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 2018208452 ps |
| CPU time | 8.63 seconds |
| Started | Oct 14 11:44:27 PM UTC 24 |
| Finished | Oct 14 11:44:37 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632016443 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.1632016443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1628504406 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2015410515 ps |
| CPU time | 9.19 seconds |
| Started | Oct 14 11:44:27 PM UTC 24 |
| Finished | Oct 14 11:44:37 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628504406 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.1628504406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2904881678 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2013884170 ps |
| CPU time | 7.22 seconds |
| Started | Oct 14 11:44:29 PM UTC 24 |
| Finished | Oct 14 11:44:37 PM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904881678 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.2904881678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.718639706 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2022638658 ps |
| CPU time | 5.41 seconds |
| Started | Oct 14 11:44:29 PM UTC 24 |
| Finished | Oct 14 11:44:35 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718639706 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.718639706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.433612044 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 2013168456 ps |
| CPU time | 9.58 seconds |
| Started | Oct 14 11:44:29 PM UTC 24 |
| Finished | Oct 14 11:44:39 PM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433612044 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.433612044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3944053102 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2014878739 ps |
| CPU time | 5.02 seconds |
| Started | Oct 14 11:44:29 PM UTC 24 |
| Finished | Oct 14 11:44:35 PM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944053102 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.3944053102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.4152297028 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2013835367 ps |
| CPU time | 5.96 seconds |
| Started | Oct 14 11:44:29 PM UTC 24 |
| Finished | Oct 14 11:44:36 PM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152297028 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.4152297028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.4134591793 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 2047429104 ps |
| CPU time | 6.35 seconds |
| Started | Oct 14 11:42:35 PM UTC 24 |
| Finished | Oct 14 11:42:43 PM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4134591793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5 .sysrst_ctrl_csr_mem_rw_with_rand_reset.4134591793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2056325204 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2030903306 ps |
| CPU time | 10.3 seconds |
| Started | Oct 14 11:42:32 PM UTC 24 |
| Finished | Oct 14 11:42:44 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056325204 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.2056325204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2529080317 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 2040919903 ps |
| CPU time | 3.48 seconds |
| Started | Oct 14 11:42:31 PM UTC 24 |
| Finished | Oct 14 11:42:36 PM UTC 24 |
| Peak memory | 209284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529080317 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.2529080317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1625105181 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5189394106 ps |
| CPU time | 9.27 seconds |
| Started | Oct 14 11:42:35 PM UTC 24 |
| Finished | Oct 14 11:42:46 PM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625105181 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.1625105181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.152111552 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3577807630 ps |
| CPU time | 3.17 seconds |
| Started | Oct 14 11:42:30 PM UTC 24 |
| Finished | Oct 14 11:42:34 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152111552 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.152111552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2199726459 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 22546874667 ps |
| CPU time | 22.24 seconds |
| Started | Oct 14 11:42:31 PM UTC 24 |
| Finished | Oct 14 11:42:55 PM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199726459 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.2199726459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3163097975 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2477661772 ps |
| CPU time | 2.31 seconds |
| Started | Oct 14 11:42:46 PM UTC 24 |
| Finished | Oct 14 11:42:49 PM UTC 24 |
| Peak memory | 209640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3163097975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3163097975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1192432716 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2036922209 ps |
| CPU time | 5.03 seconds |
| Started | Oct 14 11:42:44 PM UTC 24 |
| Finished | Oct 14 11:42:50 PM UTC 24 |
| Peak memory | 209392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192432716 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.1192432716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2187096508 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 2032350683 ps |
| CPU time | 2.56 seconds |
| Started | Oct 14 11:42:42 PM UTC 24 |
| Finished | Oct 14 11:42:45 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187096508 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.2187096508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2630753860 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 8429322438 ps |
| CPU time | 13.29 seconds |
| Started | Oct 14 11:42:45 PM UTC 24 |
| Finished | Oct 14 11:42:59 PM UTC 24 |
| Peak memory | 209956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630753860 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.2630753860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1090337380 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2154297854 ps |
| CPU time | 12.44 seconds |
| Started | Oct 14 11:42:36 PM UTC 24 |
| Finished | Oct 14 11:42:50 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090337380 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.1090337380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3771949685 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 42415756881 ps |
| CPU time | 156.08 seconds |
| Started | Oct 14 11:42:41 PM UTC 24 |
| Finished | Oct 14 11:45:19 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771949685 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.3771949685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3473226272 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2070366820 ps |
| CPU time | 9.07 seconds |
| Started | Oct 14 11:42:51 PM UTC 24 |
| Finished | Oct 14 11:43:01 PM UTC 24 |
| Peak memory | 209588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3473226272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3473226272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4283286598 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2049217966 ps |
| CPU time | 7.83 seconds |
| Started | Oct 14 11:42:50 PM UTC 24 |
| Finished | Oct 14 11:42:59 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283286598 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.4283286598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3127170844 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 2025002958 ps |
| CPU time | 5.77 seconds |
| Started | Oct 14 11:42:47 PM UTC 24 |
| Finished | Oct 14 11:42:54 PM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127170844 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.3127170844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2492962069 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5377822281 ps |
| CPU time | 16.19 seconds |
| Started | Oct 14 11:42:50 PM UTC 24 |
| Finished | Oct 14 11:43:07 PM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492962069 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.2492962069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3021504350 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2057801316 ps |
| CPU time | 9.35 seconds |
| Started | Oct 14 11:42:46 PM UTC 24 |
| Finished | Oct 14 11:42:56 PM UTC 24 |
| Peak memory | 209724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021504350 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.3021504350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.641569355 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 22187742150 ps |
| CPU time | 52.2 seconds |
| Started | Oct 14 11:42:47 PM UTC 24 |
| Finished | Oct 14 11:43:41 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641569355 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.641569355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3234385329 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2095669416 ps |
| CPU time | 2.28 seconds |
| Started | Oct 14 11:43:00 PM UTC 24 |
| Finished | Oct 14 11:43:03 PM UTC 24 |
| Peak memory | 209776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3234385329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3234385329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3263871907 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2031932268 ps |
| CPU time | 6.14 seconds |
| Started | Oct 14 11:42:57 PM UTC 24 |
| Finished | Oct 14 11:43:04 PM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263871907 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.3263871907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2337934548 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2033458129 ps |
| CPU time | 3.28 seconds |
| Started | Oct 14 11:42:56 PM UTC 24 |
| Finished | Oct 14 11:43:00 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337934548 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.2337934548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1200012862 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 10687127087 ps |
| CPU time | 12.04 seconds |
| Started | Oct 14 11:42:57 PM UTC 24 |
| Finished | Oct 14 11:43:10 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200012862 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.1200012862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.336623388 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2084569324 ps |
| CPU time | 6.84 seconds |
| Started | Oct 14 11:42:54 PM UTC 24 |
| Finished | Oct 14 11:43:02 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336623388 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.336623388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2118830044 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 42587538907 ps |
| CPU time | 84 seconds |
| Started | Oct 14 11:42:56 PM UTC 24 |
| Finished | Oct 14 11:44:21 PM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118830044 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.2118830044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2458900307 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2076511940 ps |
| CPU time | 5.18 seconds |
| Started | Oct 14 11:43:04 PM UTC 24 |
| Finished | Oct 14 11:43:11 PM UTC 24 |
| Peak memory | 209520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2458900307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2458900307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.563685430 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2038860799 ps |
| CPU time | 8.6 seconds |
| Started | Oct 14 11:43:03 PM UTC 24 |
| Finished | Oct 14 11:43:13 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563685430 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.563685430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.832738442 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2098524679 ps |
| CPU time | 2.27 seconds |
| Started | Oct 14 11:43:02 PM UTC 24 |
| Finished | Oct 14 11:43:05 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832738442 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.832738442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1335743490 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5118725964 ps |
| CPU time | 9.08 seconds |
| Started | Oct 14 11:43:03 PM UTC 24 |
| Finished | Oct 14 11:43:13 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335743490 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.1335743490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2447796143 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2418157568 ps |
| CPU time | 6.41 seconds |
| Started | Oct 14 11:43:00 PM UTC 24 |
| Finished | Oct 14 11:43:07 PM UTC 24 |
| Peak memory | 209932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447796143 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.2447796143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.4014395526 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 42616214321 ps |
| CPU time | 53.79 seconds |
| Started | Oct 14 11:43:01 PM UTC 24 |
| Finished | Oct 14 11:43:56 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014395526 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.4014395526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1480757640 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3372515229 ps |
| CPU time | 9.3 seconds |
| Started | Oct 14 10:12:18 PM UTC 24 |
| Finished | Oct 14 10:12:29 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480757640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1480757640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2599290825 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2529161179 ps |
| CPU time | 4.6 seconds |
| Started | Oct 14 10:12:11 PM UTC 24 |
| Finished | Oct 14 10:12:17 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599290825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2599290825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3429806117 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3548057224 ps |
| CPU time | 11.87 seconds |
| Started | Oct 14 10:12:20 PM UTC 24 |
| Finished | Oct 14 10:12:33 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429806117 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.3429806117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.4229139016 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2614937178 ps |
| CPU time | 8.34 seconds |
| Started | Oct 14 10:12:17 PM UTC 24 |
| Finished | Oct 14 10:12:26 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229139016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.4229139016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1779527053 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2237246557 ps |
| CPU time | 3.47 seconds |
| Started | Oct 14 10:12:13 PM UTC 24 |
| Finished | Oct 14 10:12:17 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779527053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1779527053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2922419809 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 42010792757 ps |
| CPU time | 144.37 seconds |
| Started | Oct 14 10:12:25 PM UTC 24 |
| Finished | Oct 14 10:14:52 PM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922419809 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.2922419809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.3940636241 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2110371376 ps |
| CPU time | 11.47 seconds |
| Started | Oct 14 10:12:08 PM UTC 24 |
| Finished | Oct 14 10:12:20 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940636241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3940636241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.4133586243 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5716823503 ps |
| CPU time | 15.13 seconds |
| Started | Oct 14 10:12:18 PM UTC 24 |
| Finished | Oct 14 10:12:35 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133586243 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.4133586243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3403041096 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2030406937 ps |
| CPU time | 3.28 seconds |
| Started | Oct 14 10:12:39 PM UTC 24 |
| Finished | Oct 14 10:12:43 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403041096 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.3403041096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3563152376 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 139203652343 ps |
| CPU time | 398.87 seconds |
| Started | Oct 14 10:12:32 PM UTC 24 |
| Finished | Oct 14 10:19:16 PM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563152376 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.3563152376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2965485892 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2425921811 ps |
| CPU time | 11.29 seconds |
| Started | Oct 14 10:12:26 PM UTC 24 |
| Finished | Oct 14 10:12:39 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965485892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2965485892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2871473337 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2539628446 ps |
| CPU time | 9.35 seconds |
| Started | Oct 14 10:12:27 PM UTC 24 |
| Finished | Oct 14 10:12:38 PM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871473337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2871473337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.300392883 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4638576602 ps |
| CPU time | 16.37 seconds |
| Started | Oct 14 10:12:31 PM UTC 24 |
| Finished | Oct 14 10:12:48 PM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300392883 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.300392883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1003746872 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3080376940 ps |
| CPU time | 9.53 seconds |
| Started | Oct 14 10:12:33 PM UTC 24 |
| Finished | Oct 14 10:12:43 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003746872 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.1003746872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.23765879 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2618331841 ps |
| CPU time | 7.65 seconds |
| Started | Oct 14 10:12:31 PM UTC 24 |
| Finished | Oct 14 10:12:39 PM UTC 24 |
| Peak memory | 209144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23765879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.23765879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1455557619 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2487051433 ps |
| CPU time | 4.35 seconds |
| Started | Oct 14 10:12:26 PM UTC 24 |
| Finished | Oct 14 10:12:31 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455557619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1455557619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.1836947876 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2206903471 ps |
| CPU time | 9.05 seconds |
| Started | Oct 14 10:12:29 PM UTC 24 |
| Finished | Oct 14 10:12:40 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836947876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1836947876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2034243506 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2509759134 ps |
| CPU time | 7.98 seconds |
| Started | Oct 14 10:12:29 PM UTC 24 |
| Finished | Oct 14 10:12:39 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034243506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.2034243506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1061841862 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2113147768 ps |
| CPU time | 11.1 seconds |
| Started | Oct 14 10:12:26 PM UTC 24 |
| Finished | Oct 14 10:12:38 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061841862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.1061841862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2100551169 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 6560503057 ps |
| CPU time | 16.45 seconds |
| Started | Oct 14 10:12:35 PM UTC 24 |
| Finished | Oct 14 10:12:53 PM UTC 24 |
| Peak memory | 217796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2100551169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.2100551169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.840450534 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2010044285 ps |
| CPU time | 8.25 seconds |
| Started | Oct 14 10:14:09 PM UTC 24 |
| Finished | Oct 14 10:14:19 PM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840450534 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.840450534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3617539373 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3464127059 ps |
| CPU time | 13.1 seconds |
| Started | Oct 14 10:14:06 PM UTC 24 |
| Finished | Oct 14 10:14:20 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617539373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3617539373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.340523457 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 97762075781 ps |
| CPU time | 291.45 seconds |
| Started | Oct 14 10:14:07 PM UTC 24 |
| Finished | Oct 14 10:19:02 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340523457 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.340523457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2980372157 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5120879801 ps |
| CPU time | 2.47 seconds |
| Started | Oct 14 10:14:06 PM UTC 24 |
| Finished | Oct 14 10:14:09 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980372157 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.2980372157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.455231466 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3395294485 ps |
| CPU time | 13.63 seconds |
| Started | Oct 14 10:14:07 PM UTC 24 |
| Finished | Oct 14 10:14:22 PM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455231466 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.455231466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2472740448 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2626059046 ps |
| CPU time | 2.6 seconds |
| Started | Oct 14 10:14:05 PM UTC 24 |
| Finished | Oct 14 10:14:08 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472740448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2472740448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.612809645 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2465287075 ps |
| CPU time | 5.59 seconds |
| Started | Oct 14 10:14:00 PM UTC 24 |
| Finished | Oct 14 10:14:07 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612809645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.612809645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.758566148 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2274819735 ps |
| CPU time | 3.12 seconds |
| Started | Oct 14 10:14:02 PM UTC 24 |
| Finished | Oct 14 10:14:06 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758566148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.758566148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3975293332 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2528558860 ps |
| CPU time | 2.68 seconds |
| Started | Oct 14 10:14:04 PM UTC 24 |
| Finished | Oct 14 10:14:07 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975293332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3975293332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.1054374292 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2109141235 ps |
| CPU time | 10.99 seconds |
| Started | Oct 14 10:13:57 PM UTC 24 |
| Finished | Oct 14 10:14:10 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054374292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.1054374292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.678908285 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 14123372520 ps |
| CPU time | 9.65 seconds |
| Started | Oct 14 10:14:08 PM UTC 24 |
| Finished | Oct 14 10:14:19 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=678908285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.678908285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.291159168 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3752336416 ps |
| CPU time | 2.71 seconds |
| Started | Oct 14 10:14:07 PM UTC 24 |
| Finished | Oct 14 10:14:11 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291159168 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.291159168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2958641282 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2033942943 ps |
| CPU time | 3.2 seconds |
| Started | Oct 14 10:14:21 PM UTC 24 |
| Finished | Oct 14 10:14:25 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958641282 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.2958641282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.871354510 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3305100543 ps |
| CPU time | 2.15 seconds |
| Started | Oct 14 10:14:16 PM UTC 24 |
| Finished | Oct 14 10:14:19 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871354510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.871354510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3911826762 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 26592738690 ps |
| CPU time | 33.88 seconds |
| Started | Oct 14 10:14:18 PM UTC 24 |
| Finished | Oct 14 10:14:54 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911826762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.3911826762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3867352654 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4235042936 ps |
| CPU time | 6.13 seconds |
| Started | Oct 14 10:14:16 PM UTC 24 |
| Finished | Oct 14 10:14:23 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867352654 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.3867352654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3195215109 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2614207807 ps |
| CPU time | 7.99 seconds |
| Started | Oct 14 10:14:16 PM UTC 24 |
| Finished | Oct 14 10:14:25 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195215109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.3195215109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3768320014 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2489749525 ps |
| CPU time | 4.01 seconds |
| Started | Oct 14 10:14:11 PM UTC 24 |
| Finished | Oct 14 10:14:16 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768320014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3768320014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3384589407 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2083702453 ps |
| CPU time | 7.69 seconds |
| Started | Oct 14 10:14:11 PM UTC 24 |
| Finished | Oct 14 10:14:19 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384589407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.3384589407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3398962597 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2530009940 ps |
| CPU time | 3.49 seconds |
| Started | Oct 14 10:14:12 PM UTC 24 |
| Finished | Oct 14 10:14:16 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398962597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3398962597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2633579754 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2115498395 ps |
| CPU time | 6.01 seconds |
| Started | Oct 14 10:14:10 PM UTC 24 |
| Finished | Oct 14 10:14:17 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633579754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2633579754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2670620035 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 8285074770 ps |
| CPU time | 13.2 seconds |
| Started | Oct 14 10:14:21 PM UTC 24 |
| Finished | Oct 14 10:14:35 PM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670620035 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.2670620035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.4098434365 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 7900890897 ps |
| CPU time | 11.64 seconds |
| Started | Oct 14 10:14:19 PM UTC 24 |
| Finished | Oct 14 10:14:32 PM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4098434365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.4098434365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.4068340851 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2090422512 ps |
| CPU time | 1.84 seconds |
| Started | Oct 14 10:14:32 PM UTC 24 |
| Finished | Oct 14 10:14:35 PM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068340851 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.4068340851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1011108771 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3717227415 ps |
| CPU time | 5.39 seconds |
| Started | Oct 14 10:14:26 PM UTC 24 |
| Finished | Oct 14 10:14:33 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011108771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1011108771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4285848217 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 64208556189 ps |
| CPU time | 233.61 seconds |
| Started | Oct 14 10:14:29 PM UTC 24 |
| Finished | Oct 14 10:18:27 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285848217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_with_pre_cond.4285848217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3960184059 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2791544605 ps |
| CPU time | 10.94 seconds |
| Started | Oct 14 10:14:25 PM UTC 24 |
| Finished | Oct 14 10:14:37 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960184059 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.3960184059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1964223088 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3238824005 ps |
| CPU time | 10.35 seconds |
| Started | Oct 14 10:14:28 PM UTC 24 |
| Finished | Oct 14 10:14:40 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964223088 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.1964223088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2048367811 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2632370482 ps |
| CPU time | 3.98 seconds |
| Started | Oct 14 10:14:24 PM UTC 24 |
| Finished | Oct 14 10:14:29 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048367811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2048367811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1601517641 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2466943731 ps |
| CPU time | 13.43 seconds |
| Started | Oct 14 10:14:21 PM UTC 24 |
| Finished | Oct 14 10:14:35 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601517641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.1601517641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.888225381 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2106595485 ps |
| CPU time | 2.87 seconds |
| Started | Oct 14 10:14:23 PM UTC 24 |
| Finished | Oct 14 10:14:27 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888225381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.888225381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1695036424 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2135123221 ps |
| CPU time | 2.82 seconds |
| Started | Oct 14 10:14:21 PM UTC 24 |
| Finished | Oct 14 10:14:25 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695036424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1695036424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2497792556 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 93552564144 ps |
| CPU time | 363.6 seconds |
| Started | Oct 14 10:14:31 PM UTC 24 |
| Finished | Oct 14 10:20:39 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497792556 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.2497792556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3003656575 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 14898351426 ps |
| CPU time | 7.67 seconds |
| Started | Oct 14 10:14:30 PM UTC 24 |
| Finished | Oct 14 10:14:39 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3003656575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3003656575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4191105688 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 11445438751 ps |
| CPU time | 2.27 seconds |
| Started | Oct 14 10:14:26 PM UTC 24 |
| Finished | Oct 14 10:14:30 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191105688 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.4191105688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1700080294 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2015469297 ps |
| CPU time | 8.02 seconds |
| Started | Oct 14 10:14:49 PM UTC 24 |
| Finished | Oct 14 10:14:58 PM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700080294 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.1700080294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2623873287 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 67664817912 ps |
| CPU time | 112.05 seconds |
| Started | Oct 14 10:14:41 PM UTC 24 |
| Finished | Oct 14 10:16:36 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623873287 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.2623873287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3887854194 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 24332721083 ps |
| CPU time | 88.29 seconds |
| Started | Oct 14 10:14:43 PM UTC 24 |
| Finished | Oct 14 10:16:13 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887854194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.3887854194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.639939172 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3281958114 ps |
| CPU time | 4.83 seconds |
| Started | Oct 14 10:14:38 PM UTC 24 |
| Finished | Oct 14 10:14:44 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639939172 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.639939172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.2627749365 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3145136127 ps |
| CPU time | 8.01 seconds |
| Started | Oct 14 10:14:42 PM UTC 24 |
| Finished | Oct 14 10:14:51 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627749365 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.2627749365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2699704203 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2611101005 ps |
| CPU time | 11.11 seconds |
| Started | Oct 14 10:14:36 PM UTC 24 |
| Finished | Oct 14 10:14:48 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699704203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2699704203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.4090225910 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2467247419 ps |
| CPU time | 13.11 seconds |
| Started | Oct 14 10:14:34 PM UTC 24 |
| Finished | Oct 14 10:14:48 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090225910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.4090225910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.4070952162 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2168347809 ps |
| CPU time | 4.35 seconds |
| Started | Oct 14 10:14:36 PM UTC 24 |
| Finished | Oct 14 10:14:42 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070952162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.4070952162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.2204644212 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2132959008 ps |
| CPU time | 3.62 seconds |
| Started | Oct 14 10:14:33 PM UTC 24 |
| Finished | Oct 14 10:14:38 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204644212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2204644212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.943980570 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 109206227208 ps |
| CPU time | 313.99 seconds |
| Started | Oct 14 10:14:45 PM UTC 24 |
| Finished | Oct 14 10:20:03 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943980570 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.943980570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3708602544 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 17405217402 ps |
| CPU time | 19.72 seconds |
| Started | Oct 14 10:14:44 PM UTC 24 |
| Finished | Oct 14 10:15:05 PM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3708602544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3708602544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.942088187 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 7333967057 ps |
| CPU time | 7.51 seconds |
| Started | Oct 14 10:14:39 PM UTC 24 |
| Finished | Oct 14 10:14:48 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942088187 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.942088187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2737357271 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2015877751 ps |
| CPU time | 5.16 seconds |
| Started | Oct 14 10:15:04 PM UTC 24 |
| Finished | Oct 14 10:15:10 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737357271 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.2737357271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2728782418 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3484724827 ps |
| CPU time | 8.4 seconds |
| Started | Oct 14 10:14:53 PM UTC 24 |
| Finished | Oct 14 10:15:03 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728782418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2728782418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1626736218 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 40319361742 ps |
| CPU time | 131.31 seconds |
| Started | Oct 14 10:15:01 PM UTC 24 |
| Finished | Oct 14 10:17:14 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626736218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.1626736218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.384635802 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3619083580 ps |
| CPU time | 17.73 seconds |
| Started | Oct 14 10:14:53 PM UTC 24 |
| Finished | Oct 14 10:15:12 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384635802 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.384635802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.3182175842 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2964533326 ps |
| CPU time | 11.92 seconds |
| Started | Oct 14 10:14:59 PM UTC 24 |
| Finished | Oct 14 10:15:12 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182175842 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.3182175842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3146263943 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2611590719 ps |
| CPU time | 10.96 seconds |
| Started | Oct 14 10:14:52 PM UTC 24 |
| Finished | Oct 14 10:15:04 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146263943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3146263943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.3107129776 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2500384152 ps |
| CPU time | 5.69 seconds |
| Started | Oct 14 10:14:49 PM UTC 24 |
| Finished | Oct 14 10:14:56 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107129776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3107129776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4000293504 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2062654620 ps |
| CPU time | 2.12 seconds |
| Started | Oct 14 10:14:49 PM UTC 24 |
| Finished | Oct 14 10:14:52 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000293504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.4000293504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1876907246 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2512015136 ps |
| CPU time | 7.18 seconds |
| Started | Oct 14 10:14:52 PM UTC 24 |
| Finished | Oct 14 10:15:00 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876907246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1876907246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.2930025154 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2108361890 ps |
| CPU time | 9.88 seconds |
| Started | Oct 14 10:14:49 PM UTC 24 |
| Finished | Oct 14 10:15:00 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930025154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.2930025154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2266778258 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 9252540673 ps |
| CPU time | 8.65 seconds |
| Started | Oct 14 10:15:02 PM UTC 24 |
| Finished | Oct 14 10:15:12 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266778258 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.2266778258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1702642677 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8989537926 ps |
| CPU time | 36.1 seconds |
| Started | Oct 14 10:15:01 PM UTC 24 |
| Finished | Oct 14 10:15:38 PM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1702642677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1702642677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.665419685 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2032648550 ps |
| CPU time | 3.64 seconds |
| Started | Oct 14 10:15:21 PM UTC 24 |
| Finished | Oct 14 10:15:26 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665419685 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.665419685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1418934590 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3819093478 ps |
| CPU time | 17.28 seconds |
| Started | Oct 14 10:15:13 PM UTC 24 |
| Finished | Oct 14 10:15:31 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418934590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.1418934590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.609282520 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 134956240855 ps |
| CPU time | 60.4 seconds |
| Started | Oct 14 10:15:14 PM UTC 24 |
| Finished | Oct 14 10:16:16 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609282520 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.609282520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1898273420 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 61601120960 ps |
| CPU time | 90.37 seconds |
| Started | Oct 14 10:15:19 PM UTC 24 |
| Finished | Oct 14 10:16:51 PM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898273420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.1898273420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.696436852 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3504116619 ps |
| CPU time | 3.86 seconds |
| Started | Oct 14 10:15:13 PM UTC 24 |
| Finished | Oct 14 10:15:18 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696436852 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.696436852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.716508759 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5633815638 ps |
| CPU time | 6.37 seconds |
| Started | Oct 14 10:15:14 PM UTC 24 |
| Finished | Oct 14 10:15:21 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716508759 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.716508759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1477874099 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2612074470 ps |
| CPU time | 7.31 seconds |
| Started | Oct 14 10:15:11 PM UTC 24 |
| Finished | Oct 14 10:15:20 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477874099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1477874099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.967449814 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2458541142 ps |
| CPU time | 12.8 seconds |
| Started | Oct 14 10:15:06 PM UTC 24 |
| Finished | Oct 14 10:15:20 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967449814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.967449814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1376012482 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2087058620 ps |
| CPU time | 3.76 seconds |
| Started | Oct 14 10:15:08 PM UTC 24 |
| Finished | Oct 14 10:15:13 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376012482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1376012482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2164932780 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2534507411 ps |
| CPU time | 2.94 seconds |
| Started | Oct 14 10:15:09 PM UTC 24 |
| Finished | Oct 14 10:15:13 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164932780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2164932780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.4011879762 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2135951961 ps |
| CPU time | 2.93 seconds |
| Started | Oct 14 10:15:05 PM UTC 24 |
| Finished | Oct 14 10:15:09 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011879762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.4011879762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.2928373735 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 9256544476 ps |
| CPU time | 18.98 seconds |
| Started | Oct 14 10:15:21 PM UTC 24 |
| Finished | Oct 14 10:15:41 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928373735 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.2928373735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.760574115 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5051960711 ps |
| CPU time | 12.49 seconds |
| Started | Oct 14 10:15:19 PM UTC 24 |
| Finished | Oct 14 10:15:33 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=760574115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.760574115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.777685090 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 7609256408 ps |
| CPU time | 4.34 seconds |
| Started | Oct 14 10:15:13 PM UTC 24 |
| Finished | Oct 14 10:15:18 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777685090 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.777685090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.524236616 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2120720391 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 10:15:41 PM UTC 24 |
| Finished | Oct 14 10:15:44 PM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524236616 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.524236616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.4202382670 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3832398486 ps |
| CPU time | 5.83 seconds |
| Started | Oct 14 10:15:34 PM UTC 24 |
| Finished | Oct 14 10:15:41 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202382670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.4202382670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2324520492 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 54188318299 ps |
| CPU time | 81.52 seconds |
| Started | Oct 14 10:15:35 PM UTC 24 |
| Finished | Oct 14 10:16:58 PM UTC 24 |
| Peak memory | 209668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324520492 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.2324520492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.272804658 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 99951419397 ps |
| CPU time | 83.21 seconds |
| Started | Oct 14 10:15:39 PM UTC 24 |
| Finished | Oct 14 10:17:04 PM UTC 24 |
| Peak memory | 209740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272804658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.272804658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.983147315 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4094539207 ps |
| CPU time | 23.29 seconds |
| Started | Oct 14 10:15:33 PM UTC 24 |
| Finished | Oct 14 10:15:57 PM UTC 24 |
| Peak memory | 209144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983147315 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.983147315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3974749466 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2737270131 ps |
| CPU time | 13.56 seconds |
| Started | Oct 14 10:15:37 PM UTC 24 |
| Finished | Oct 14 10:15:52 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974749466 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.3974749466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.989430554 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2617328346 ps |
| CPU time | 5.22 seconds |
| Started | Oct 14 10:15:33 PM UTC 24 |
| Finished | Oct 14 10:15:39 PM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989430554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.989430554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3314583474 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2467643308 ps |
| CPU time | 6.27 seconds |
| Started | Oct 14 10:15:26 PM UTC 24 |
| Finished | Oct 14 10:15:34 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314583474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3314583474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.2182890490 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2038883320 ps |
| CPU time | 8.01 seconds |
| Started | Oct 14 10:15:32 PM UTC 24 |
| Finished | Oct 14 10:15:41 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182890490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2182890490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2634227136 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2509939173 ps |
| CPU time | 15.22 seconds |
| Started | Oct 14 10:15:32 PM UTC 24 |
| Finished | Oct 14 10:15:48 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634227136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2634227136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1357456288 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2107922255 ps |
| CPU time | 7.42 seconds |
| Started | Oct 14 10:15:22 PM UTC 24 |
| Finished | Oct 14 10:15:31 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357456288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1357456288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.3178378905 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 6316137190 ps |
| CPU time | 8.85 seconds |
| Started | Oct 14 10:15:40 PM UTC 24 |
| Finished | Oct 14 10:15:51 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178378905 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.3178378905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1725014060 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 13726049218 ps |
| CPU time | 16.38 seconds |
| Started | Oct 14 10:15:40 PM UTC 24 |
| Finished | Oct 14 10:15:58 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1725014060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1725014060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2191287703 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 6283464860 ps |
| CPU time | 3.65 seconds |
| Started | Oct 14 10:15:35 PM UTC 24 |
| Finished | Oct 14 10:15:40 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191287703 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.2191287703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.2336662251 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2014949645 ps |
| CPU time | 10.98 seconds |
| Started | Oct 14 10:15:59 PM UTC 24 |
| Finished | Oct 14 10:16:11 PM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336662251 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.2336662251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3603101523 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 220459566355 ps |
| CPU time | 678.33 seconds |
| Started | Oct 14 10:15:52 PM UTC 24 |
| Finished | Oct 14 10:27:17 PM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603101523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.3603101523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1228650046 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 88331964939 ps |
| CPU time | 165.54 seconds |
| Started | Oct 14 10:15:56 PM UTC 24 |
| Finished | Oct 14 10:18:45 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228650046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.1228650046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1583810146 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2743198395 ps |
| CPU time | 12 seconds |
| Started | Oct 14 10:15:49 PM UTC 24 |
| Finished | Oct 14 10:16:02 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583810146 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.1583810146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.359033653 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2764940876 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 10:15:54 PM UTC 24 |
| Finished | Oct 14 10:15:57 PM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359033653 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.359033653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1207757688 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2628648093 ps |
| CPU time | 4.62 seconds |
| Started | Oct 14 10:15:48 PM UTC 24 |
| Finished | Oct 14 10:15:54 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207757688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1207757688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.564422896 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2490105745 ps |
| CPU time | 2.67 seconds |
| Started | Oct 14 10:15:43 PM UTC 24 |
| Finished | Oct 14 10:15:46 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564422896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.564422896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1490359927 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2223830053 ps |
| CPU time | 5.97 seconds |
| Started | Oct 14 10:15:45 PM UTC 24 |
| Finished | Oct 14 10:15:52 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490359927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1490359927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3458667251 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2517780119 ps |
| CPU time | 7.84 seconds |
| Started | Oct 14 10:15:47 PM UTC 24 |
| Finished | Oct 14 10:15:56 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458667251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3458667251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.1971336315 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2123997679 ps |
| CPU time | 3.27 seconds |
| Started | Oct 14 10:15:42 PM UTC 24 |
| Finished | Oct 14 10:15:46 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971336315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1971336315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1334716253 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 155949620784 ps |
| CPU time | 107.15 seconds |
| Started | Oct 14 10:15:58 PM UTC 24 |
| Finished | Oct 14 10:17:47 PM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334716253 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.1334716253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.67429620 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 6399470241 ps |
| CPU time | 3.8 seconds |
| Started | Oct 14 10:15:53 PM UTC 24 |
| Finished | Oct 14 10:15:58 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67429620 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.67429620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2320890680 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2027114200 ps |
| CPU time | 3.11 seconds |
| Started | Oct 14 10:16:21 PM UTC 24 |
| Finished | Oct 14 10:16:25 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320890680 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.2320890680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4206961939 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3246208072 ps |
| CPU time | 8.75 seconds |
| Started | Oct 14 10:16:10 PM UTC 24 |
| Finished | Oct 14 10:16:20 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206961939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.4206961939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3062180916 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 85656065396 ps |
| CPU time | 170.98 seconds |
| Started | Oct 14 10:16:11 PM UTC 24 |
| Finished | Oct 14 10:19:05 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062180916 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.3062180916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.186662581 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 149707460023 ps |
| CPU time | 93.94 seconds |
| Started | Oct 14 10:16:14 PM UTC 24 |
| Finished | Oct 14 10:17:49 PM UTC 24 |
| Peak memory | 209688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186662581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.186662581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1422930800 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 5332917723 ps |
| CPU time | 30.53 seconds |
| Started | Oct 14 10:16:06 PM UTC 24 |
| Finished | Oct 14 10:16:38 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422930800 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.1422930800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2381242687 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4848415715 ps |
| CPU time | 6.89 seconds |
| Started | Oct 14 10:16:14 PM UTC 24 |
| Finished | Oct 14 10:16:22 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381242687 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.2381242687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3342738214 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2626915522 ps |
| CPU time | 3.77 seconds |
| Started | Oct 14 10:16:04 PM UTC 24 |
| Finished | Oct 14 10:16:09 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342738214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.3342738214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1741816215 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2491995944 ps |
| CPU time | 4.08 seconds |
| Started | Oct 14 10:16:00 PM UTC 24 |
| Finished | Oct 14 10:16:05 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741816215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1741816215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.356606440 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2203617914 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 10:16:01 PM UTC 24 |
| Finished | Oct 14 10:16:04 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356606440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.356606440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.2665138560 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2514335414 ps |
| CPU time | 8.28 seconds |
| Started | Oct 14 10:16:03 PM UTC 24 |
| Finished | Oct 14 10:16:13 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665138560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.2665138560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3943558008 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2114007079 ps |
| CPU time | 11.12 seconds |
| Started | Oct 14 10:15:59 PM UTC 24 |
| Finished | Oct 14 10:16:11 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943558008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3943558008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.2555686903 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 15893314194 ps |
| CPU time | 84.06 seconds |
| Started | Oct 14 10:16:19 PM UTC 24 |
| Finished | Oct 14 10:17:45 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555686903 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.2555686903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.441986610 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4043657195 ps |
| CPU time | 22.92 seconds |
| Started | Oct 14 10:16:17 PM UTC 24 |
| Finished | Oct 14 10:16:41 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=441986610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.441986610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.141252628 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 8387408334934 ps |
| CPU time | 380.94 seconds |
| Started | Oct 14 10:16:11 PM UTC 24 |
| Finished | Oct 14 10:22:37 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141252628 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.141252628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.1308435618 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2020282746 ps |
| CPU time | 5.94 seconds |
| Started | Oct 14 10:16:39 PM UTC 24 |
| Finished | Oct 14 10:16:46 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308435618 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.1308435618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1472758382 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3694485066 ps |
| CPU time | 4.65 seconds |
| Started | Oct 14 10:16:33 PM UTC 24 |
| Finished | Oct 14 10:16:38 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472758382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1472758382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.3231394391 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 73590156312 ps |
| CPU time | 61.83 seconds |
| Started | Oct 14 10:16:34 PM UTC 24 |
| Finished | Oct 14 10:17:37 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231394391 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.3231394391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2906436194 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 72192291164 ps |
| CPU time | 91.4 seconds |
| Started | Oct 14 10:16:37 PM UTC 24 |
| Finished | Oct 14 10:18:10 PM UTC 24 |
| Peak memory | 209700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906436194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.2906436194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1171747483 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5400364512 ps |
| CPU time | 7.27 seconds |
| Started | Oct 14 10:16:33 PM UTC 24 |
| Finished | Oct 14 10:16:41 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171747483 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.1171747483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1945412702 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4890098523 ps |
| CPU time | 4.7 seconds |
| Started | Oct 14 10:16:37 PM UTC 24 |
| Finished | Oct 14 10:16:43 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945412702 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.1945412702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1942242555 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2629092993 ps |
| CPU time | 4.01 seconds |
| Started | Oct 14 10:16:31 PM UTC 24 |
| Finished | Oct 14 10:16:36 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942242555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1942242555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3078493231 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2464447123 ps |
| CPU time | 3.93 seconds |
| Started | Oct 14 10:16:26 PM UTC 24 |
| Finished | Oct 14 10:16:31 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078493231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3078493231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.4169884573 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2237242320 ps |
| CPU time | 4.23 seconds |
| Started | Oct 14 10:16:27 PM UTC 24 |
| Finished | Oct 14 10:16:33 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169884573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.4169884573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.67869402 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2538044924 ps |
| CPU time | 3.58 seconds |
| Started | Oct 14 10:16:28 PM UTC 24 |
| Finished | Oct 14 10:16:33 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67869402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.67869402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.2741287577 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2130109687 ps |
| CPU time | 3.24 seconds |
| Started | Oct 14 10:16:22 PM UTC 24 |
| Finished | Oct 14 10:16:26 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741287577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2741287577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2062850789 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 134971666204 ps |
| CPU time | 189.71 seconds |
| Started | Oct 14 10:16:39 PM UTC 24 |
| Finished | Oct 14 10:19:51 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062850789 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.2062850789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.404308091 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 7206528905 ps |
| CPU time | 20.77 seconds |
| Started | Oct 14 10:16:38 PM UTC 24 |
| Finished | Oct 14 10:17:00 PM UTC 24 |
| Peak memory | 225288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=404308091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.404308091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3399631561 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 10322607952 ps |
| CPU time | 2.49 seconds |
| Started | Oct 14 10:16:34 PM UTC 24 |
| Finished | Oct 14 10:16:37 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399631561 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.3399631561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2192239587 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2023003421 ps |
| CPU time | 6.14 seconds |
| Started | Oct 14 10:12:51 PM UTC 24 |
| Finished | Oct 14 10:12:58 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192239587 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.2192239587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1528112299 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3524038824 ps |
| CPU time | 10.78 seconds |
| Started | Oct 14 10:12:43 PM UTC 24 |
| Finished | Oct 14 10:12:55 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528112299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1528112299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3027345306 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2403611588 ps |
| CPU time | 8.73 seconds |
| Started | Oct 14 10:12:40 PM UTC 24 |
| Finished | Oct 14 10:12:50 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027345306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3027345306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4265271657 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2353551126 ps |
| CPU time | 11.64 seconds |
| Started | Oct 14 10:12:40 PM UTC 24 |
| Finished | Oct 14 10:12:53 PM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265271657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4265271657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3759758627 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 25859383859 ps |
| CPU time | 18.53 seconds |
| Started | Oct 14 10:12:48 PM UTC 24 |
| Finished | Oct 14 10:13:07 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759758627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.3759758627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.145172493 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 3735233881 ps |
| CPU time | 18.63 seconds |
| Started | Oct 14 10:12:42 PM UTC 24 |
| Finished | Oct 14 10:13:02 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145172493 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.145172493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3473154789 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2617859632 ps |
| CPU time | 7.08 seconds |
| Started | Oct 14 10:12:42 PM UTC 24 |
| Finished | Oct 14 10:12:50 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473154789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3473154789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.525084165 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2101792868 ps |
| CPU time | 2.69 seconds |
| Started | Oct 14 10:12:41 PM UTC 24 |
| Finished | Oct 14 10:12:45 PM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525084165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.525084165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.1553636460 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2527819226 ps |
| CPU time | 4.25 seconds |
| Started | Oct 14 10:12:41 PM UTC 24 |
| Finished | Oct 14 10:12:46 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553636460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1553636460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.4234081971 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 22013110455 ps |
| CPU time | 73.74 seconds |
| Started | Oct 14 10:12:51 PM UTC 24 |
| Finished | Oct 14 10:14:06 PM UTC 24 |
| Peak memory | 241008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234081971 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.4234081971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.767225214 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2111264891 ps |
| CPU time | 9 seconds |
| Started | Oct 14 10:12:40 PM UTC 24 |
| Finished | Oct 14 10:12:50 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767225214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.767225214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.3729370460 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 11098488152 ps |
| CPU time | 7.44 seconds |
| Started | Oct 14 10:12:50 PM UTC 24 |
| Finished | Oct 14 10:12:58 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729370460 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.3729370460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2102582595 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5505378063 ps |
| CPU time | 12.61 seconds |
| Started | Oct 14 10:12:49 PM UTC 24 |
| Finished | Oct 14 10:13:03 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2102582595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2102582595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.4141508209 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2011573391 ps |
| CPU time | 6.94 seconds |
| Started | Oct 14 10:16:58 PM UTC 24 |
| Finished | Oct 14 10:17:06 PM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141508209 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.4141508209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1940625423 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3367809501 ps |
| CPU time | 11.51 seconds |
| Started | Oct 14 10:16:47 PM UTC 24 |
| Finished | Oct 14 10:16:59 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940625423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.1940625423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.991618653 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 168261127610 ps |
| CPU time | 240.89 seconds |
| Started | Oct 14 10:16:47 PM UTC 24 |
| Finished | Oct 14 10:20:51 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991618653 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.991618653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3768496487 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 97007166081 ps |
| CPU time | 99.45 seconds |
| Started | Oct 14 10:16:52 PM UTC 24 |
| Finished | Oct 14 10:18:34 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768496487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.3768496487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2999430546 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2734501244 ps |
| CPU time | 13.08 seconds |
| Started | Oct 14 10:16:44 PM UTC 24 |
| Finished | Oct 14 10:16:58 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999430546 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.2999430546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2601250832 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2831053100 ps |
| CPU time | 16.05 seconds |
| Started | Oct 14 10:16:49 PM UTC 24 |
| Finished | Oct 14 10:17:06 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601250832 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.2601250832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3897905880 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2625262173 ps |
| CPU time | 3.86 seconds |
| Started | Oct 14 10:16:44 PM UTC 24 |
| Finished | Oct 14 10:16:48 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897905880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.3897905880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2513952187 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2446287192 ps |
| CPU time | 13.09 seconds |
| Started | Oct 14 10:16:41 PM UTC 24 |
| Finished | Oct 14 10:16:55 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513952187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.2513952187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3759877698 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2290143548 ps |
| CPU time | 3.33 seconds |
| Started | Oct 14 10:16:41 PM UTC 24 |
| Finished | Oct 14 10:16:46 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759877698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3759877698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.4117249117 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2515087587 ps |
| CPU time | 7.07 seconds |
| Started | Oct 14 10:16:43 PM UTC 24 |
| Finished | Oct 14 10:16:52 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117249117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.4117249117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.4116431509 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2157158748 ps |
| CPU time | 1.8 seconds |
| Started | Oct 14 10:16:40 PM UTC 24 |
| Finished | Oct 14 10:16:43 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116431509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.4116431509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1327671677 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 71921285383 ps |
| CPU time | 64.15 seconds |
| Started | Oct 14 10:16:56 PM UTC 24 |
| Finished | Oct 14 10:18:02 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327671677 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.1327671677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.90861389 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 8535259892 ps |
| CPU time | 13.14 seconds |
| Started | Oct 14 10:16:47 PM UTC 24 |
| Finished | Oct 14 10:17:01 PM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90861389 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.90861389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.2266608986 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2013726445 ps |
| CPU time | 13.12 seconds |
| Started | Oct 14 10:17:13 PM UTC 24 |
| Finished | Oct 14 10:17:27 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266608986 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.2266608986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1252480450 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3702130905 ps |
| CPU time | 3.16 seconds |
| Started | Oct 14 10:17:05 PM UTC 24 |
| Finished | Oct 14 10:17:09 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252480450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1252480450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2650171213 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 3502197716 ps |
| CPU time | 11.05 seconds |
| Started | Oct 14 10:17:05 PM UTC 24 |
| Finished | Oct 14 10:17:17 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650171213 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.2650171213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.451722147 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2612186946 ps |
| CPU time | 13.55 seconds |
| Started | Oct 14 10:17:03 PM UTC 24 |
| Finished | Oct 14 10:17:18 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451722147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.451722147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.2642343329 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2491130529 ps |
| CPU time | 4.52 seconds |
| Started | Oct 14 10:17:00 PM UTC 24 |
| Finished | Oct 14 10:17:06 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642343329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2642343329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.2831242038 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2269525968 ps |
| CPU time | 6.61 seconds |
| Started | Oct 14 10:17:01 PM UTC 24 |
| Finished | Oct 14 10:17:08 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831242038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2831242038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1269785161 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2524806288 ps |
| CPU time | 4.59 seconds |
| Started | Oct 14 10:17:02 PM UTC 24 |
| Finished | Oct 14 10:17:07 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269785161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1269785161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.536459287 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2129919779 ps |
| CPU time | 3.14 seconds |
| Started | Oct 14 10:16:59 PM UTC 24 |
| Finished | Oct 14 10:17:04 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536459287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.536459287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3420429580 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 109006996460 ps |
| CPU time | 370.32 seconds |
| Started | Oct 14 10:17:10 PM UTC 24 |
| Finished | Oct 14 10:23:26 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420429580 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.3420429580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.936661170 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 10931940132 ps |
| CPU time | 8.82 seconds |
| Started | Oct 14 10:17:07 PM UTC 24 |
| Finished | Oct 14 10:17:18 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936661170 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.936661170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1060940961 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2038052514 ps |
| CPU time | 4.12 seconds |
| Started | Oct 14 10:17:31 PM UTC 24 |
| Finished | Oct 14 10:17:36 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060940961 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.1060940961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.91880092 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3529427376 ps |
| CPU time | 3.71 seconds |
| Started | Oct 14 10:17:25 PM UTC 24 |
| Finished | Oct 14 10:17:30 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91880092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.91880092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2193350247 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 65917330295 ps |
| CPU time | 246.01 seconds |
| Started | Oct 14 10:17:26 PM UTC 24 |
| Finished | Oct 14 10:21:36 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193350247 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.2193350247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.767074100 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3626693942 ps |
| CPU time | 6.65 seconds |
| Started | Oct 14 10:17:22 PM UTC 24 |
| Finished | Oct 14 10:17:30 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767074100 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.767074100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1828158173 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 3351398522 ps |
| CPU time | 2.37 seconds |
| Started | Oct 14 10:17:26 PM UTC 24 |
| Finished | Oct 14 10:17:30 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828158173 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.1828158173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1315756721 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2608329010 ps |
| CPU time | 13.59 seconds |
| Started | Oct 14 10:17:21 PM UTC 24 |
| Finished | Oct 14 10:17:36 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315756721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1315756721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3098797227 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2557966620 ps |
| CPU time | 1.8 seconds |
| Started | Oct 14 10:17:18 PM UTC 24 |
| Finished | Oct 14 10:17:21 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098797227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3098797227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1036848325 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2094003993 ps |
| CPU time | 5.61 seconds |
| Started | Oct 14 10:17:19 PM UTC 24 |
| Finished | Oct 14 10:17:26 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036848325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1036848325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1924433995 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2536902875 ps |
| CPU time | 3.76 seconds |
| Started | Oct 14 10:17:19 PM UTC 24 |
| Finished | Oct 14 10:17:24 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924433995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1924433995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1636543756 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2111597535 ps |
| CPU time | 9.07 seconds |
| Started | Oct 14 10:17:15 PM UTC 24 |
| Finished | Oct 14 10:17:25 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636543756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1636543756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.704895277 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 9536782286 ps |
| CPU time | 4.54 seconds |
| Started | Oct 14 10:17:31 PM UTC 24 |
| Finished | Oct 14 10:17:36 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704895277 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.704895277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2689240317 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 9356812732 ps |
| CPU time | 16.96 seconds |
| Started | Oct 14 10:17:31 PM UTC 24 |
| Finished | Oct 14 10:17:49 PM UTC 24 |
| Peak memory | 226224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2689240317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2689240317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3738461818 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3518548965 ps |
| CPU time | 8.03 seconds |
| Started | Oct 14 10:17:25 PM UTC 24 |
| Finished | Oct 14 10:17:35 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738461818 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.3738461818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.1503985605 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2146195575 ps |
| CPU time | 1.34 seconds |
| Started | Oct 14 10:17:50 PM UTC 24 |
| Finished | Oct 14 10:17:52 PM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503985605 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.1503985605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3198491772 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3347365278 ps |
| CPU time | 8.19 seconds |
| Started | Oct 14 10:17:41 PM UTC 24 |
| Finished | Oct 14 10:17:51 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198491772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3198491772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.1559247984 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 93958124034 ps |
| CPU time | 62.91 seconds |
| Started | Oct 14 10:17:46 PM UTC 24 |
| Finished | Oct 14 10:18:50 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559247984 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.1559247984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3922781095 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 25831488705 ps |
| CPU time | 124.36 seconds |
| Started | Oct 14 10:17:49 PM UTC 24 |
| Finished | Oct 14 10:19:55 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922781095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_with_pre_cond.3922781095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1847016874 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 4303941919 ps |
| CPU time | 26.28 seconds |
| Started | Oct 14 10:17:38 PM UTC 24 |
| Finished | Oct 14 10:18:06 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847016874 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.1847016874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.581990830 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2532719726 ps |
| CPU time | 1.7 seconds |
| Started | Oct 14 10:17:48 PM UTC 24 |
| Finished | Oct 14 10:17:50 PM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581990830 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.581990830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.680453464 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2610115873 ps |
| CPU time | 12.78 seconds |
| Started | Oct 14 10:17:38 PM UTC 24 |
| Finished | Oct 14 10:17:52 PM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680453464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.680453464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.3982115125 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2456327235 ps |
| CPU time | 9.66 seconds |
| Started | Oct 14 10:17:37 PM UTC 24 |
| Finished | Oct 14 10:17:48 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982115125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.3982115125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.3934830871 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2066812404 ps |
| CPU time | 11.13 seconds |
| Started | Oct 14 10:17:37 PM UTC 24 |
| Finished | Oct 14 10:17:49 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934830871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.3934830871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.1471223045 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2535565237 ps |
| CPU time | 4.52 seconds |
| Started | Oct 14 10:17:37 PM UTC 24 |
| Finished | Oct 14 10:17:43 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471223045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.1471223045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2324144551 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2123207905 ps |
| CPU time | 3.54 seconds |
| Started | Oct 14 10:17:36 PM UTC 24 |
| Finished | Oct 14 10:17:41 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324144551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2324144551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.215349433 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 158820980380 ps |
| CPU time | 78.54 seconds |
| Started | Oct 14 10:17:50 PM UTC 24 |
| Finished | Oct 14 10:19:10 PM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215349433 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.215349433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2135467420 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 7359806128 ps |
| CPU time | 16.9 seconds |
| Started | Oct 14 10:17:50 PM UTC 24 |
| Finished | Oct 14 10:18:08 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2135467420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2135467420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4035980084 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 12659287462 ps |
| CPU time | 6.35 seconds |
| Started | Oct 14 10:17:44 PM UTC 24 |
| Finished | Oct 14 10:17:51 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035980084 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.4035980084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.4269582845 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2029692376 ps |
| CPU time | 3.1 seconds |
| Started | Oct 14 10:18:02 PM UTC 24 |
| Finished | Oct 14 10:18:06 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269582845 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.4269582845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3629423932 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3556560993 ps |
| CPU time | 4.64 seconds |
| Started | Oct 14 10:17:55 PM UTC 24 |
| Finished | Oct 14 10:18:00 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629423932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3629423932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1393617505 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2777126000 ps |
| CPU time | 2.67 seconds |
| Started | Oct 14 10:17:54 PM UTC 24 |
| Finished | Oct 14 10:17:57 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393617505 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.1393617505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2882516856 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2632775449 ps |
| CPU time | 2.4 seconds |
| Started | Oct 14 10:17:58 PM UTC 24 |
| Finished | Oct 14 10:18:02 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882516856 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.2882516856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.602375880 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2622089404 ps |
| CPU time | 4.68 seconds |
| Started | Oct 14 10:17:54 PM UTC 24 |
| Finished | Oct 14 10:17:59 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602375880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.602375880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.481438987 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2475648754 ps |
| CPU time | 16.61 seconds |
| Started | Oct 14 10:17:51 PM UTC 24 |
| Finished | Oct 14 10:18:09 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481438987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.481438987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3777067850 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2096294796 ps |
| CPU time | 6.5 seconds |
| Started | Oct 14 10:17:51 PM UTC 24 |
| Finished | Oct 14 10:17:59 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777067850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3777067850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2040366594 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2527413453 ps |
| CPU time | 3.4 seconds |
| Started | Oct 14 10:17:52 PM UTC 24 |
| Finished | Oct 14 10:17:57 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040366594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2040366594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.3142655839 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2124291583 ps |
| CPU time | 4.72 seconds |
| Started | Oct 14 10:17:50 PM UTC 24 |
| Finished | Oct 14 10:17:56 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142655839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3142655839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2553406389 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 108887226732 ps |
| CPU time | 307.49 seconds |
| Started | Oct 14 10:18:01 PM UTC 24 |
| Finished | Oct 14 10:23:13 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553406389 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.2553406389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1592404831 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 14721453580 ps |
| CPU time | 16.1 seconds |
| Started | Oct 14 10:18:00 PM UTC 24 |
| Finished | Oct 14 10:18:17 PM UTC 24 |
| Peak memory | 217808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1592404831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1592404831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.817940580 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 9623435195 ps |
| CPU time | 7.96 seconds |
| Started | Oct 14 10:17:57 PM UTC 24 |
| Finished | Oct 14 10:18:06 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817940580 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.817940580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.3990511934 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2011904351 ps |
| CPU time | 7.84 seconds |
| Started | Oct 14 10:18:20 PM UTC 24 |
| Finished | Oct 14 10:18:29 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990511934 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.3990511934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.777766779 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 3372941528 ps |
| CPU time | 9.58 seconds |
| Started | Oct 14 10:18:09 PM UTC 24 |
| Finished | Oct 14 10:18:20 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777766779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.777766779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2274474556 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 57803123156 ps |
| CPU time | 193.3 seconds |
| Started | Oct 14 10:18:11 PM UTC 24 |
| Finished | Oct 14 10:21:27 PM UTC 24 |
| Peak memory | 209056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274474556 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.2274474556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3531148787 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3684033809 ps |
| CPU time | 5.02 seconds |
| Started | Oct 14 10:18:09 PM UTC 24 |
| Finished | Oct 14 10:18:15 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531148787 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.3531148787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1606650238 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2753500901 ps |
| CPU time | 11.98 seconds |
| Started | Oct 14 10:18:11 PM UTC 24 |
| Finished | Oct 14 10:18:24 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606650238 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.1606650238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.279249554 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2612590629 ps |
| CPU time | 10.75 seconds |
| Started | Oct 14 10:18:08 PM UTC 24 |
| Finished | Oct 14 10:18:20 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279249554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.279249554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.4287647286 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2452166831 ps |
| CPU time | 10.4 seconds |
| Started | Oct 14 10:18:04 PM UTC 24 |
| Finished | Oct 14 10:18:15 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287647286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.4287647286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.638681141 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2178273586 ps |
| CPU time | 2.71 seconds |
| Started | Oct 14 10:18:07 PM UTC 24 |
| Finished | Oct 14 10:18:10 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638681141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.638681141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.3115841911 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2510125464 ps |
| CPU time | 11.27 seconds |
| Started | Oct 14 10:18:07 PM UTC 24 |
| Finished | Oct 14 10:18:19 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115841911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3115841911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.118220849 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2123780979 ps |
| CPU time | 4.94 seconds |
| Started | Oct 14 10:18:02 PM UTC 24 |
| Finished | Oct 14 10:18:08 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118220849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.118220849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3856702171 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 372968460266 ps |
| CPU time | 36.57 seconds |
| Started | Oct 14 10:18:19 PM UTC 24 |
| Finished | Oct 14 10:18:56 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856702171 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.3856702171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3857838542 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5740203089 ps |
| CPU time | 31.23 seconds |
| Started | Oct 14 10:18:15 PM UTC 24 |
| Finished | Oct 14 10:18:48 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3857838542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.3857838542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2055355554 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2038104786 ps |
| CPU time | 3.57 seconds |
| Started | Oct 14 10:18:37 PM UTC 24 |
| Finished | Oct 14 10:18:42 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055355554 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.2055355554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1255587459 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3317760061 ps |
| CPU time | 5.4 seconds |
| Started | Oct 14 10:18:28 PM UTC 24 |
| Finished | Oct 14 10:18:35 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255587459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.1255587459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.911040515 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 143364431053 ps |
| CPU time | 258.9 seconds |
| Started | Oct 14 10:18:29 PM UTC 24 |
| Finished | Oct 14 10:22:52 PM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911040515 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.911040515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.943889211 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4212726754 ps |
| CPU time | 25.63 seconds |
| Started | Oct 14 10:18:27 PM UTC 24 |
| Finished | Oct 14 10:18:54 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943889211 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.943889211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3206521197 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2611264706 ps |
| CPU time | 9.34 seconds |
| Started | Oct 14 10:18:26 PM UTC 24 |
| Finished | Oct 14 10:18:36 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206521197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3206521197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1599405684 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2458765656 ps |
| CPU time | 3.76 seconds |
| Started | Oct 14 10:18:21 PM UTC 24 |
| Finished | Oct 14 10:18:26 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599405684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1599405684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.2223264660 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2141770453 ps |
| CPU time | 3.51 seconds |
| Started | Oct 14 10:18:23 PM UTC 24 |
| Finished | Oct 14 10:18:27 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223264660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2223264660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.1250808202 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2529834521 ps |
| CPU time | 4.54 seconds |
| Started | Oct 14 10:18:25 PM UTC 24 |
| Finished | Oct 14 10:18:31 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250808202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.1250808202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.836641904 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2117673326 ps |
| CPU time | 5.75 seconds |
| Started | Oct 14 10:18:21 PM UTC 24 |
| Finished | Oct 14 10:18:28 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836641904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.836641904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1673207046 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 74135175624 ps |
| CPU time | 51.95 seconds |
| Started | Oct 14 10:18:36 PM UTC 24 |
| Finished | Oct 14 10:19:29 PM UTC 24 |
| Peak memory | 209656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673207046 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.1673207046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1848255547 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 18834571260 ps |
| CPU time | 11.9 seconds |
| Started | Oct 14 10:18:35 PM UTC 24 |
| Finished | Oct 14 10:18:48 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1848255547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.1848255547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1291681837 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 8073627275 ps |
| CPU time | 12.27 seconds |
| Started | Oct 14 10:18:28 PM UTC 24 |
| Finished | Oct 14 10:18:42 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291681837 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.1291681837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.3198942949 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2030096326 ps |
| CPU time | 3.13 seconds |
| Started | Oct 14 10:18:53 PM UTC 24 |
| Finished | Oct 14 10:18:57 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198942949 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.3198942949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.694141852 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3340575932 ps |
| CPU time | 4.61 seconds |
| Started | Oct 14 10:18:48 PM UTC 24 |
| Finished | Oct 14 10:18:54 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694141852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.694141852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.3243926758 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 75256004911 ps |
| CPU time | 207.45 seconds |
| Started | Oct 14 10:18:51 PM UTC 24 |
| Finished | Oct 14 10:22:21 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243926758 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.3243926758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.311361390 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2436090374 ps |
| CPU time | 7.26 seconds |
| Started | Oct 14 10:18:45 PM UTC 24 |
| Finished | Oct 14 10:18:54 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311361390 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.311361390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.2022738815 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2722549078 ps |
| CPU time | 3.11 seconds |
| Started | Oct 14 10:18:51 PM UTC 24 |
| Finished | Oct 14 10:18:55 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022738815 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.2022738815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1211580419 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2613402810 ps |
| CPU time | 6.77 seconds |
| Started | Oct 14 10:18:43 PM UTC 24 |
| Finished | Oct 14 10:18:51 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211580419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.1211580419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.204736167 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2481554360 ps |
| CPU time | 8.84 seconds |
| Started | Oct 14 10:18:42 PM UTC 24 |
| Finished | Oct 14 10:18:52 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204736167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.204736167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.235926139 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2251156124 ps |
| CPU time | 8.96 seconds |
| Started | Oct 14 10:18:42 PM UTC 24 |
| Finished | Oct 14 10:18:52 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235926139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.235926139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1563452636 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2516297765 ps |
| CPU time | 7.71 seconds |
| Started | Oct 14 10:18:43 PM UTC 24 |
| Finished | Oct 14 10:18:52 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563452636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1563452636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2819490778 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2122701557 ps |
| CPU time | 3.25 seconds |
| Started | Oct 14 10:18:37 PM UTC 24 |
| Finished | Oct 14 10:18:41 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819490778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2819490778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3845698118 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 18367587674 ps |
| CPU time | 30.76 seconds |
| Started | Oct 14 10:18:53 PM UTC 24 |
| Finished | Oct 14 10:19:25 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845698118 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.3845698118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1972700261 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 430772492600 ps |
| CPU time | 29.1 seconds |
| Started | Oct 14 10:18:49 PM UTC 24 |
| Finished | Oct 14 10:19:19 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972700261 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.1972700261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2575928101 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2023832849 ps |
| CPU time | 6.93 seconds |
| Started | Oct 14 10:19:08 PM UTC 24 |
| Finished | Oct 14 10:19:16 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575928101 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.2575928101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2807531094 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3275495104 ps |
| CPU time | 10.7 seconds |
| Started | Oct 14 10:18:59 PM UTC 24 |
| Finished | Oct 14 10:19:10 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807531094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2807531094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.2159337518 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 106478821439 ps |
| CPU time | 90.31 seconds |
| Started | Oct 14 10:19:03 PM UTC 24 |
| Finished | Oct 14 10:20:35 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159337518 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.2159337518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3632171521 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2773758306 ps |
| CPU time | 7.39 seconds |
| Started | Oct 14 10:18:59 PM UTC 24 |
| Finished | Oct 14 10:19:07 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632171521 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.3632171521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.749227461 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 5663241968 ps |
| CPU time | 2.2 seconds |
| Started | Oct 14 10:19:04 PM UTC 24 |
| Finished | Oct 14 10:19:07 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749227461 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.749227461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4292159886 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2607439406 ps |
| CPU time | 11.35 seconds |
| Started | Oct 14 10:18:57 PM UTC 24 |
| Finished | Oct 14 10:19:10 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292159886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.4292159886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.3315527119 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2447277717 ps |
| CPU time | 12.21 seconds |
| Started | Oct 14 10:18:55 PM UTC 24 |
| Finished | Oct 14 10:19:09 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315527119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.3315527119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2331570645 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2109837054 ps |
| CPU time | 8.73 seconds |
| Started | Oct 14 10:18:55 PM UTC 24 |
| Finished | Oct 14 10:19:05 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331570645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2331570645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1833139733 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2536991050 ps |
| CPU time | 2.47 seconds |
| Started | Oct 14 10:18:56 PM UTC 24 |
| Finished | Oct 14 10:19:00 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833139733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1833139733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.2244220536 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2115022274 ps |
| CPU time | 10.11 seconds |
| Started | Oct 14 10:18:55 PM UTC 24 |
| Finished | Oct 14 10:19:06 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244220536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.2244220536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.2318942730 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 514348908075 ps |
| CPU time | 44.09 seconds |
| Started | Oct 14 10:19:07 PM UTC 24 |
| Finished | Oct 14 10:19:53 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318942730 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.2318942730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3607564651 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 19260505812 ps |
| CPU time | 13.61 seconds |
| Started | Oct 14 10:19:06 PM UTC 24 |
| Finished | Oct 14 10:19:21 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3607564651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3607564651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2487265131 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 12777680646 ps |
| CPU time | 20.83 seconds |
| Started | Oct 14 10:19:01 PM UTC 24 |
| Finished | Oct 14 10:19:23 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487265131 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.2487265131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.3048781372 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2009864744 ps |
| CPU time | 12.29 seconds |
| Started | Oct 14 10:19:22 PM UTC 24 |
| Finished | Oct 14 10:19:35 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048781372 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.3048781372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.4074256030 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3688656896 ps |
| CPU time | 5.4 seconds |
| Started | Oct 14 10:19:16 PM UTC 24 |
| Finished | Oct 14 10:19:22 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074256030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.4074256030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1191868667 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 102926673110 ps |
| CPU time | 281.72 seconds |
| Started | Oct 14 10:19:20 PM UTC 24 |
| Finished | Oct 14 10:24:06 PM UTC 24 |
| Peak memory | 208916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191868667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.1191868667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.4281650459 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 5019604378 ps |
| CPU time | 6.41 seconds |
| Started | Oct 14 10:19:12 PM UTC 24 |
| Finished | Oct 14 10:19:19 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281650459 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.4281650459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.984694034 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5220753411 ps |
| CPU time | 21.92 seconds |
| Started | Oct 14 10:19:20 PM UTC 24 |
| Finished | Oct 14 10:19:44 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984694034 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.984694034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3312177907 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2617778589 ps |
| CPU time | 7.11 seconds |
| Started | Oct 14 10:19:12 PM UTC 24 |
| Finished | Oct 14 10:19:20 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312177907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3312177907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.567611073 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2450093196 ps |
| CPU time | 8.66 seconds |
| Started | Oct 14 10:19:09 PM UTC 24 |
| Finished | Oct 14 10:19:19 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567611073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.567611073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1335321996 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2249521270 ps |
| CPU time | 5.94 seconds |
| Started | Oct 14 10:19:11 PM UTC 24 |
| Finished | Oct 14 10:19:18 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335321996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1335321996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.932274848 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2512016291 ps |
| CPU time | 11.9 seconds |
| Started | Oct 14 10:19:11 PM UTC 24 |
| Finished | Oct 14 10:19:24 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932274848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.932274848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.3451291651 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2178003556 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 10:19:08 PM UTC 24 |
| Finished | Oct 14 10:19:11 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451291651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3451291651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1623459347 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8544274871 ps |
| CPU time | 20.9 seconds |
| Started | Oct 14 10:19:20 PM UTC 24 |
| Finished | Oct 14 10:19:43 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623459347 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.1623459347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2312724906 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 12351747467 ps |
| CPU time | 15.38 seconds |
| Started | Oct 14 10:19:20 PM UTC 24 |
| Finished | Oct 14 10:19:37 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2312724906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2312724906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.826296859 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 4938961386 ps |
| CPU time | 12.74 seconds |
| Started | Oct 14 10:19:17 PM UTC 24 |
| Finished | Oct 14 10:19:31 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826296859 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.826296859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3868449746 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2025743280 ps |
| CPU time | 3.01 seconds |
| Started | Oct 14 10:12:59 PM UTC 24 |
| Finished | Oct 14 10:13:03 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868449746 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.3868449746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.4160343979 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3148483639 ps |
| CPU time | 9.94 seconds |
| Started | Oct 14 10:12:57 PM UTC 24 |
| Finished | Oct 14 10:13:08 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160343979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.4160343979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1656134433 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 76365902210 ps |
| CPU time | 54.38 seconds |
| Started | Oct 14 10:12:58 PM UTC 24 |
| Finished | Oct 14 10:13:54 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656134433 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.1656134433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1857055160 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2190330939 ps |
| CPU time | 10.2 seconds |
| Started | Oct 14 10:12:51 PM UTC 24 |
| Finished | Oct 14 10:13:02 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857055160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.1857055160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.440118512 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2264755704 ps |
| CPU time | 3.36 seconds |
| Started | Oct 14 10:12:52 PM UTC 24 |
| Finished | Oct 14 10:12:57 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440118512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.440118512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.555386834 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 27336128039 ps |
| CPU time | 53.11 seconds |
| Started | Oct 14 10:12:58 PM UTC 24 |
| Finished | Oct 14 10:13:53 PM UTC 24 |
| Peak memory | 209676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555386834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.555386834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2728427613 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3700614502 ps |
| CPU time | 14.02 seconds |
| Started | Oct 14 10:12:56 PM UTC 24 |
| Finished | Oct 14 10:13:12 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728427613 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.2728427613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2183263139 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6010816914 ps |
| CPU time | 6.03 seconds |
| Started | Oct 14 10:12:58 PM UTC 24 |
| Finished | Oct 14 10:13:05 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183263139 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.2183263139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.146808423 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2627532541 ps |
| CPU time | 3.15 seconds |
| Started | Oct 14 10:12:54 PM UTC 24 |
| Finished | Oct 14 10:12:59 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146808423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.146808423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1830945974 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2469922330 ps |
| CPU time | 7.41 seconds |
| Started | Oct 14 10:12:51 PM UTC 24 |
| Finished | Oct 14 10:12:59 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830945974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1830945974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2963063883 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2239713994 ps |
| CPU time | 2.39 seconds |
| Started | Oct 14 10:12:53 PM UTC 24 |
| Finished | Oct 14 10:12:57 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963063883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2963063883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2151420771 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2534104741 ps |
| CPU time | 3.5 seconds |
| Started | Oct 14 10:12:53 PM UTC 24 |
| Finished | Oct 14 10:12:58 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151420771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2151420771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3036787657 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 42116472151 ps |
| CPU time | 53.62 seconds |
| Started | Oct 14 10:12:59 PM UTC 24 |
| Finished | Oct 14 10:13:55 PM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036787657 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3036787657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.267962339 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2111831888 ps |
| CPU time | 10.06 seconds |
| Started | Oct 14 10:12:51 PM UTC 24 |
| Finished | Oct 14 10:13:02 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267962339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.267962339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.2954241050 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 179374658377 ps |
| CPU time | 513.24 seconds |
| Started | Oct 14 10:12:59 PM UTC 24 |
| Finished | Oct 14 10:21:38 PM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954241050 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.2954241050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.701072507 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3747383246 ps |
| CPU time | 10.23 seconds |
| Started | Oct 14 10:12:59 PM UTC 24 |
| Finished | Oct 14 10:13:10 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=701072507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.701072507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.502239188 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4762002061 ps |
| CPU time | 5.26 seconds |
| Started | Oct 14 10:12:58 PM UTC 24 |
| Finished | Oct 14 10:13:05 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502239188 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.502239188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3810325525 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2020730086 ps |
| CPU time | 6.06 seconds |
| Started | Oct 14 10:19:37 PM UTC 24 |
| Finished | Oct 14 10:19:44 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810325525 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.3810325525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3782572752 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3368336432 ps |
| CPU time | 1.97 seconds |
| Started | Oct 14 10:19:30 PM UTC 24 |
| Finished | Oct 14 10:19:33 PM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782572752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.3782572752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.1629757450 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 200601833344 ps |
| CPU time | 357.05 seconds |
| Started | Oct 14 10:19:31 PM UTC 24 |
| Finished | Oct 14 10:25:33 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629757450 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.1629757450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1090423210 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 37026307118 ps |
| CPU time | 31.82 seconds |
| Started | Oct 14 10:19:35 PM UTC 24 |
| Finished | Oct 14 10:20:08 PM UTC 24 |
| Peak memory | 209820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090423210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.1090423210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2154752891 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 3198289969 ps |
| CPU time | 8.18 seconds |
| Started | Oct 14 10:19:29 PM UTC 24 |
| Finished | Oct 14 10:19:38 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154752891 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.2154752891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1126752764 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3241795647 ps |
| CPU time | 3.23 seconds |
| Started | Oct 14 10:19:32 PM UTC 24 |
| Finished | Oct 14 10:19:37 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126752764 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.1126752764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.208891474 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2609530829 ps |
| CPU time | 7.33 seconds |
| Started | Oct 14 10:19:27 PM UTC 24 |
| Finished | Oct 14 10:19:36 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208891474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.208891474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.124546670 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2477844836 ps |
| CPU time | 12.36 seconds |
| Started | Oct 14 10:19:24 PM UTC 24 |
| Finished | Oct 14 10:19:37 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124546670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.124546670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.3428724647 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2044871603 ps |
| CPU time | 3.04 seconds |
| Started | Oct 14 10:19:25 PM UTC 24 |
| Finished | Oct 14 10:19:29 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428724647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3428724647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.1267829967 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2531613541 ps |
| CPU time | 4.26 seconds |
| Started | Oct 14 10:19:26 PM UTC 24 |
| Finished | Oct 14 10:19:31 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267829967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1267829967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1790594452 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2124351041 ps |
| CPU time | 3.18 seconds |
| Started | Oct 14 10:19:24 PM UTC 24 |
| Finished | Oct 14 10:19:28 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790594452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1790594452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.2061749107 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 91244566664 ps |
| CPU time | 62 seconds |
| Started | Oct 14 10:19:36 PM UTC 24 |
| Finished | Oct 14 10:20:39 PM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061749107 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.2061749107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.108452106 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 4200893441 ps |
| CPU time | 18.33 seconds |
| Started | Oct 14 10:19:35 PM UTC 24 |
| Finished | Oct 14 10:19:54 PM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=108452106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.108452106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.104480240 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 779178497102 ps |
| CPU time | 69.04 seconds |
| Started | Oct 14 10:19:30 PM UTC 24 |
| Finished | Oct 14 10:20:41 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104480240 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.104480240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1279870530 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2101916603 ps |
| CPU time | 1.84 seconds |
| Started | Oct 14 10:19:53 PM UTC 24 |
| Finished | Oct 14 10:19:56 PM UTC 24 |
| Peak memory | 207136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279870530 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.1279870530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.4278459935 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2876079036 ps |
| CPU time | 6.12 seconds |
| Started | Oct 14 10:19:43 PM UTC 24 |
| Finished | Oct 14 10:19:51 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278459935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.4278459935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.2441137791 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 102323391222 ps |
| CPU time | 149.09 seconds |
| Started | Oct 14 10:19:45 PM UTC 24 |
| Finished | Oct 14 10:22:16 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441137791 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.2441137791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3881628722 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3223334768 ps |
| CPU time | 3.21 seconds |
| Started | Oct 14 10:19:43 PM UTC 24 |
| Finished | Oct 14 10:19:48 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881628722 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.3881628722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3720802883 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3298333651 ps |
| CPU time | 3.06 seconds |
| Started | Oct 14 10:19:49 PM UTC 24 |
| Finished | Oct 14 10:19:53 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720802883 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.3720802883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1403822498 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2611906194 ps |
| CPU time | 6.97 seconds |
| Started | Oct 14 10:19:42 PM UTC 24 |
| Finished | Oct 14 10:19:50 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403822498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.1403822498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.893503880 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2469967947 ps |
| CPU time | 12.83 seconds |
| Started | Oct 14 10:19:38 PM UTC 24 |
| Finished | Oct 14 10:19:52 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893503880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.893503880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.3665596826 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2139435278 ps |
| CPU time | 3.89 seconds |
| Started | Oct 14 10:19:38 PM UTC 24 |
| Finished | Oct 14 10:19:43 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665596826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3665596826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.193193035 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2513457373 ps |
| CPU time | 14.5 seconds |
| Started | Oct 14 10:19:39 PM UTC 24 |
| Finished | Oct 14 10:19:55 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193193035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.193193035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.1821853316 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2172894702 ps |
| CPU time | 2.19 seconds |
| Started | Oct 14 10:19:38 PM UTC 24 |
| Finished | Oct 14 10:19:41 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821853316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.1821853316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.3242166457 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 14171140768 ps |
| CPU time | 66.95 seconds |
| Started | Oct 14 10:19:52 PM UTC 24 |
| Finished | Oct 14 10:21:01 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242166457 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.3242166457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.521506684 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3647461886 ps |
| CPU time | 12.38 seconds |
| Started | Oct 14 10:19:52 PM UTC 24 |
| Finished | Oct 14 10:20:05 PM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=521506684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.521506684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2730168644 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 4376298561 ps |
| CPU time | 13.01 seconds |
| Started | Oct 14 10:19:45 PM UTC 24 |
| Finished | Oct 14 10:19:59 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730168644 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.2730168644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.2143237241 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2018546493 ps |
| CPU time | 6.4 seconds |
| Started | Oct 14 10:20:06 PM UTC 24 |
| Finished | Oct 14 10:20:14 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143237241 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.2143237241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3827608009 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3514527999 ps |
| CPU time | 8.13 seconds |
| Started | Oct 14 10:19:59 PM UTC 24 |
| Finished | Oct 14 10:20:09 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827608009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3827608009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.1828680341 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 62467280701 ps |
| CPU time | 201.27 seconds |
| Started | Oct 14 10:20:00 PM UTC 24 |
| Finished | Oct 14 10:23:25 PM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828680341 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.1828680341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.564079432 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1089615449738 ps |
| CPU time | 3096.42 seconds |
| Started | Oct 14 10:19:58 PM UTC 24 |
| Finished | Oct 14 11:12:01 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564079432 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.564079432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3343952237 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2882736647 ps |
| CPU time | 4.39 seconds |
| Started | Oct 14 10:20:01 PM UTC 24 |
| Finished | Oct 14 10:20:07 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343952237 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.3343952237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3665825079 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2624232456 ps |
| CPU time | 4.08 seconds |
| Started | Oct 14 10:19:56 PM UTC 24 |
| Finished | Oct 14 10:20:02 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665825079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3665825079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.1180268490 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2467042466 ps |
| CPU time | 4.38 seconds |
| Started | Oct 14 10:19:53 PM UTC 24 |
| Finished | Oct 14 10:19:59 PM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180268490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1180268490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2182863228 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2190249756 ps |
| CPU time | 10.41 seconds |
| Started | Oct 14 10:19:55 PM UTC 24 |
| Finished | Oct 14 10:20:07 PM UTC 24 |
| Peak memory | 209164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182863228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.2182863228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2528252318 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2531135239 ps |
| CPU time | 4.08 seconds |
| Started | Oct 14 10:19:55 PM UTC 24 |
| Finished | Oct 14 10:20:01 PM UTC 24 |
| Peak memory | 209172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528252318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2528252318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.200259590 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2131389463 ps |
| CPU time | 3.86 seconds |
| Started | Oct 14 10:19:53 PM UTC 24 |
| Finished | Oct 14 10:19:58 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200259590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.200259590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.406120646 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 13556450527 ps |
| CPU time | 2.97 seconds |
| Started | Oct 14 10:20:06 PM UTC 24 |
| Finished | Oct 14 10:20:10 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406120646 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.406120646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3435852250 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 6963967830 ps |
| CPU time | 19.91 seconds |
| Started | Oct 14 10:20:04 PM UTC 24 |
| Finished | Oct 14 10:20:25 PM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3435852250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3435852250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1733903518 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 3740824116 ps |
| CPU time | 4.03 seconds |
| Started | Oct 14 10:20:00 PM UTC 24 |
| Finished | Oct 14 10:20:06 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733903518 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.1733903518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.1752037127 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2030898661 ps |
| CPU time | 3.29 seconds |
| Started | Oct 14 10:20:25 PM UTC 24 |
| Finished | Oct 14 10:20:29 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752037127 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.1752037127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1527967183 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3413793149 ps |
| CPU time | 15.51 seconds |
| Started | Oct 14 10:20:18 PM UTC 24 |
| Finished | Oct 14 10:20:35 PM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527967183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1527967183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1613799544 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 74475044905 ps |
| CPU time | 125.41 seconds |
| Started | Oct 14 10:20:22 PM UTC 24 |
| Finished | Oct 14 10:22:30 PM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613799544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.1613799544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3297714706 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 4275929793 ps |
| CPU time | 5.63 seconds |
| Started | Oct 14 10:20:15 PM UTC 24 |
| Finished | Oct 14 10:20:22 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297714706 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.3297714706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.1200354858 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 835421349107 ps |
| CPU time | 2732.21 seconds |
| Started | Oct 14 10:20:22 PM UTC 24 |
| Finished | Oct 14 11:06:20 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200354858 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.1200354858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3861220682 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 2609141385 ps |
| CPU time | 11.84 seconds |
| Started | Oct 14 10:20:11 PM UTC 24 |
| Finished | Oct 14 10:20:24 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861220682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3861220682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3202170830 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2461042404 ps |
| CPU time | 8.98 seconds |
| Started | Oct 14 10:20:08 PM UTC 24 |
| Finished | Oct 14 10:20:18 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202170830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3202170830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2005802020 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2132524932 ps |
| CPU time | 11.9 seconds |
| Started | Oct 14 10:20:09 PM UTC 24 |
| Finished | Oct 14 10:20:22 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005802020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.2005802020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3408155660 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2518682147 ps |
| CPU time | 6.83 seconds |
| Started | Oct 14 10:20:10 PM UTC 24 |
| Finished | Oct 14 10:20:18 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408155660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3408155660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.829494471 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2108787644 ps |
| CPU time | 9.33 seconds |
| Started | Oct 14 10:20:08 PM UTC 24 |
| Finished | Oct 14 10:20:18 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829494471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.829494471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.2324293197 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 428655781868 ps |
| CPU time | 160.8 seconds |
| Started | Oct 14 10:20:25 PM UTC 24 |
| Finished | Oct 14 10:23:08 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324293197 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.2324293197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1018659428 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 8444128680 ps |
| CPU time | 9.5 seconds |
| Started | Oct 14 10:20:18 PM UTC 24 |
| Finished | Oct 14 10:20:29 PM UTC 24 |
| Peak memory | 209068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018659428 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.1018659428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2143065523 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2034477623 ps |
| CPU time | 3.66 seconds |
| Started | Oct 14 10:20:40 PM UTC 24 |
| Finished | Oct 14 10:20:45 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143065523 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.2143065523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2126784728 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3383255011 ps |
| CPU time | 3.78 seconds |
| Started | Oct 14 10:20:34 PM UTC 24 |
| Finished | Oct 14 10:20:39 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126784728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2126784728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1097342005 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 156346117797 ps |
| CPU time | 454.31 seconds |
| Started | Oct 14 10:20:35 PM UTC 24 |
| Finished | Oct 14 10:28:15 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097342005 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.1097342005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2201373341 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 40673436453 ps |
| CPU time | 15.19 seconds |
| Started | Oct 14 10:20:37 PM UTC 24 |
| Finished | Oct 14 10:20:53 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201373341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.2201373341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1184054727 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 3612697826 ps |
| CPU time | 4.75 seconds |
| Started | Oct 14 10:20:33 PM UTC 24 |
| Finished | Oct 14 10:20:39 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184054727 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.1184054727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.235315573 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4720693977 ps |
| CPU time | 16.62 seconds |
| Started | Oct 14 10:20:35 PM UTC 24 |
| Finished | Oct 14 10:20:53 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235315573 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.235315573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3720349695 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2637683561 ps |
| CPU time | 3.17 seconds |
| Started | Oct 14 10:20:31 PM UTC 24 |
| Finished | Oct 14 10:20:35 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720349695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3720349695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.220679675 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2475418493 ps |
| CPU time | 4.81 seconds |
| Started | Oct 14 10:20:27 PM UTC 24 |
| Finished | Oct 14 10:20:33 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220679675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.220679675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.4077349169 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2267391876 ps |
| CPU time | 2.63 seconds |
| Started | Oct 14 10:20:30 PM UTC 24 |
| Finished | Oct 14 10:20:34 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077349169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.4077349169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2516258182 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2511004255 ps |
| CPU time | 7.7 seconds |
| Started | Oct 14 10:20:30 PM UTC 24 |
| Finished | Oct 14 10:20:39 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516258182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.2516258182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3429805798 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2111793216 ps |
| CPU time | 11.04 seconds |
| Started | Oct 14 10:20:26 PM UTC 24 |
| Finished | Oct 14 10:20:38 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429805798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3429805798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3888160254 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 46249654215 ps |
| CPU time | 123.74 seconds |
| Started | Oct 14 10:20:40 PM UTC 24 |
| Finished | Oct 14 10:22:46 PM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888160254 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.3888160254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.4018667488 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4271010174 ps |
| CPU time | 16.61 seconds |
| Started | Oct 14 10:20:39 PM UTC 24 |
| Finished | Oct 14 10:20:56 PM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4018667488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.4018667488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2964071029 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6061700187 ps |
| CPU time | 11.54 seconds |
| Started | Oct 14 10:20:34 PM UTC 24 |
| Finished | Oct 14 10:20:47 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964071029 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.2964071029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.897491934 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2009755279 ps |
| CPU time | 8.85 seconds |
| Started | Oct 14 10:20:52 PM UTC 24 |
| Finished | Oct 14 10:21:02 PM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897491934 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.897491934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.863205913 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3376491823 ps |
| CPU time | 4.53 seconds |
| Started | Oct 14 10:20:45 PM UTC 24 |
| Finished | Oct 14 10:20:51 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863205913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.863205913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2813567467 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 32292760321 ps |
| CPU time | 11.16 seconds |
| Started | Oct 14 10:20:48 PM UTC 24 |
| Finished | Oct 14 10:21:00 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813567467 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.2813567467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2880503337 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 3672925652 ps |
| CPU time | 4.77 seconds |
| Started | Oct 14 10:20:44 PM UTC 24 |
| Finished | Oct 14 10:20:50 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880503337 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.2880503337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2023423568 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 4019004475 ps |
| CPU time | 6.05 seconds |
| Started | Oct 14 10:20:48 PM UTC 24 |
| Finished | Oct 14 10:20:55 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023423568 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.2023423568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1985411140 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2633065635 ps |
| CPU time | 4.21 seconds |
| Started | Oct 14 10:20:42 PM UTC 24 |
| Finished | Oct 14 10:20:47 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985411140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.1985411140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.3250073846 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2451974129 ps |
| CPU time | 14.09 seconds |
| Started | Oct 14 10:20:40 PM UTC 24 |
| Finished | Oct 14 10:20:55 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250073846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.3250073846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.94584762 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2142526387 ps |
| CPU time | 10.42 seconds |
| Started | Oct 14 10:20:40 PM UTC 24 |
| Finished | Oct 14 10:20:52 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94584762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.94584762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.3623906994 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2520796056 ps |
| CPU time | 4.65 seconds |
| Started | Oct 14 10:20:41 PM UTC 24 |
| Finished | Oct 14 10:20:47 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623906994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.3623906994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.1032602835 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2120647649 ps |
| CPU time | 3.6 seconds |
| Started | Oct 14 10:20:40 PM UTC 24 |
| Finished | Oct 14 10:20:45 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032602835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.1032602835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.112788531 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 71311373992 ps |
| CPU time | 190.04 seconds |
| Started | Oct 14 10:20:51 PM UTC 24 |
| Finished | Oct 14 10:24:04 PM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112788531 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.112788531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2840131282 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 9597999134 ps |
| CPU time | 26.86 seconds |
| Started | Oct 14 10:20:50 PM UTC 24 |
| Finished | Oct 14 10:21:18 PM UTC 24 |
| Peak memory | 217872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2840131282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.2840131282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.1283925837 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2017980603 ps |
| CPU time | 7.33 seconds |
| Started | Oct 14 10:21:01 PM UTC 24 |
| Finished | Oct 14 10:21:10 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283925837 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.1283925837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2855235422 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3861443070 ps |
| CPU time | 4.77 seconds |
| Started | Oct 14 10:20:58 PM UTC 24 |
| Finished | Oct 14 10:21:04 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855235422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.2855235422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.1322705159 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 49473436757 ps |
| CPU time | 144.91 seconds |
| Started | Oct 14 10:20:58 PM UTC 24 |
| Finished | Oct 14 10:23:25 PM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322705159 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.1322705159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2535998027 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 35109625278 ps |
| CPU time | 27.76 seconds |
| Started | Oct 14 10:21:00 PM UTC 24 |
| Finished | Oct 14 10:21:29 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535998027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.2535998027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3972142424 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4663012182 ps |
| CPU time | 6.39 seconds |
| Started | Oct 14 10:20:56 PM UTC 24 |
| Finished | Oct 14 10:21:03 PM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972142424 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.3972142424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3703328156 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2699001810 ps |
| CPU time | 12.41 seconds |
| Started | Oct 14 10:21:00 PM UTC 24 |
| Finished | Oct 14 10:21:14 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703328156 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.3703328156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.4016845484 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2612387503 ps |
| CPU time | 12.92 seconds |
| Started | Oct 14 10:20:56 PM UTC 24 |
| Finished | Oct 14 10:21:10 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016845484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.4016845484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3999225013 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2477099194 ps |
| CPU time | 5.69 seconds |
| Started | Oct 14 10:20:52 PM UTC 24 |
| Finished | Oct 14 10:20:59 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999225013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3999225013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.2596372379 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2108259424 ps |
| CPU time | 2.48 seconds |
| Started | Oct 14 10:20:53 PM UTC 24 |
| Finished | Oct 14 10:20:57 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596372379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2596372379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3040264624 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2512016625 ps |
| CPU time | 10.64 seconds |
| Started | Oct 14 10:20:54 PM UTC 24 |
| Finished | Oct 14 10:21:06 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040264624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3040264624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.4148697982 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2110712267 ps |
| CPU time | 7.28 seconds |
| Started | Oct 14 10:20:52 PM UTC 24 |
| Finished | Oct 14 10:21:01 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148697982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.4148697982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.3911274006 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 64671778378 ps |
| CPU time | 181.68 seconds |
| Started | Oct 14 10:21:01 PM UTC 24 |
| Finished | Oct 14 10:24:06 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911274006 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.3911274006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1410634320 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 5383117814 ps |
| CPU time | 9.36 seconds |
| Started | Oct 14 10:21:00 PM UTC 24 |
| Finished | Oct 14 10:21:11 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1410634320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.1410634320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.4090379533 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 6643079639 ps |
| CPU time | 5.04 seconds |
| Started | Oct 14 10:20:58 PM UTC 24 |
| Finished | Oct 14 10:21:04 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090379533 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.4090379533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.1938158993 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2042695718 ps |
| CPU time | 3.15 seconds |
| Started | Oct 14 10:21:12 PM UTC 24 |
| Finished | Oct 14 10:21:16 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938158993 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.1938158993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3068270194 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 2995827614 ps |
| CPU time | 16.66 seconds |
| Started | Oct 14 10:21:07 PM UTC 24 |
| Finished | Oct 14 10:21:25 PM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068270194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3068270194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.601671877 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 121882549401 ps |
| CPU time | 194.87 seconds |
| Started | Oct 14 10:21:10 PM UTC 24 |
| Finished | Oct 14 10:24:28 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601671877 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.601671877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.61007107 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2888373888 ps |
| CPU time | 2.1 seconds |
| Started | Oct 14 10:21:06 PM UTC 24 |
| Finished | Oct 14 10:21:09 PM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61007107 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.61007107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.734295545 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2957184173 ps |
| CPU time | 4.83 seconds |
| Started | Oct 14 10:21:10 PM UTC 24 |
| Finished | Oct 14 10:21:16 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734295545 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.734295545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.4167658570 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2614841140 ps |
| CPU time | 11.39 seconds |
| Started | Oct 14 10:21:05 PM UTC 24 |
| Finished | Oct 14 10:21:17 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167658570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.4167658570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1739901502 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2475929773 ps |
| CPU time | 6.85 seconds |
| Started | Oct 14 10:21:03 PM UTC 24 |
| Finished | Oct 14 10:21:11 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739901502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1739901502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.4209044724 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2069684509 ps |
| CPU time | 4.08 seconds |
| Started | Oct 14 10:21:04 PM UTC 24 |
| Finished | Oct 14 10:21:09 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209044724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.4209044724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.3473062373 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2531647100 ps |
| CPU time | 3.79 seconds |
| Started | Oct 14 10:21:05 PM UTC 24 |
| Finished | Oct 14 10:21:10 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473062373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3473062373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2263410887 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2129201465 ps |
| CPU time | 2.6 seconds |
| Started | Oct 14 10:21:01 PM UTC 24 |
| Finished | Oct 14 10:21:05 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263410887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.2263410887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1952947844 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 21056993275 ps |
| CPU time | 20.34 seconds |
| Started | Oct 14 10:21:10 PM UTC 24 |
| Finished | Oct 14 10:21:32 PM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1952947844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1952947844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.534596038 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3711819973 ps |
| CPU time | 4.29 seconds |
| Started | Oct 14 10:21:09 PM UTC 24 |
| Finished | Oct 14 10:21:14 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534596038 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.534596038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3539003653 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2011527142 ps |
| CPU time | 9.93 seconds |
| Started | Oct 14 10:21:31 PM UTC 24 |
| Finished | Oct 14 10:21:42 PM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539003653 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.3539003653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2214005246 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3357472720 ps |
| CPU time | 4.04 seconds |
| Started | Oct 14 10:21:21 PM UTC 24 |
| Finished | Oct 14 10:21:26 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214005246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2214005246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.1016807012 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 85965013039 ps |
| CPU time | 49.37 seconds |
| Started | Oct 14 10:21:26 PM UTC 24 |
| Finished | Oct 14 10:22:18 PM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016807012 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.1016807012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3679579238 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 95264065191 ps |
| CPU time | 100.42 seconds |
| Started | Oct 14 10:21:28 PM UTC 24 |
| Finished | Oct 14 10:23:10 PM UTC 24 |
| Peak memory | 209736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679579238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.3679579238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.818864878 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 4904743012 ps |
| CPU time | 21.76 seconds |
| Started | Oct 14 10:21:19 PM UTC 24 |
| Finished | Oct 14 10:21:42 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818864878 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.818864878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.390322606 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2619063623 ps |
| CPU time | 7.01 seconds |
| Started | Oct 14 10:21:18 PM UTC 24 |
| Finished | Oct 14 10:21:26 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390322606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.390322606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.516402994 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2480786282 ps |
| CPU time | 3.83 seconds |
| Started | Oct 14 10:21:16 PM UTC 24 |
| Finished | Oct 14 10:21:21 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516402994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.516402994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3486078968 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2050522010 ps |
| CPU time | 11.84 seconds |
| Started | Oct 14 10:21:17 PM UTC 24 |
| Finished | Oct 14 10:21:30 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486078968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3486078968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1553783975 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2512637612 ps |
| CPU time | 12.34 seconds |
| Started | Oct 14 10:21:17 PM UTC 24 |
| Finished | Oct 14 10:21:30 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553783975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1553783975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.1127442228 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2111111704 ps |
| CPU time | 9.27 seconds |
| Started | Oct 14 10:21:15 PM UTC 24 |
| Finished | Oct 14 10:21:25 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127442228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1127442228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.346435551 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 66051554633 ps |
| CPU time | 237.32 seconds |
| Started | Oct 14 10:21:30 PM UTC 24 |
| Finished | Oct 14 10:25:31 PM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346435551 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.346435551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2214201653 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 13901070511 ps |
| CPU time | 13.02 seconds |
| Started | Oct 14 10:21:29 PM UTC 24 |
| Finished | Oct 14 10:21:43 PM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2214201653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.2214201653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2571169256 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2646214642 ps |
| CPU time | 5.05 seconds |
| Started | Oct 14 10:21:25 PM UTC 24 |
| Finished | Oct 14 10:21:32 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571169256 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.2571169256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.3855921688 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2013217221 ps |
| CPU time | 11.55 seconds |
| Started | Oct 14 10:21:45 PM UTC 24 |
| Finished | Oct 14 10:21:58 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855921688 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.3855921688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.523638692 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3163785757 ps |
| CPU time | 5.61 seconds |
| Started | Oct 14 10:21:40 PM UTC 24 |
| Finished | Oct 14 10:21:46 PM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523638692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.523638692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.957091352 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 136751062774 ps |
| CPU time | 508.26 seconds |
| Started | Oct 14 10:21:41 PM UTC 24 |
| Finished | Oct 14 10:30:15 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957091352 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.957091352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.5574737 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 22832442013 ps |
| CPU time | 84.69 seconds |
| Started | Oct 14 10:21:43 PM UTC 24 |
| Finished | Oct 14 10:23:10 PM UTC 24 |
| Peak memory | 209356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5574737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_ TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.5574737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2335954429 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2885340656 ps |
| CPU time | 11.16 seconds |
| Started | Oct 14 10:21:39 PM UTC 24 |
| Finished | Oct 14 10:21:52 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335954429 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.2335954429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.1274632360 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3373038199 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 10:21:41 PM UTC 24 |
| Finished | Oct 14 10:21:43 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274632360 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.1274632360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1903004274 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2619836562 ps |
| CPU time | 6.06 seconds |
| Started | Oct 14 10:21:36 PM UTC 24 |
| Finished | Oct 14 10:21:44 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903004274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1903004274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3541658380 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2463032904 ps |
| CPU time | 11.96 seconds |
| Started | Oct 14 10:21:32 PM UTC 24 |
| Finished | Oct 14 10:21:46 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541658380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3541658380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.328462967 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2132753091 ps |
| CPU time | 3.83 seconds |
| Started | Oct 14 10:21:33 PM UTC 24 |
| Finished | Oct 14 10:21:38 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328462967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.328462967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.2568230467 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2512674664 ps |
| CPU time | 10.83 seconds |
| Started | Oct 14 10:21:33 PM UTC 24 |
| Finished | Oct 14 10:21:45 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568230467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.2568230467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2575710018 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2118812007 ps |
| CPU time | 6.79 seconds |
| Started | Oct 14 10:21:31 PM UTC 24 |
| Finished | Oct 14 10:21:40 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575710018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.2575710018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1101938405 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3164409347 ps |
| CPU time | 10.34 seconds |
| Started | Oct 14 10:21:43 PM UTC 24 |
| Finished | Oct 14 10:21:55 PM UTC 24 |
| Peak memory | 208996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1101938405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.1101938405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1051193855 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 9982931618 ps |
| CPU time | 14.48 seconds |
| Started | Oct 14 10:21:40 PM UTC 24 |
| Finished | Oct 14 10:21:55 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051193855 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.1051193855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.2808573590 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2047877398 ps |
| CPU time | 3.25 seconds |
| Started | Oct 14 10:13:06 PM UTC 24 |
| Finished | Oct 14 10:13:11 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808573590 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.2808573590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3714459768 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3450920961 ps |
| CPU time | 13.87 seconds |
| Started | Oct 14 10:13:03 PM UTC 24 |
| Finished | Oct 14 10:13:18 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714459768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3714459768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3209741852 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 77378223291 ps |
| CPU time | 213.77 seconds |
| Started | Oct 14 10:13:03 PM UTC 24 |
| Finished | Oct 14 10:16:40 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209741852 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.3209741852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.4247018035 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2415986927 ps |
| CPU time | 3.21 seconds |
| Started | Oct 14 10:13:00 PM UTC 24 |
| Finished | Oct 14 10:13:05 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247018035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.4247018035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3661949844 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2307297525 ps |
| CPU time | 2.52 seconds |
| Started | Oct 14 10:13:00 PM UTC 24 |
| Finished | Oct 14 10:13:04 PM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661949844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3661949844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.165097832 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2992674724 ps |
| CPU time | 5.47 seconds |
| Started | Oct 14 10:13:03 PM UTC 24 |
| Finished | Oct 14 10:13:09 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165097832 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.165097832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.64989996 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2616396644 ps |
| CPU time | 4.45 seconds |
| Started | Oct 14 10:13:02 PM UTC 24 |
| Finished | Oct 14 10:13:07 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64989996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.64989996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1155553927 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2473626807 ps |
| CPU time | 6.91 seconds |
| Started | Oct 14 10:13:00 PM UTC 24 |
| Finished | Oct 14 10:13:08 PM UTC 24 |
| Peak memory | 209204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155553927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1155553927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.1177304343 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2249772742 ps |
| CPU time | 5.09 seconds |
| Started | Oct 14 10:13:02 PM UTC 24 |
| Finished | Oct 14 10:13:08 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177304343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1177304343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.3011985396 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2530818558 ps |
| CPU time | 4 seconds |
| Started | Oct 14 10:13:02 PM UTC 24 |
| Finished | Oct 14 10:13:07 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011985396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3011985396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.2052019562 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 42015388463 ps |
| CPU time | 68.82 seconds |
| Started | Oct 14 10:13:05 PM UTC 24 |
| Finished | Oct 14 10:14:16 PM UTC 24 |
| Peak memory | 241292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052019562 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.2052019562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1284530329 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2114925000 ps |
| CPU time | 3.92 seconds |
| Started | Oct 14 10:13:00 PM UTC 24 |
| Finished | Oct 14 10:13:05 PM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284530329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1284530329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3734119544 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 7936465163 ps |
| CPU time | 25.51 seconds |
| Started | Oct 14 10:13:05 PM UTC 24 |
| Finished | Oct 14 10:13:32 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734119544 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.3734119544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.537874191 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3222420878 ps |
| CPU time | 15.4 seconds |
| Started | Oct 14 10:13:05 PM UTC 24 |
| Finished | Oct 14 10:13:22 PM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=537874191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.537874191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3176922494 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 10587709142 ps |
| CPU time | 4 seconds |
| Started | Oct 14 10:13:03 PM UTC 24 |
| Finished | Oct 14 10:13:08 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176922494 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.3176922494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.108397725 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2011858683 ps |
| CPU time | 9.91 seconds |
| Started | Oct 14 10:21:54 PM UTC 24 |
| Finished | Oct 14 10:22:05 PM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108397725 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.108397725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2590941539 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3283514088 ps |
| CPU time | 7.05 seconds |
| Started | Oct 14 10:21:49 PM UTC 24 |
| Finished | Oct 14 10:21:57 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590941539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.2590941539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.2421325164 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 81800674810 ps |
| CPU time | 239.59 seconds |
| Started | Oct 14 10:21:53 PM UTC 24 |
| Finished | Oct 14 10:25:56 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421325164 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.2421325164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.27589181 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2596959069 ps |
| CPU time | 3.42 seconds |
| Started | Oct 14 10:21:47 PM UTC 24 |
| Finished | Oct 14 10:21:51 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27589181 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.27589181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.3894239675 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3239582903 ps |
| CPU time | 11.63 seconds |
| Started | Oct 14 10:21:53 PM UTC 24 |
| Finished | Oct 14 10:22:06 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894239675 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.3894239675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3725484854 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2611504763 ps |
| CPU time | 13.98 seconds |
| Started | Oct 14 10:21:47 PM UTC 24 |
| Finished | Oct 14 10:22:02 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725484854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3725484854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3408206576 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2505644241 ps |
| CPU time | 3.32 seconds |
| Started | Oct 14 10:21:45 PM UTC 24 |
| Finished | Oct 14 10:21:50 PM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408206576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3408206576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.4146581963 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2177015421 ps |
| CPU time | 3.62 seconds |
| Started | Oct 14 10:21:47 PM UTC 24 |
| Finished | Oct 14 10:21:51 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146581963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.4146581963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.568398253 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2537119562 ps |
| CPU time | 2.88 seconds |
| Started | Oct 14 10:21:47 PM UTC 24 |
| Finished | Oct 14 10:21:51 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568398253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.568398253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.2805006092 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2116939795 ps |
| CPU time | 6.61 seconds |
| Started | Oct 14 10:21:45 PM UTC 24 |
| Finished | Oct 14 10:21:53 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805006092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2805006092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.3116194846 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 59894040030 ps |
| CPU time | 118.87 seconds |
| Started | Oct 14 10:21:54 PM UTC 24 |
| Finished | Oct 14 10:23:55 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116194846 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.3116194846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.4044214789 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 3747775112 ps |
| CPU time | 10.22 seconds |
| Started | Oct 14 10:21:54 PM UTC 24 |
| Finished | Oct 14 10:22:06 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4044214789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.4044214789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.189316545 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 6463350620 ps |
| CPU time | 15.36 seconds |
| Started | Oct 14 10:21:51 PM UTC 24 |
| Finished | Oct 14 10:22:08 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189316545 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.189316545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.3709599379 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2022556236 ps |
| CPU time | 6.15 seconds |
| Started | Oct 14 10:22:07 PM UTC 24 |
| Finished | Oct 14 10:22:14 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709599379 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.3709599379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1683013520 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4088601063 ps |
| CPU time | 11.9 seconds |
| Started | Oct 14 10:22:00 PM UTC 24 |
| Finished | Oct 14 10:22:13 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683013520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1683013520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1984612725 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 153779903677 ps |
| CPU time | 260.03 seconds |
| Started | Oct 14 10:22:03 PM UTC 24 |
| Finished | Oct 14 10:26:27 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984612725 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.1984612725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3122811363 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 124704316588 ps |
| CPU time | 105.65 seconds |
| Started | Oct 14 10:22:05 PM UTC 24 |
| Finished | Oct 14 10:23:53 PM UTC 24 |
| Peak memory | 209672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122811363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.3122811363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2915133927 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3013895924 ps |
| CPU time | 8 seconds |
| Started | Oct 14 10:21:59 PM UTC 24 |
| Finished | Oct 14 10:22:08 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915133927 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.2915133927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.1813521530 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 6097482755 ps |
| CPU time | 15.5 seconds |
| Started | Oct 14 10:22:03 PM UTC 24 |
| Finished | Oct 14 10:22:20 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813521530 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.1813521530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.380690727 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2619269611 ps |
| CPU time | 5.78 seconds |
| Started | Oct 14 10:21:58 PM UTC 24 |
| Finished | Oct 14 10:22:05 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380690727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.380690727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1976911908 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2465167956 ps |
| CPU time | 4.51 seconds |
| Started | Oct 14 10:21:57 PM UTC 24 |
| Finished | Oct 14 10:22:02 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976911908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1976911908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.2699258737 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2244993362 ps |
| CPU time | 1.97 seconds |
| Started | Oct 14 10:21:57 PM UTC 24 |
| Finished | Oct 14 10:22:00 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699258737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2699258737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.24861129 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2509840959 ps |
| CPU time | 8.93 seconds |
| Started | Oct 14 10:21:58 PM UTC 24 |
| Finished | Oct 14 10:22:08 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24861129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.24861129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.2397562599 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2228534718 ps |
| CPU time | 1.2 seconds |
| Started | Oct 14 10:21:57 PM UTC 24 |
| Finished | Oct 14 10:21:59 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397562599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.2397562599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.1761837587 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 65070279967 ps |
| CPU time | 37.03 seconds |
| Started | Oct 14 10:22:06 PM UTC 24 |
| Finished | Oct 14 10:22:45 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761837587 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.1761837587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2449379287 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 519156641013 ps |
| CPU time | 41.93 seconds |
| Started | Oct 14 10:22:06 PM UTC 24 |
| Finished | Oct 14 10:22:50 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2449379287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2449379287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2131746312 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 7359356731 ps |
| CPU time | 14.1 seconds |
| Started | Oct 14 10:22:00 PM UTC 24 |
| Finished | Oct 14 10:22:15 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131746312 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.2131746312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.2634950509 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2009580494 ps |
| CPU time | 11.55 seconds |
| Started | Oct 14 10:22:20 PM UTC 24 |
| Finished | Oct 14 10:22:32 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634950509 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.2634950509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3335217763 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3455307797 ps |
| CPU time | 15.16 seconds |
| Started | Oct 14 10:22:15 PM UTC 24 |
| Finished | Oct 14 10:22:32 PM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335217763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3335217763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.918759822 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 40324633698 ps |
| CPU time | 73.47 seconds |
| Started | Oct 14 10:22:15 PM UTC 24 |
| Finished | Oct 14 10:23:30 PM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918759822 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.918759822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.4256064726 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 46354531755 ps |
| CPU time | 118.02 seconds |
| Started | Oct 14 10:22:16 PM UTC 24 |
| Finished | Oct 14 10:24:16 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256064726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.4256064726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3676005278 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4881378600 ps |
| CPU time | 4.57 seconds |
| Started | Oct 14 10:22:14 PM UTC 24 |
| Finished | Oct 14 10:22:20 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676005278 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.3676005278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.2371093309 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4232290414 ps |
| CPU time | 20.1 seconds |
| Started | Oct 14 10:22:16 PM UTC 24 |
| Finished | Oct 14 10:22:38 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371093309 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.2371093309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.503494444 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2618711846 ps |
| CPU time | 6.4 seconds |
| Started | Oct 14 10:22:14 PM UTC 24 |
| Finished | Oct 14 10:22:21 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503494444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.503494444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.3421454844 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2493614325 ps |
| CPU time | 4.7 seconds |
| Started | Oct 14 10:22:09 PM UTC 24 |
| Finished | Oct 14 10:22:15 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421454844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3421454844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1297081269 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2118589560 ps |
| CPU time | 2.99 seconds |
| Started | Oct 14 10:22:09 PM UTC 24 |
| Finished | Oct 14 10:22:13 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297081269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1297081269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2981465795 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2526041452 ps |
| CPU time | 3.84 seconds |
| Started | Oct 14 10:22:09 PM UTC 24 |
| Finished | Oct 14 10:22:14 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981465795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2981465795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2528034259 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2111440073 ps |
| CPU time | 10.09 seconds |
| Started | Oct 14 10:22:08 PM UTC 24 |
| Finished | Oct 14 10:22:19 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528034259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2528034259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3454951768 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 16415473946 ps |
| CPU time | 62.11 seconds |
| Started | Oct 14 10:22:20 PM UTC 24 |
| Finished | Oct 14 10:23:23 PM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454951768 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.3454951768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2343258087 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 18682749305 ps |
| CPU time | 21.59 seconds |
| Started | Oct 14 10:22:18 PM UTC 24 |
| Finished | Oct 14 10:22:42 PM UTC 24 |
| Peak memory | 218144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2343258087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2343258087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1105792747 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3505824600 ps |
| CPU time | 2.53 seconds |
| Started | Oct 14 10:22:15 PM UTC 24 |
| Finished | Oct 14 10:22:19 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105792747 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.1105792747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.3245590757 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2011822320 ps |
| CPU time | 8.06 seconds |
| Started | Oct 14 10:22:34 PM UTC 24 |
| Finished | Oct 14 10:22:43 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245590757 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.3245590757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3355635078 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 124838423012 ps |
| CPU time | 86.6 seconds |
| Started | Oct 14 10:22:26 PM UTC 24 |
| Finished | Oct 14 10:23:55 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355635078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3355635078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.3405517169 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 81536812198 ps |
| CPU time | 99.02 seconds |
| Started | Oct 14 10:22:28 PM UTC 24 |
| Finished | Oct 14 10:24:09 PM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405517169 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.3405517169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2216839818 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 73102609422 ps |
| CPU time | 231.44 seconds |
| Started | Oct 14 10:22:32 PM UTC 24 |
| Finished | Oct 14 10:26:26 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216839818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.2216839818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.4000756345 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4977430070 ps |
| CPU time | 4.09 seconds |
| Started | Oct 14 10:22:25 PM UTC 24 |
| Finished | Oct 14 10:22:30 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000756345 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.4000756345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1740955400 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4550422164 ps |
| CPU time | 22.36 seconds |
| Started | Oct 14 10:22:31 PM UTC 24 |
| Finished | Oct 14 10:22:54 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740955400 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.1740955400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1523868332 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2643475040 ps |
| CPU time | 2.99 seconds |
| Started | Oct 14 10:22:23 PM UTC 24 |
| Finished | Oct 14 10:22:27 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523868332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.1523868332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.786171616 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2484302336 ps |
| CPU time | 9.26 seconds |
| Started | Oct 14 10:22:21 PM UTC 24 |
| Finished | Oct 14 10:22:31 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786171616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.786171616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.254250414 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2201530860 ps |
| CPU time | 1.99 seconds |
| Started | Oct 14 10:22:22 PM UTC 24 |
| Finished | Oct 14 10:22:25 PM UTC 24 |
| Peak memory | 206928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254250414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.254250414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.1785515065 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2535385538 ps |
| CPU time | 3.39 seconds |
| Started | Oct 14 10:22:22 PM UTC 24 |
| Finished | Oct 14 10:22:27 PM UTC 24 |
| Peak memory | 209120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785515065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1785515065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.3522547427 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2146303779 ps |
| CPU time | 2.03 seconds |
| Started | Oct 14 10:22:21 PM UTC 24 |
| Finished | Oct 14 10:22:24 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522547427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.3522547427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4229657462 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 10000444999 ps |
| CPU time | 6.04 seconds |
| Started | Oct 14 10:22:33 PM UTC 24 |
| Finished | Oct 14 10:22:40 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4229657462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.4229657462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4198116019 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3333626381 ps |
| CPU time | 11.15 seconds |
| Started | Oct 14 10:22:27 PM UTC 24 |
| Finished | Oct 14 10:22:40 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198116019 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.4198116019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1828392091 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2040780277 ps |
| CPU time | 2.24 seconds |
| Started | Oct 14 10:22:48 PM UTC 24 |
| Finished | Oct 14 10:22:52 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828392091 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.1828392091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.533187212 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3288311594 ps |
| CPU time | 11.18 seconds |
| Started | Oct 14 10:22:42 PM UTC 24 |
| Finished | Oct 14 10:22:55 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533187212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.533187212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.2939038640 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 186605109665 ps |
| CPU time | 135.02 seconds |
| Started | Oct 14 10:22:44 PM UTC 24 |
| Finished | Oct 14 10:25:01 PM UTC 24 |
| Peak memory | 209532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939038640 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.2939038640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3285268449 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3348692718 ps |
| CPU time | 3.37 seconds |
| Started | Oct 14 10:22:42 PM UTC 24 |
| Finished | Oct 14 10:22:47 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285268449 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.3285268449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3464841915 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3015756386 ps |
| CPU time | 7.16 seconds |
| Started | Oct 14 10:22:45 PM UTC 24 |
| Finished | Oct 14 10:22:53 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464841915 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.3464841915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1826606797 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2609156480 ps |
| CPU time | 10.29 seconds |
| Started | Oct 14 10:22:40 PM UTC 24 |
| Finished | Oct 14 10:22:52 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826606797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1826606797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.237575037 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2462511804 ps |
| CPU time | 13.93 seconds |
| Started | Oct 14 10:22:38 PM UTC 24 |
| Finished | Oct 14 10:22:53 PM UTC 24 |
| Peak memory | 209324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237575037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.237575037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.1444570299 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2140303723 ps |
| CPU time | 2.32 seconds |
| Started | Oct 14 10:22:38 PM UTC 24 |
| Finished | Oct 14 10:22:41 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444570299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.1444570299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.2675231628 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2560522066 ps |
| CPU time | 2.43 seconds |
| Started | Oct 14 10:22:40 PM UTC 24 |
| Finished | Oct 14 10:22:44 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675231628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2675231628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.3302938294 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2121396924 ps |
| CPU time | 4.08 seconds |
| Started | Oct 14 10:22:38 PM UTC 24 |
| Finished | Oct 14 10:22:43 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302938294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3302938294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.241760552 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1368536904573 ps |
| CPU time | 179.5 seconds |
| Started | Oct 14 10:22:47 PM UTC 24 |
| Finished | Oct 14 10:25:49 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241760552 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.241760552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2068389532 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 18071956159 ps |
| CPU time | 10.44 seconds |
| Started | Oct 14 10:22:47 PM UTC 24 |
| Finished | Oct 14 10:22:59 PM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2068389532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.2068389532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.491734129 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6625135298 ps |
| CPU time | 7.58 seconds |
| Started | Oct 14 10:22:44 PM UTC 24 |
| Finished | Oct 14 10:22:52 PM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491734129 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.491734129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.24082826 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 2015455626 ps |
| CPU time | 4.56 seconds |
| Started | Oct 14 10:22:56 PM UTC 24 |
| Finished | Oct 14 10:23:02 PM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24082826 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.24082826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2916456266 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3435454523 ps |
| CPU time | 10.58 seconds |
| Started | Oct 14 10:22:54 PM UTC 24 |
| Finished | Oct 14 10:23:05 PM UTC 24 |
| Peak memory | 209536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916456266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.2916456266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.744607354 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3742747545 ps |
| CPU time | 4.95 seconds |
| Started | Oct 14 10:22:54 PM UTC 24 |
| Finished | Oct 14 10:23:00 PM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744607354 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.744607354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3103345949 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3609146720 ps |
| CPU time | 17.54 seconds |
| Started | Oct 14 10:22:55 PM UTC 24 |
| Finished | Oct 14 10:23:14 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103345949 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.3103345949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.234693408 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2664115903 ps |
| CPU time | 2.21 seconds |
| Started | Oct 14 10:22:52 PM UTC 24 |
| Finished | Oct 14 10:22:56 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234693408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.234693408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3660973346 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2480487204 ps |
| CPU time | 3.88 seconds |
| Started | Oct 14 10:22:50 PM UTC 24 |
| Finished | Oct 14 10:22:55 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660973346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3660973346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.72894682 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2052580573 ps |
| CPU time | 7.87 seconds |
| Started | Oct 14 10:22:50 PM UTC 24 |
| Finished | Oct 14 10:23:00 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72894682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.72894682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2672215551 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2609087269 ps |
| CPU time | 1.71 seconds |
| Started | Oct 14 10:22:52 PM UTC 24 |
| Finished | Oct 14 10:22:55 PM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672215551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2672215551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.873163421 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 2121035605 ps |
| CPU time | 4.26 seconds |
| Started | Oct 14 10:22:48 PM UTC 24 |
| Finished | Oct 14 10:22:53 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873163421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.873163421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.3052962835 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 11620906623 ps |
| CPU time | 25.17 seconds |
| Started | Oct 14 10:22:56 PM UTC 24 |
| Finished | Oct 14 10:23:23 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052962835 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.3052962835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3868837552 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 11269268327 ps |
| CPU time | 20.55 seconds |
| Started | Oct 14 10:22:56 PM UTC 24 |
| Finished | Oct 14 10:23:18 PM UTC 24 |
| Peak memory | 219956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3868837552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3868837552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.333719710 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 328767122086 ps |
| CPU time | 78.82 seconds |
| Started | Oct 14 10:22:54 PM UTC 24 |
| Finished | Oct 14 10:24:14 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333719710 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.333719710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.1485541966 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2009456809 ps |
| CPU time | 11.16 seconds |
| Started | Oct 14 10:23:09 PM UTC 24 |
| Finished | Oct 14 10:23:22 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485541966 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.1485541966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1875448072 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3419676817 ps |
| CPU time | 18.28 seconds |
| Started | Oct 14 10:23:03 PM UTC 24 |
| Finished | Oct 14 10:23:22 PM UTC 24 |
| Peak memory | 209164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875448072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.1875448072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1207140923 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 85389459834 ps |
| CPU time | 285.28 seconds |
| Started | Oct 14 10:23:06 PM UTC 24 |
| Finished | Oct 14 10:27:55 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207140923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.1207140923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3686689216 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3375050882 ps |
| CPU time | 8.29 seconds |
| Started | Oct 14 10:23:01 PM UTC 24 |
| Finished | Oct 14 10:23:10 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686689216 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.3686689216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3892822849 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2618472215 ps |
| CPU time | 6.93 seconds |
| Started | Oct 14 10:23:01 PM UTC 24 |
| Finished | Oct 14 10:23:09 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892822849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.3892822849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.3610491781 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2488289875 ps |
| CPU time | 3.81 seconds |
| Started | Oct 14 10:22:59 PM UTC 24 |
| Finished | Oct 14 10:23:04 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610491781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3610491781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3188361767 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2028062833 ps |
| CPU time | 3.85 seconds |
| Started | Oct 14 10:22:59 PM UTC 24 |
| Finished | Oct 14 10:23:04 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188361767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.3188361767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.2492742563 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2511759767 ps |
| CPU time | 9.67 seconds |
| Started | Oct 14 10:23:00 PM UTC 24 |
| Finished | Oct 14 10:23:11 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492742563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2492742563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.3942065232 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2129903232 ps |
| CPU time | 3.11 seconds |
| Started | Oct 14 10:22:57 PM UTC 24 |
| Finished | Oct 14 10:23:02 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942065232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3942065232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.4189177003 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 96456157032 ps |
| CPU time | 93.85 seconds |
| Started | Oct 14 10:23:09 PM UTC 24 |
| Finished | Oct 14 10:24:45 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189177003 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.4189177003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3636828626 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4200353799 ps |
| CPU time | 18.48 seconds |
| Started | Oct 14 10:23:09 PM UTC 24 |
| Finished | Oct 14 10:23:29 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3636828626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3636828626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3516090798 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2691522918 ps |
| CPU time | 4.18 seconds |
| Started | Oct 14 10:23:03 PM UTC 24 |
| Finished | Oct 14 10:23:08 PM UTC 24 |
| Peak memory | 209264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516090798 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.3516090798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.49714571 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2027294224 ps |
| CPU time | 3.57 seconds |
| Started | Oct 14 10:23:23 PM UTC 24 |
| Finished | Oct 14 10:23:27 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49714571 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.49714571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3109528575 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3490724458 ps |
| CPU time | 11.53 seconds |
| Started | Oct 14 10:23:15 PM UTC 24 |
| Finished | Oct 14 10:23:28 PM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109528575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3109528575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2780262988 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 155160975728 ps |
| CPU time | 330.22 seconds |
| Started | Oct 14 10:23:18 PM UTC 24 |
| Finished | Oct 14 10:28:53 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780262988 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.2780262988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2709796260 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 42747488561 ps |
| CPU time | 8.48 seconds |
| Started | Oct 14 10:23:19 PM UTC 24 |
| Finished | Oct 14 10:23:29 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709796260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.2709796260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.488195879 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2722639917 ps |
| CPU time | 6.62 seconds |
| Started | Oct 14 10:23:14 PM UTC 24 |
| Finished | Oct 14 10:23:22 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488195879 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.488195879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.524817747 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3255418577 ps |
| CPU time | 7.98 seconds |
| Started | Oct 14 10:23:19 PM UTC 24 |
| Finished | Oct 14 10:23:28 PM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524817747 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.524817747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4153624702 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2617759685 ps |
| CPU time | 5.9 seconds |
| Started | Oct 14 10:23:13 PM UTC 24 |
| Finished | Oct 14 10:23:20 PM UTC 24 |
| Peak memory | 209628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153624702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.4153624702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.2364929600 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 2461768867 ps |
| CPU time | 12.37 seconds |
| Started | Oct 14 10:23:10 PM UTC 24 |
| Finished | Oct 14 10:23:24 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364929600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2364929600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.2717613379 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2072965633 ps |
| CPU time | 3.32 seconds |
| Started | Oct 14 10:23:12 PM UTC 24 |
| Finished | Oct 14 10:23:16 PM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717613379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2717613379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1220474051 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2524412367 ps |
| CPU time | 4.23 seconds |
| Started | Oct 14 10:23:12 PM UTC 24 |
| Finished | Oct 14 10:23:17 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220474051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1220474051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.1110323746 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2110745948 ps |
| CPU time | 6.61 seconds |
| Started | Oct 14 10:23:10 PM UTC 24 |
| Finished | Oct 14 10:23:18 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110323746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.1110323746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1293342829 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 16062719282 ps |
| CPU time | 14.03 seconds |
| Started | Oct 14 10:23:20 PM UTC 24 |
| Finished | Oct 14 10:23:36 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293342829 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.1293342829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1786834503 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 9052871440 ps |
| CPU time | 3.36 seconds |
| Started | Oct 14 10:23:17 PM UTC 24 |
| Finished | Oct 14 10:23:21 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786834503 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.1786834503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.4100312771 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 2020162303 ps |
| CPU time | 4.81 seconds |
| Started | Oct 14 10:23:30 PM UTC 24 |
| Finished | Oct 14 10:23:36 PM UTC 24 |
| Peak memory | 209092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100312771 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.4100312771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2465850776 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3170758757 ps |
| CPU time | 1.89 seconds |
| Started | Oct 14 10:23:26 PM UTC 24 |
| Finished | Oct 14 10:23:29 PM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465850776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2465850776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1998066692 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 123280047361 ps |
| CPU time | 394.14 seconds |
| Started | Oct 14 10:23:27 PM UTC 24 |
| Finished | Oct 14 10:30:06 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998066692 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.1998066692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2811698213 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 71978075876 ps |
| CPU time | 73.56 seconds |
| Started | Oct 14 10:23:29 PM UTC 24 |
| Finished | Oct 14 10:24:44 PM UTC 24 |
| Peak memory | 209700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811698213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.2811698213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2731195834 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3116561509 ps |
| CPU time | 4.41 seconds |
| Started | Oct 14 10:23:25 PM UTC 24 |
| Finished | Oct 14 10:23:31 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731195834 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.2731195834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.935650069 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3262585129 ps |
| CPU time | 2.59 seconds |
| Started | Oct 14 10:23:28 PM UTC 24 |
| Finished | Oct 14 10:23:32 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935650069 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.935650069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1529368547 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2650500830 ps |
| CPU time | 2.44 seconds |
| Started | Oct 14 10:23:24 PM UTC 24 |
| Finished | Oct 14 10:23:27 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529368547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1529368547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3192565115 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 2498110030 ps |
| CPU time | 3.89 seconds |
| Started | Oct 14 10:23:23 PM UTC 24 |
| Finished | Oct 14 10:23:28 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192565115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3192565115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.1882112286 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 2134742979 ps |
| CPU time | 4.29 seconds |
| Started | Oct 14 10:23:23 PM UTC 24 |
| Finished | Oct 14 10:23:28 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882112286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1882112286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.631341585 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2538988922 ps |
| CPU time | 4.97 seconds |
| Started | Oct 14 10:23:24 PM UTC 24 |
| Finished | Oct 14 10:23:30 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631341585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.631341585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3129608006 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2122257190 ps |
| CPU time | 5.96 seconds |
| Started | Oct 14 10:23:23 PM UTC 24 |
| Finished | Oct 14 10:23:30 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129608006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3129608006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.4127152842 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 10327188277 ps |
| CPU time | 25.77 seconds |
| Started | Oct 14 10:23:29 PM UTC 24 |
| Finished | Oct 14 10:23:56 PM UTC 24 |
| Peak memory | 209360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127152842 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.4127152842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3925857943 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 9251693978 ps |
| CPU time | 8.65 seconds |
| Started | Oct 14 10:23:29 PM UTC 24 |
| Finished | Oct 14 10:23:38 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3925857943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3925857943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.775410885 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 5330510746 ps |
| CPU time | 4.91 seconds |
| Started | Oct 14 10:23:26 PM UTC 24 |
| Finished | Oct 14 10:23:32 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775410885 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.775410885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.1805353720 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2042977437 ps |
| CPU time | 2.17 seconds |
| Started | Oct 14 10:23:37 PM UTC 24 |
| Finished | Oct 14 10:23:40 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805353720 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.1805353720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.172520620 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3647204849 ps |
| CPU time | 5.39 seconds |
| Started | Oct 14 10:23:31 PM UTC 24 |
| Finished | Oct 14 10:23:38 PM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172520620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.172520620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.3007753723 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 197317777991 ps |
| CPU time | 285.94 seconds |
| Started | Oct 14 10:23:33 PM UTC 24 |
| Finished | Oct 14 10:28:23 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007753723 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.3007753723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.955454622 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 62922685816 ps |
| CPU time | 15.56 seconds |
| Started | Oct 14 10:23:36 PM UTC 24 |
| Finished | Oct 14 10:23:52 PM UTC 24 |
| Peak memory | 209676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955454622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.955454622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2911981892 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3201910611 ps |
| CPU time | 15.33 seconds |
| Started | Oct 14 10:23:31 PM UTC 24 |
| Finished | Oct 14 10:23:48 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911981892 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.2911981892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.151449740 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2835576594 ps |
| CPU time | 11.6 seconds |
| Started | Oct 14 10:23:33 PM UTC 24 |
| Finished | Oct 14 10:23:46 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151449740 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.151449740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.746349215 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2630733527 ps |
| CPU time | 3.84 seconds |
| Started | Oct 14 10:23:31 PM UTC 24 |
| Finished | Oct 14 10:23:36 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746349215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.746349215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.403286543 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2488264826 ps |
| CPU time | 3.85 seconds |
| Started | Oct 14 10:23:30 PM UTC 24 |
| Finished | Oct 14 10:23:35 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403286543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.403286543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.707395412 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2192134142 ps |
| CPU time | 9.26 seconds |
| Started | Oct 14 10:23:30 PM UTC 24 |
| Finished | Oct 14 10:23:40 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707395412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.707395412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.3818767207 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2512239726 ps |
| CPU time | 10.93 seconds |
| Started | Oct 14 10:23:30 PM UTC 24 |
| Finished | Oct 14 10:23:42 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818767207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.3818767207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.889147509 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2112618154 ps |
| CPU time | 6.27 seconds |
| Started | Oct 14 10:23:30 PM UTC 24 |
| Finished | Oct 14 10:23:37 PM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889147509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.889147509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.170197956 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 128618907099 ps |
| CPU time | 82.74 seconds |
| Started | Oct 14 10:23:36 PM UTC 24 |
| Finished | Oct 14 10:25:00 PM UTC 24 |
| Peak memory | 209736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170197956 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.170197956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.641208666 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3953869654 ps |
| CPU time | 23.97 seconds |
| Started | Oct 14 10:23:36 PM UTC 24 |
| Finished | Oct 14 10:24:01 PM UTC 24 |
| Peak memory | 217728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=641208666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.641208666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2457882691 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 8233545407 ps |
| CPU time | 2.81 seconds |
| Started | Oct 14 10:23:31 PM UTC 24 |
| Finished | Oct 14 10:23:35 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457882691 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.2457882691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1230220830 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2026255097 ps |
| CPU time | 3.55 seconds |
| Started | Oct 14 10:13:13 PM UTC 24 |
| Finished | Oct 14 10:13:17 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230220830 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.1230220830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1677299190 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3571520052 ps |
| CPU time | 3.08 seconds |
| Started | Oct 14 10:13:09 PM UTC 24 |
| Finished | Oct 14 10:13:13 PM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677299190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1677299190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.781658643 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 195319290294 ps |
| CPU time | 274.99 seconds |
| Started | Oct 14 10:13:10 PM UTC 24 |
| Finished | Oct 14 10:17:49 PM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781658643 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.781658643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2781901683 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 70327683707 ps |
| CPU time | 52.03 seconds |
| Started | Oct 14 10:13:11 PM UTC 24 |
| Finished | Oct 14 10:14:05 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781901683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.2781901683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.211013391 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3349239432 ps |
| CPU time | 11.25 seconds |
| Started | Oct 14 10:13:09 PM UTC 24 |
| Finished | Oct 14 10:13:22 PM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211013391 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.211013391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.710403998 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3330233711 ps |
| CPU time | 12.66 seconds |
| Started | Oct 14 10:13:11 PM UTC 24 |
| Finished | Oct 14 10:13:25 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710403998 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.710403998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1740352434 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2647747898 ps |
| CPU time | 2.5 seconds |
| Started | Oct 14 10:13:09 PM UTC 24 |
| Finished | Oct 14 10:13:13 PM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740352434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1740352434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.186996053 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2475688258 ps |
| CPU time | 4.33 seconds |
| Started | Oct 14 10:13:08 PM UTC 24 |
| Finished | Oct 14 10:13:13 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186996053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.186996053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.294499242 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2073097861 ps |
| CPU time | 7.91 seconds |
| Started | Oct 14 10:13:08 PM UTC 24 |
| Finished | Oct 14 10:13:17 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294499242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.294499242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2663941043 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2532888216 ps |
| CPU time | 4.31 seconds |
| Started | Oct 14 10:13:09 PM UTC 24 |
| Finished | Oct 14 10:13:15 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663941043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2663941043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.4268339581 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2108750369 ps |
| CPU time | 8.16 seconds |
| Started | Oct 14 10:13:06 PM UTC 24 |
| Finished | Oct 14 10:13:16 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268339581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.4268339581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2419296359 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 6952504148 ps |
| CPU time | 18.06 seconds |
| Started | Oct 14 10:13:12 PM UTC 24 |
| Finished | Oct 14 10:13:32 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419296359 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.2419296359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.226394582 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3339173949 ps |
| CPU time | 12.68 seconds |
| Started | Oct 14 10:13:12 PM UTC 24 |
| Finished | Oct 14 10:13:26 PM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=226394582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.226394582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1880613402 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4393506733 ps |
| CPU time | 14.15 seconds |
| Started | Oct 14 10:13:10 PM UTC 24 |
| Finished | Oct 14 10:13:26 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880613402 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.1880613402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.467084717 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 23108736784 ps |
| CPU time | 18.77 seconds |
| Started | Oct 14 10:23:37 PM UTC 24 |
| Finished | Oct 14 10:23:57 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467084717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.467084717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2760736948 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 169611325585 ps |
| CPU time | 128.51 seconds |
| Started | Oct 14 10:23:37 PM UTC 24 |
| Finished | Oct 14 10:25:48 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760736948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.2760736948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2317438977 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 90779361047 ps |
| CPU time | 41.67 seconds |
| Started | Oct 14 10:23:38 PM UTC 24 |
| Finished | Oct 14 10:24:21 PM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317438977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.2317438977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.660471501 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 88429794272 ps |
| CPU time | 264.96 seconds |
| Started | Oct 14 10:23:38 PM UTC 24 |
| Finished | Oct 14 10:28:06 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660471501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.660471501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2051246043 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 128686992554 ps |
| CPU time | 218.38 seconds |
| Started | Oct 14 10:23:39 PM UTC 24 |
| Finished | Oct 14 10:27:21 PM UTC 24 |
| Peak memory | 209736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051246043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.2051246043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.692808005 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 45693989288 ps |
| CPU time | 77.43 seconds |
| Started | Oct 14 10:23:41 PM UTC 24 |
| Finished | Oct 14 10:25:00 PM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692808005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.692808005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.985187755 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 134734403423 ps |
| CPU time | 145.81 seconds |
| Started | Oct 14 10:23:41 PM UTC 24 |
| Finished | Oct 14 10:26:10 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985187755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.985187755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2436220311 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 38753726723 ps |
| CPU time | 55.22 seconds |
| Started | Oct 14 10:23:42 PM UTC 24 |
| Finished | Oct 14 10:24:39 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436220311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.2436220311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4112580249 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 72894228234 ps |
| CPU time | 61.88 seconds |
| Started | Oct 14 10:23:47 PM UTC 24 |
| Finished | Oct 14 10:24:50 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112580249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.4112580249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.772877824 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 85970133155 ps |
| CPU time | 70.07 seconds |
| Started | Oct 14 10:23:49 PM UTC 24 |
| Finished | Oct 14 10:25:00 PM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772877824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.772877824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.80086012 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2044961200 ps |
| CPU time | 2.85 seconds |
| Started | Oct 14 10:13:23 PM UTC 24 |
| Finished | Oct 14 10:13:27 PM UTC 24 |
| Peak memory | 209232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80086012 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.80086012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1026895306 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3466807696 ps |
| CPU time | 14.76 seconds |
| Started | Oct 14 10:13:18 PM UTC 24 |
| Finished | Oct 14 10:13:34 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026895306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1026895306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3878166527 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 45330316372 ps |
| CPU time | 53.26 seconds |
| Started | Oct 14 10:13:20 PM UTC 24 |
| Finished | Oct 14 10:14:15 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878166527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.3878166527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2886207795 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4833804446 ps |
| CPU time | 4.38 seconds |
| Started | Oct 14 10:13:17 PM UTC 24 |
| Finished | Oct 14 10:13:22 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886207795 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.2886207795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.3388453981 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3201833411 ps |
| CPU time | 3.39 seconds |
| Started | Oct 14 10:13:19 PM UTC 24 |
| Finished | Oct 14 10:13:24 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388453981 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.3388453981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.538640725 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2623005095 ps |
| CPU time | 4.14 seconds |
| Started | Oct 14 10:13:16 PM UTC 24 |
| Finished | Oct 14 10:13:21 PM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538640725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.538640725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2395417641 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2470926902 ps |
| CPU time | 7.06 seconds |
| Started | Oct 14 10:13:15 PM UTC 24 |
| Finished | Oct 14 10:13:23 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395417641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2395417641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.1142300552 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2088471957 ps |
| CPU time | 4.07 seconds |
| Started | Oct 14 10:13:15 PM UTC 24 |
| Finished | Oct 14 10:13:20 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142300552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.1142300552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3386299059 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2524514148 ps |
| CPU time | 3.71 seconds |
| Started | Oct 14 10:13:15 PM UTC 24 |
| Finished | Oct 14 10:13:20 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386299059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3386299059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.256784051 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2137294480 ps |
| CPU time | 3.89 seconds |
| Started | Oct 14 10:13:14 PM UTC 24 |
| Finished | Oct 14 10:13:19 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256784051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.256784051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3926960217 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 10867649407 ps |
| CPU time | 28.04 seconds |
| Started | Oct 14 10:13:22 PM UTC 24 |
| Finished | Oct 14 10:13:51 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926960217 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.3926960217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2422915406 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3370335164 ps |
| CPU time | 16.73 seconds |
| Started | Oct 14 10:13:21 PM UTC 24 |
| Finished | Oct 14 10:13:39 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2422915406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2422915406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2485198510 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 6678674414 ps |
| CPU time | 4.29 seconds |
| Started | Oct 14 10:13:18 PM UTC 24 |
| Finished | Oct 14 10:13:23 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485198510 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.2485198510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4235574554 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 35610140266 ps |
| CPU time | 47.44 seconds |
| Started | Oct 14 10:23:49 PM UTC 24 |
| Finished | Oct 14 10:24:38 PM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235574554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.4235574554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2469040876 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 36983752870 ps |
| CPU time | 106.49 seconds |
| Started | Oct 14 10:23:49 PM UTC 24 |
| Finished | Oct 14 10:25:37 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469040876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.2469040876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1645550212 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 35807745614 ps |
| CPU time | 79.59 seconds |
| Started | Oct 14 10:23:53 PM UTC 24 |
| Finished | Oct 14 10:25:14 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645550212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.1645550212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4222160662 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 67556310127 ps |
| CPU time | 124.74 seconds |
| Started | Oct 14 10:23:53 PM UTC 24 |
| Finished | Oct 14 10:26:00 PM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222160662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.4222160662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1660411607 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 26832544512 ps |
| CPU time | 93.6 seconds |
| Started | Oct 14 10:23:54 PM UTC 24 |
| Finished | Oct 14 10:25:30 PM UTC 24 |
| Peak memory | 209680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660411607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.1660411607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1715554739 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 46132713745 ps |
| CPU time | 112.37 seconds |
| Started | Oct 14 10:23:56 PM UTC 24 |
| Finished | Oct 14 10:25:51 PM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715554739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.1715554739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1522384687 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 43140864015 ps |
| CPU time | 41.84 seconds |
| Started | Oct 14 10:23:56 PM UTC 24 |
| Finished | Oct 14 10:24:40 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522384687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.1522384687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.3074634551 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2018957370 ps |
| CPU time | 5.5 seconds |
| Started | Oct 14 10:13:32 PM UTC 24 |
| Finished | Oct 14 10:13:38 PM UTC 24 |
| Peak memory | 209228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074634551 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.3074634551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2313153901 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3447714720 ps |
| CPU time | 7.98 seconds |
| Started | Oct 14 10:13:26 PM UTC 24 |
| Finished | Oct 14 10:13:35 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313153901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.2313153901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.1597682945 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 131848419235 ps |
| CPU time | 122.39 seconds |
| Started | Oct 14 10:13:28 PM UTC 24 |
| Finished | Oct 14 10:15:32 PM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597682945 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.1597682945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3770265788 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3358233337 ps |
| CPU time | 2.98 seconds |
| Started | Oct 14 10:13:26 PM UTC 24 |
| Finished | Oct 14 10:13:30 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770265788 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.3770265788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2861760113 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3014685830 ps |
| CPU time | 3.39 seconds |
| Started | Oct 14 10:13:28 PM UTC 24 |
| Finished | Oct 14 10:13:32 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861760113 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.2861760113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1411778181 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2612626872 ps |
| CPU time | 13.09 seconds |
| Started | Oct 14 10:13:25 PM UTC 24 |
| Finished | Oct 14 10:13:39 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411778181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.1411778181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.619435162 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2507023964 ps |
| CPU time | 3.12 seconds |
| Started | Oct 14 10:13:24 PM UTC 24 |
| Finished | Oct 14 10:13:28 PM UTC 24 |
| Peak memory | 209368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619435162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.619435162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.431795807 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2100605404 ps |
| CPU time | 10.81 seconds |
| Started | Oct 14 10:13:24 PM UTC 24 |
| Finished | Oct 14 10:13:36 PM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431795807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.431795807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.1684661590 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2521413080 ps |
| CPU time | 6.46 seconds |
| Started | Oct 14 10:13:24 PM UTC 24 |
| Finished | Oct 14 10:13:32 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684661590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.1684661590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1508447815 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2140610828 ps |
| CPU time | 2.55 seconds |
| Started | Oct 14 10:13:23 PM UTC 24 |
| Finished | Oct 14 10:13:27 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508447815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1508447815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.1825273192 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 217771265372 ps |
| CPU time | 405.63 seconds |
| Started | Oct 14 10:13:31 PM UTC 24 |
| Finished | Oct 14 10:20:21 PM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825273192 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.1825273192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3998727803 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4591689816 ps |
| CPU time | 22.65 seconds |
| Started | Oct 14 10:13:29 PM UTC 24 |
| Finished | Oct 14 10:13:53 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3998727803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.3998727803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1943717976 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 706028187381 ps |
| CPU time | 27.25 seconds |
| Started | Oct 14 10:13:27 PM UTC 24 |
| Finished | Oct 14 10:13:56 PM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943717976 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.1943717976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.473091456 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 75744013884 ps |
| CPU time | 198.09 seconds |
| Started | Oct 14 10:24:02 PM UTC 24 |
| Finished | Oct 14 10:27:22 PM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473091456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.473091456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2973001274 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 82715544979 ps |
| CPU time | 61.22 seconds |
| Started | Oct 14 10:24:07 PM UTC 24 |
| Finished | Oct 14 10:25:10 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973001274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.2973001274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2676964535 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 32901819763 ps |
| CPU time | 121.35 seconds |
| Started | Oct 14 10:24:07 PM UTC 24 |
| Finished | Oct 14 10:26:10 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676964535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.2676964535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1796513109 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 89921691183 ps |
| CPU time | 42.75 seconds |
| Started | Oct 14 10:24:10 PM UTC 24 |
| Finished | Oct 14 10:24:54 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796513109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.1796513109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3468923683 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 25116449845 ps |
| CPU time | 28.96 seconds |
| Started | Oct 14 10:24:17 PM UTC 24 |
| Finished | Oct 14 10:24:47 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468923683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.3468923683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1136798481 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 60419402489 ps |
| CPU time | 80.73 seconds |
| Started | Oct 14 10:24:22 PM UTC 24 |
| Finished | Oct 14 10:25:45 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136798481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.1136798481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1638872950 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 33571542945 ps |
| CPU time | 109.18 seconds |
| Started | Oct 14 10:24:29 PM UTC 24 |
| Finished | Oct 14 10:26:21 PM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638872950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.1638872950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3719006541 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 29345522520 ps |
| CPU time | 35.89 seconds |
| Started | Oct 14 10:24:38 PM UTC 24 |
| Finished | Oct 14 10:25:16 PM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719006541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.3719006541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3620317640 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2009844164 ps |
| CPU time | 10.82 seconds |
| Started | Oct 14 10:13:42 PM UTC 24 |
| Finished | Oct 14 10:13:54 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620317640 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.3620317640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.4194876481 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3719516671 ps |
| CPU time | 6.28 seconds |
| Started | Oct 14 10:13:37 PM UTC 24 |
| Finished | Oct 14 10:13:45 PM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194876481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.4194876481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3785270730 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 38509602782 ps |
| CPU time | 165.03 seconds |
| Started | Oct 14 10:13:40 PM UTC 24 |
| Finished | Oct 14 10:16:28 PM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785270730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.3785270730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3876984846 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 655229613558 ps |
| CPU time | 1883.16 seconds |
| Started | Oct 14 10:13:36 PM UTC 24 |
| Finished | Oct 14 10:45:17 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876984846 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.3876984846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1488379741 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3044310021 ps |
| CPU time | 14.25 seconds |
| Started | Oct 14 10:13:40 PM UTC 24 |
| Finished | Oct 14 10:13:55 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488379741 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.1488379741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1958736733 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2612539274 ps |
| CPU time | 13.35 seconds |
| Started | Oct 14 10:13:35 PM UTC 24 |
| Finished | Oct 14 10:13:50 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958736733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1958736733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.4227208249 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2472663252 ps |
| CPU time | 4.01 seconds |
| Started | Oct 14 10:13:33 PM UTC 24 |
| Finished | Oct 14 10:13:38 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227208249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.4227208249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.2895854329 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2081051904 ps |
| CPU time | 6.52 seconds |
| Started | Oct 14 10:13:33 PM UTC 24 |
| Finished | Oct 14 10:13:41 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895854329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.2895854329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1387597421 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2514255124 ps |
| CPU time | 7.31 seconds |
| Started | Oct 14 10:13:33 PM UTC 24 |
| Finished | Oct 14 10:13:42 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387597421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1387597421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.4010716946 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2112520954 ps |
| CPU time | 3.99 seconds |
| Started | Oct 14 10:13:33 PM UTC 24 |
| Finished | Oct 14 10:13:38 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010716946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.4010716946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.911058931 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 284685480495 ps |
| CPU time | 569.83 seconds |
| Started | Oct 14 10:13:42 PM UTC 24 |
| Finished | Oct 14 10:23:18 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911058931 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.911058931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1262331704 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 6248381637 ps |
| CPU time | 32.83 seconds |
| Started | Oct 14 10:13:41 PM UTC 24 |
| Finished | Oct 14 10:14:15 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1262331704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.1262331704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.479986225 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 10536371408 ps |
| CPU time | 2.61 seconds |
| Started | Oct 14 10:13:39 PM UTC 24 |
| Finished | Oct 14 10:13:42 PM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479986225 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.479986225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.808422949 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 33803294706 ps |
| CPU time | 33.42 seconds |
| Started | Oct 14 10:24:40 PM UTC 24 |
| Finished | Oct 14 10:25:14 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808422949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.808422949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2924376994 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 58731867339 ps |
| CPU time | 87.36 seconds |
| Started | Oct 14 10:24:48 PM UTC 24 |
| Finished | Oct 14 10:26:17 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924376994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.2924376994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2375123178 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 39527015046 ps |
| CPU time | 75.27 seconds |
| Started | Oct 14 10:24:51 PM UTC 24 |
| Finished | Oct 14 10:26:08 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375123178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.2375123178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.590357412 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 25583045416 ps |
| CPU time | 74.56 seconds |
| Started | Oct 14 10:24:55 PM UTC 24 |
| Finished | Oct 14 10:26:11 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590357412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.590357412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3491769240 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 74207671583 ps |
| CPU time | 186.9 seconds |
| Started | Oct 14 10:25:01 PM UTC 24 |
| Finished | Oct 14 10:28:11 PM UTC 24 |
| Peak memory | 209332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491769240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.3491769240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3193390031 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 27292893988 ps |
| CPU time | 34.5 seconds |
| Started | Oct 14 10:25:01 PM UTC 24 |
| Finished | Oct 14 10:25:37 PM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193390031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.3193390031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.1685714433 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2011836829 ps |
| CPU time | 9.55 seconds |
| Started | Oct 14 10:13:56 PM UTC 24 |
| Finished | Oct 14 10:14:07 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685714433 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.1685714433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.596151741 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 196041697910 ps |
| CPU time | 505.99 seconds |
| Started | Oct 14 10:13:51 PM UTC 24 |
| Finished | Oct 14 10:22:22 PM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596151741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.596151741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.588461283 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 46061752710 ps |
| CPU time | 35.2 seconds |
| Started | Oct 14 10:13:54 PM UTC 24 |
| Finished | Oct 14 10:14:30 PM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588461283 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.588461283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1492544296 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 33185163241 ps |
| CPU time | 98.99 seconds |
| Started | Oct 14 10:13:55 PM UTC 24 |
| Finished | Oct 14 10:15:36 PM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492544296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.1492544296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.101541302 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3839775221 ps |
| CPU time | 12.29 seconds |
| Started | Oct 14 10:13:51 PM UTC 24 |
| Finished | Oct 14 10:14:04 PM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101541302 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.101541302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2773011024 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2607409911 ps |
| CPU time | 11.95 seconds |
| Started | Oct 14 10:13:49 PM UTC 24 |
| Finished | Oct 14 10:14:03 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773011024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2773011024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.1163849416 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2460954714 ps |
| CPU time | 3.55 seconds |
| Started | Oct 14 10:13:43 PM UTC 24 |
| Finished | Oct 14 10:13:48 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163849416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1163849416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.2857630915 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2092510207 ps |
| CPU time | 3.1 seconds |
| Started | Oct 14 10:13:45 PM UTC 24 |
| Finished | Oct 14 10:13:49 PM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857630915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2857630915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1951062142 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2512818558 ps |
| CPU time | 15.88 seconds |
| Started | Oct 14 10:13:48 PM UTC 24 |
| Finished | Oct 14 10:14:05 PM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951062142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.1951062142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.1567497535 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2121089531 ps |
| CPU time | 4.43 seconds |
| Started | Oct 14 10:13:43 PM UTC 24 |
| Finished | Oct 14 10:13:49 PM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567497535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.1567497535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2707927882 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5237775979 ps |
| CPU time | 31.73 seconds |
| Started | Oct 14 10:13:55 PM UTC 24 |
| Finished | Oct 14 10:14:28 PM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2707927882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.2707927882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2256208980 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5317901660 ps |
| CPU time | 15.53 seconds |
| Started | Oct 14 10:13:52 PM UTC 24 |
| Finished | Oct 14 10:14:08 PM UTC 24 |
| Peak memory | 209372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256208980 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.2256208980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2547226701 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 44365291052 ps |
| CPU time | 124.43 seconds |
| Started | Oct 14 10:25:04 PM UTC 24 |
| Finished | Oct 14 10:27:10 PM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547226701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.2547226701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4252596282 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 43314824425 ps |
| CPU time | 19.26 seconds |
| Started | Oct 14 10:25:04 PM UTC 24 |
| Finished | Oct 14 10:25:24 PM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252596282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.4252596282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3926980646 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 148997866358 ps |
| CPU time | 508.63 seconds |
| Started | Oct 14 10:25:11 PM UTC 24 |
| Finished | Oct 14 10:33:45 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926980646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.3926980646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3273353639 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 74925153674 ps |
| CPU time | 32.43 seconds |
| Started | Oct 14 10:25:15 PM UTC 24 |
| Finished | Oct 14 10:25:49 PM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273353639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.3273353639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2480963364 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 28531621808 ps |
| CPU time | 33.89 seconds |
| Started | Oct 14 10:25:15 PM UTC 24 |
| Finished | Oct 14 10:25:50 PM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480963364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.2480963364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1941483913 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 64761898693 ps |
| CPU time | 104.32 seconds |
| Started | Oct 14 10:25:16 PM UTC 24 |
| Finished | Oct 14 10:27:02 PM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941483913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.1941483913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.885389992 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 26098553043 ps |
| CPU time | 30.18 seconds |
| Started | Oct 14 10:25:17 PM UTC 24 |
| Finished | Oct 14 10:25:49 PM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885389992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.885389992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2216627938 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 27833903922 ps |
| CPU time | 90.15 seconds |
| Started | Oct 14 10:25:17 PM UTC 24 |
| Finished | Oct 14 10:26:49 PM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216627938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.2216627938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest |
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