UART Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	53.340s	11.619ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	52.294us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.620s	17.633us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.590s	1.045ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	99.645us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.450s	29.662us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.620s	17.633us	20	20	100.00
		uart_csr_aliasing	0.770s	99.645us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.003m	102.387ms	50	50	100.00
V2	parity	uart_smoke	53.340s	11.619ms	50	50	100.00
		uart_tx_rx	3.003m	102.387ms	50	50	100.00
V2	parity_error	uart_intr	44.561m	1.869s	49	50	98.00
		uart_rx_parity_err	6.304m	279.954ms	50	50	100.00
V2	watermark	uart_tx_rx	3.003m	102.387ms	50	50	100.00
		uart_intr	44.561m	1.869s	49	50	98.00
V2	fifo_full	uart_fifo_full	5.972m	230.582ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	15.004m	113.213ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.990m	100.773ms	300	300	100.00
V2	rx_frame_err	uart_intr	44.561m	1.869s	49	50	98.00
V2	rx_break_err	uart_intr	44.561m	1.869s	49	50	98.00
V2	rx_timeout	uart_intr	44.561m	1.869s	49	50	98.00
V2	perf	uart_perf	18.492m	22.279ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.260s	3.484ms	50	50	100.00
V2	line_loopback	uart_loopback	27.260s	3.484ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.118m	120.452ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.639m	61.570ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	21.680s	7.035ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	44.520s	5.179ms	45	50	90.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.394m	173.065ms	50	50	100.00
V2	stress_all	uart_stress_all	47.339m	2.362s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	33.937m	186.280ms	100	100	100.00
V2	alert_test	uart_alert_test	0.640s	127.212us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	14.475us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.820s	1.147ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.820s	1.147ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	52.294us	5	5	100.00
		uart_csr_rw	0.620s	17.633us	20	20	100.00
		uart_csr_aliasing	0.770s	99.645us	5	5	100.00
		uart_same_csr_outstanding	0.760s	18.777us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	52.294us	5	5	100.00
		uart_csr_rw	0.620s	17.633us	20	20	100.00
		uart_csr_aliasing	0.770s	99.645us	5	5	100.00
		uart_same_csr_outstanding	0.760s	18.777us	20	20	100.00
V2		TOTAL			1184	1190	99.50
V2S	tl_intg_err	uart_sec_cm	0.900s	507.650us	5	5	100.00
		uart_tl_intg_err	1.410s	656.632us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	656.632us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1314	1320	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	17	89.47
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.30	99.80	98.45	100.00	--	99.76	100.00	97.78

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: *

has 5 failures:

Test uart_rx_oversample has 5 failures.

6.uart_rx_oversample.864261368
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest/run.log

  UVM_ERROR @  30626081 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (16115 [0x3ef3] vs 32227 [0x7de3]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  38945637 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/3
  UVM_ERROR @  39340358 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (50161 [0xc3f1] vs 42986 [0xa7ea]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 357746140 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/3
  UVM_INFO @ 395482992 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/3

17.uart_rx_oversample.3142943755
Line 216, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 347529850 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (55745 [0xd9c1] vs 45955 [0xb383]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 356063628 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/16
  UVM_ERROR @ 356244188 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (36084 [0x8cf4] vs 6633 [0x19e9]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 373883227 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/16
  UVM_ERROR @ 374030009 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (5127 [0x1407] vs 10254 [0x280e]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 3 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_intr has 1 failures.
  - 3.uart_intr.1925017096
    Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```