042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 48.970s | 11.108ms | 37 | 50 | 74.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.630s | 24.051us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.680s | 13.863us | 18 | 20 | 90.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.510s | 1.294ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 0.800s | 63.150us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.240s | 109.910us | 15 | 20 | 75.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.680s | 13.863us | 18 | 20 | 90.00 |
| uart_csr_aliasing | 0.800s | 63.150us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 85 | 105 | 80.95 | |||
| V2 | base_random_seq | uart_tx_rx | 4.256m | 99.449ms | 42 | 50 | 84.00 |
| V2 | parity | uart_smoke | 48.970s | 11.108ms | 37 | 50 | 74.00 |
| uart_tx_rx | 4.256m | 99.449ms | 42 | 50 | 84.00 | ||
| V2 | parity_error | uart_intr | 58.525m | 578.127ms | 38 | 50 | 76.00 |
| uart_rx_parity_err | 11.498m | 173.363ms | 43 | 50 | 86.00 | ||
| V2 | watermark | uart_tx_rx | 4.256m | 99.449ms | 42 | 50 | 84.00 |
| uart_intr | 58.525m | 578.127ms | 38 | 50 | 76.00 | ||
| V2 | fifo_full | uart_fifo_full | 6.877m | 260.735ms | 43 | 50 | 86.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 6.678m | 225.973ms | 40 | 50 | 80.00 |
| V2 | fifo_reset | uart_fifo_reset | 7.637m | 265.178ms | 235 | 300 | 78.33 |
| V2 | rx_frame_err | uart_intr | 58.525m | 578.127ms | 38 | 50 | 76.00 |
| V2 | rx_break_err | uart_intr | 58.525m | 578.127ms | 38 | 50 | 76.00 |
| V2 | rx_timeout | uart_intr | 58.525m | 578.127ms | 38 | 50 | 76.00 |
| V2 | perf | uart_perf | 23.340m | 28.557ms | 39 | 50 | 78.00 |
| V2 | sys_loopback | uart_loopback | 32.180s | 12.515ms | 39 | 50 | 78.00 |
| V2 | line_loopback | uart_loopback | 32.180s | 12.515ms | 39 | 50 | 78.00 |
| V2 | rx_noise_filter | uart_noise_filter | 3.937m | 94.387ms | 41 | 50 | 82.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 50.190s | 31.015ms | 33 | 50 | 66.00 |
| V2 | tx_overide | uart_tx_ovrd | 44.390s | 6.823ms | 42 | 50 | 84.00 |
| V2 | rx_oversample | uart_rx_oversample | 39.650s | 4.260ms | 33 | 50 | 66.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 20.970m | 151.052ms | 42 | 50 | 84.00 |
| V2 | stress_all | uart_stress_all | 33.549m | 852.595ms | 36 | 50 | 72.00 |
| V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 45.857m | 70.238ms | 77 | 100 | 77.00 |
| V2 | alert_test | uart_alert_test | 0.580s | 12.988us | 46 | 50 | 92.00 |
| V2 | intr_test | uart_intr_test | 0.770s | 18.722us | 39 | 50 | 78.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 2.090s | 497.464us | 15 | 20 | 75.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 2.090s | 497.464us | 15 | 20 | 75.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.630s | 24.051us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.680s | 13.863us | 18 | 20 | 90.00 | ||
| uart_csr_aliasing | 0.800s | 63.150us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.780s | 30.648us | 15 | 20 | 75.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.630s | 24.051us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.680s | 13.863us | 18 | 20 | 90.00 | ||
| uart_csr_aliasing | 0.800s | 63.150us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.780s | 30.648us | 15 | 20 | 75.00 | ||
| V2 | TOTAL | 938 | 1190 | 78.82 | |||
| V2S | tl_intg_err | uart_sec_cm | 0.880s | 85.160us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.300s | 73.889us | 17 | 20 | 85.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.300s | 73.889us | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 1045 | 1320 | 79.17 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 3 | 50.00 |
| V2 | 19 | 19 | 0 | 0.00 |
| V2S | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.23 | 99.79 | 98.45 | 100.00 | -- | 99.76 | 100.00 | 97.38 |
Exit reason: Error: User command failed Job returned non-zero exit code has 240 failures:
0.uart_intr.57762229054206369603960816468772809530348638848816606512783481669421200206123
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_intr/latest/run.log
[make]: simulate
cd /workspace/0.uart_intr/latest && /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917137707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.917137707
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
11.uart_intr.99950279973779439706183650660317836676066504040263782038880483155325640232848
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_intr/latest/run.log
[make]: simulate
cd /workspace/11.uart_intr/latest && /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228577168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.228577168
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
0.uart_noise_filter.109161061088806695479608874627748516662903636882278216400567249188811072830049
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_noise_filter/latest/run.log
[make]: simulate
cd /workspace/0.uart_noise_filter/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645626465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.645626465
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
9.uart_noise_filter.5535663737772672203266997872893997286586569743422342272725845342998783207080
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_noise_filter/latest/run.log
[make]: simulate
cd /workspace/9.uart_noise_filter/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644832424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1644832424
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
0.uart_perf.64278546613035455981331161253823802671969948457455806083143592889535232383424
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_perf/latest/run.log
[make]: simulate
cd /workspace/0.uart_perf/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196333504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1196333504
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
12.uart_perf.90627775450701799519198713752919508922984643650829666882457694976613658394429
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_perf/latest/run.log
[make]: simulate
cd /workspace/12.uart_perf/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205758781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3205758781
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 8 more failures.
0.uart_stress_all.59995285578780829217923441734823058659648837073140091079368557081092693924371
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all/latest/run.log
[make]: simulate
cd /workspace/0.uart_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255564307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.255564307
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
10.uart_stress_all.89150116739291773680547454797641693566926790501506788191594128978057078200498
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all/latest/run.log
[make]: simulate
cd /workspace/10.uart_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016003250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4016003250
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:52 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 10 more failures.
1.uart_loopback.81132083848842135533879442079732723799267022430708694373330108080520154544993
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_loopback/latest/run.log
[make]: simulate
cd /workspace/1.uart_loopback/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472587617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3472587617
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.uart_loopback.23181434080377247046471888594696943778108355534325789761135992125732757033376
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_loopback/latest/run.log
[make]: simulate
cd /workspace/2.uart_loopback/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037947296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1037947296
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:53 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
Test uart_intr has 4 failures.
1.uart_intr.84024202530265064872282665351577548427188632607375229005145456528440561587680
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_intr/latest/run.log
Job ID: smart:d455da27-d980-434f-b444-47db533f5707
37.uart_intr.92899235927772027158162113924573022098872028377153680009700748957475354357011
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_intr/latest/run.log
Job ID: smart:4caa5fe4-8995-4dd8-a5fc-7d228e5caf86
... and 2 more failures.
Test uart_long_xfer_wo_dly has 1 failures.
29.uart_long_xfer_wo_dly.87645862553261327029694028117504309643832755971621910289373152123972050898921
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest/run.log
Job ID: smart:351352a8-8c4a-4df6-8ede-611e4f1918a8
Test uart_smoke has 1 failures.
30.uart_smoke.85509658212123165108320501479681920112643497403275278095571704343474211255961
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_smoke/latest/run.log
Job ID: smart:fa8258a6-bb64-413a-a603-4e516c15736d
Test uart_noise_filter has 2 failures.
36.uart_noise_filter.30225809759057332133156807134180272656500889140758078548850663346239975354493
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_noise_filter/latest/run.log
Job ID: smart:1702fb3b-5f29-4818-91bf-2cb1ba63924b
44.uart_noise_filter.49595460380593700721646177093034606507059317941978960100538697542272229790613
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_noise_filter/latest/run.log
Job ID: smart:fdb6441a-9f51-4b91-b77a-79571e4f057c
Test uart_perf has 1 failures.
37.uart_perf.7939823602826649842158014580733793571594399463549293559368939524085140669856
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_perf/latest/run.log
Job ID: smart:4909f5f2-f086-4ba1-9b27-ab6a311f8a7f
... and 5 more tests.
UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 6 failures:
Test uart_stress_all has 2 failures.
5.uart_stress_all.41559445590419012826883759248190091419983088256726714485447434985833805651140
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_stress_all/latest/run.log
UVM_ERROR @ 7049682749 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (12 [0xc] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 7049682749 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 12 [0xc]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 7051370249 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 16/19
UVM_INFO @ 7403745249 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 17/19
UVM_INFO @ 7871432749 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 18/19
38.uart_stress_all.77576091132616850187916423667570076885950404212699734115026172654085391028896
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_stress_all/latest/run.log
UVM_ERROR @ 8592880885 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (52 [0x34] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 8592880885 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 52 [0x34]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_ERROR @ 8592960885 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
UVM_INFO @ 8593000885 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/14
UVM_ERROR @ 8682840885 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (10 [0xa] vs 52 [0x34]) reg name: uart_reg_block.rdata
Test uart_loopback has 2 failures.
9.uart_loopback.96427166853965763755656834723727902185592852007024550025108483006453469143941
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_loopback/latest/run.log
UVM_ERROR @ 699803349 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (40 [0x28] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 699803349 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (254 [0xfe] vs 40 [0x28]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 700053351 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/11
UVM_INFO @ 1631852472 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/11
UVM_INFO @ 2855820597 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/11
46.uart_loopback.106325406155192383753209566218977059636084377961321114684717216523732552026071
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/46.uart_loopback/latest/run.log
UVM_ERROR @ 202981291 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (64 [0x40] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 202981291 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 64 [0x40]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 203606296 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/12
UVM_INFO @ 213606376 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/12
UVM_INFO @ 504442036 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/12
Test uart_stress_all_with_rand_reset has 2 failures.
15.uart_stress_all_with_rand_reset.106313876859971355725997953748120327211064472536342647267411659976386033229121
Line 429, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11006772028 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (187 [0xbb] vs 247 [0xf7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 11006772028 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (247 [0xf7] vs 187 [0xbb]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 11006835856 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 17/17
UVM_INFO @ 11018186602 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 134/714
UVM_INFO @ 11090695210 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 135/714
30.uart_stress_all_with_rand_reset.64619400385090524930654694886692526164970221353219002558431004096983970536757
Line 294, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5661873237 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (102 [0x66] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 5661873237 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 102 [0x66]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 5662113237 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/12
UVM_INFO @ 5674273237 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/12
UVM_INFO @ 5700433237 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/578
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 4 failures:
4.uart_rx_oversample.24401157582509761058243460417073920826312765169180166320320746956569451504100
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_rx_oversample/latest/run.log
UVM_ERROR @ 336496054 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (41721 [0xa2f9] vs 20860 [0x517c]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 372754768 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/9
UVM_INFO @ 790933849 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/9
UVM_INFO @ 1109934690 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/9
UVM_ERROR @ 1110997603 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (39397 [0x99e5] vs 52466 [0xccf2]) Regname: uart_reg_block.val.rx reset value: 0x0
18.uart_rx_oversample.74910297289379917897198658393805652102636936387545286272362377169285248615693
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_rx_oversample/latest/run.log
UVM_ERROR @ 58826521 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (13336 [0x3418] vs 13624 [0x3538]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 85738063 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/18
UVM_INFO @ 291598368 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/18
UVM_INFO @ 327628822 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/18
UVM_INFO @ 354240211 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/18
... and 2 more failures.
Job uart-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
Test uart_same_csr_outstanding has 1 failures.
10.uart_same_csr_outstanding.83787979026199310563830969866057239210485534837390261189045165475042337121500
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_same_csr_outstanding/latest/run.log
Job ID: smart:43311fad-551c-4bd6-8a18-de4ec8904b46
Test uart_intr_test has 3 failures.
34.uart_intr_test.17367503316772152421073296174316667834937560792256886483626746924870259252400
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/34.uart_intr_test/latest/run.log
Job ID: smart:82a63992-168d-47b9-b413-a9d65ed02296
36.uart_intr_test.42777998606479617573509711760762402214431419427283211334179078894110493505619
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_intr_test/latest/run.log
Job ID: smart:64745167-1d61-478b-a035-b42042aa200e
... and 1 more failures.
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:
12.uart_loopback.113623712089087375113232267992920958131791943711549484902195529797909396765951
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_loopback/latest/run.log
UVM_ERROR @ 3738487178 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 3738487178 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 3743653846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.uart_loopback.85679375475815800607981366510294269293663206957518598677464723865766369622390
Line 261, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_loopback/latest/run.log
UVM_ERROR @ 7782387673 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 7782387673 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 7787541521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:
18.uart_fifo_overflow.57669330522914474353950410643000664091033777445587826705305524908974552785106
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_fifo_overflow/latest/run.log
UVM_ERROR @ 4731750 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
UVM_INFO @ 1517868855 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/6
UVM_INFO @ 3734386587 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/6
UVM_INFO @ 4210973733 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/6
UVM_INFO @ 4211473737 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/6
UVM_ERROR (uart_scoreboard.sv:396) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
39.uart_stress_all_with_rand_reset.57595442877348981381250941061775732785953283402390210372006638370946952855631
Line 434, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 158181971194 ps: (uart_scoreboard.sv:396) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 158225054872 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 158225054872 ps: (uart_scoreboard.sv:396) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 158226388216 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 11
UVM_ERROR @ 158226471550 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 11
UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:
49.uart_stress_all_with_rand_reset.5699849990610938717036588822493321852729696384362589845691232471795501523725
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 107988046 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 107988046 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: TxWatermark/0, en_intr: 91
UVM_INFO @ 278988046 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing RxFrameErr
UVM_INFO @ 452363046 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]