UART Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: cf38c1d296

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 0 50 0.00
V1 csr_hw_reset uart_csr_hw_reset 0.930s 1.064ms 5 5 100.00
V1 csr_rw uart_csr_rw 0.630s 22.492us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 2.600s 257.294us 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 0.830s 30.356us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.500s 29.095us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.630s 22.492us 20 20 100.00
uart_csr_aliasing 0.830s 30.356us 5 5 100.00
V1 TOTAL 55 105 52.38
V2 base_random_seq uart_tx_rx 0 50 0.00
V2 parity uart_smoke 0 50 0.00
uart_tx_rx 0 50 0.00
V2 parity_error uart_intr 0 50 0.00
uart_rx_parity_err 0 50 0.00
V2 watermark uart_tx_rx 0 50 0.00
uart_intr 0 50 0.00
V2 fifo_full uart_fifo_full 0 50 0.00
V2 fifo_overflow uart_fifo_overflow 0 50 0.00
V2 fifo_reset uart_fifo_reset 0 300 0.00
V2 rx_frame_err uart_intr 0 50 0.00
V2 rx_break_err uart_intr 0 50 0.00
V2 rx_timeout uart_intr 0 50 0.00
V2 perf uart_perf 0 50 0.00
V2 sys_loopback uart_loopback 0 50 0.00
V2 line_loopback uart_loopback 0 50 0.00
V2 rx_noise_filter uart_noise_filter 0 50 0.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 0 50 0.00
V2 tx_overide uart_tx_ovrd 0 50 0.00
V2 rx_oversample uart_rx_oversample 0 50 0.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 0 50 0.00
V2 stress_all uart_stress_all 0 50 0.00
V2 stress_all_with_reset uart_stress_all_with_rand_reset 0 100 0.00
V2 alert_test uart_alert_test 0 50 0.00
V2 intr_test uart_intr_test 0.590s 16.724us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 2.130s 167.297us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 2.130s 167.297us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.930s 1.064ms 5 5 100.00
uart_csr_rw 0.630s 22.492us 20 20 100.00
uart_csr_aliasing 0.830s 30.356us 5 5 100.00
uart_same_csr_outstanding 0.750s 62.592us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.930s 1.064ms 5 5 100.00
uart_csr_rw 0.630s 22.492us 20 20 100.00
uart_csr_aliasing 0.830s 30.356us 5 5 100.00
uart_same_csr_outstanding 0.750s 62.592us 20 20 100.00
V2 TOTAL 90 1190 7.56
V2S tl_intg_err uart_sec_cm 0 5 0.00
uart_tl_intg_err 1.430s 1.606ms 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 1.430s 1.606ms 20 20 100.00
V2S TOTAL 20 25 80.00
V3 TOTAL 0 0 --
TOTAL 165 1320 12.50

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 19 19 3 15.79
V2S 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
65.90 64.36 63.61 96.46 -- 63.57 100.00 7.39

Failure Buckets

Past Results