UART Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	29.050s	6.273ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	13.013us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	13.710us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.270s	58.464us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	28.376us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.400s	50.082us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	13.710us	20	20	100.00
		uart_csr_aliasing	0.810s	28.376us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.206m	150.258ms	50	50	100.00
V2	parity	uart_smoke	29.050s	6.273ms	50	50	100.00
		uart_tx_rx	5.206m	150.258ms	50	50	100.00
V2	parity_error	uart_intr	34.474m	1.240s	46	50	92.00
		uart_rx_parity_err	3.964m	144.411ms	50	50	100.00
V2	watermark	uart_tx_rx	5.206m	150.258ms	50	50	100.00
		uart_intr	34.474m	1.240s	46	50	92.00
V2	fifo_full	uart_fifo_full	8.046m	143.886ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.853m	245.314ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.928m	144.226ms	300	300	100.00
V2	rx_frame_err	uart_intr	34.474m	1.240s	46	50	92.00
V2	rx_break_err	uart_intr	34.474m	1.240s	46	50	92.00
V2	rx_timeout	uart_intr	34.474m	1.240s	46	50	92.00
V2	perf	uart_perf	33.269m	39.387ms	49	50	98.00
V2	sys_loopback	uart_loopback	26.810s	7.923ms	47	50	94.00
V2	line_loopback	uart_loopback	26.810s	7.923ms	47	50	94.00
V2	rx_noise_filter	uart_noise_filter	5.693m	120.375ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.027m	43.937ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	45.120s	7.294ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	37.150s	4.420ms	43	50	86.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.728m	155.905ms	50	50	100.00
V2	stress_all	uart_stress_all	2.354h	4.949s	49	50	98.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	28.318m	86.121ms	98	100	98.00
V2	alert_test	uart_alert_test	0.630s	13.362us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	15.684us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	488.476us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	488.476us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	13.013us	5	5	100.00
		uart_csr_rw	0.640s	13.710us	20	20	100.00
		uart_csr_aliasing	0.810s	28.376us	5	5	100.00
		uart_same_csr_outstanding	0.780s	25.993us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	13.013us	5	5	100.00
		uart_csr_rw	0.640s	13.710us	20	20	100.00
		uart_csr_aliasing	0.810s	28.376us	5	5	100.00
		uart_same_csr_outstanding	0.780s	25.993us	20	20	100.00
V2		TOTAL			1172	1190	98.49
V2S	tl_intg_err	uart_sec_cm	0.880s	241.789us	5	5	100.00
		uart_tl_intg_err	1.360s	86.708us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.360s	86.708us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1302	1320	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	13	68.42
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.79	98.45	100.00	--	99.76	100.00	97.67

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 7 failures:

Test uart_rx_oversample has 7 failures.

7.uart_rx_oversample.38030951628828517554940589372827090496401773749391370623056299683690415239822
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_rx_oversample/latest/run.log

  UVM_ERROR @  34661036 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (55798 [0xd9f6] vs 51702 [0xc9f6]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @  43327772 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (32261 [0x7e05] vs 32325 [0x7e45]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  51752990 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/18
  UVM_ERROR @  52105620 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (38989 [0x984d] vs 39020 [0x986c]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 269544011 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/18

18.uart_rx_oversample.66706725579213105826330421944868821596224020550044587738194306036181841740913
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_rx_oversample/latest/run.log

  UVM_ERROR @  68848068 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (14477 [0x388d] vs 40006 [0x9c46]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  95643538 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/14
  UVM_INFO @ 399567469 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/14
  UVM_INFO @ 418221860 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/14
  UVM_ERROR @ 435889344 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (46279 [0xb4c7] vs 46215 [0xb487]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 5 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 5 failures:

Test uart_loopback has 3 failures.

0.uart_loopback.16915572881915596020011989079802949982477277052158833428868046038737971438168
Line 261, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_loopback/latest/run.log

  UVM_ERROR @ 7937766791 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (188 [0xbc] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 7937766791 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 188 [0xbc]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_ERROR @ 7937859572 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
  UVM_INFO @ 7937880190 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 14/14
  UVM_INFO @ 7948230561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

17.uart_loopback.89864840963444567191025324277368695337753134206218091290667035856676141888444
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_loopback/latest/run.log

  UVM_ERROR @ 1918494805 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (246 [0xf6] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 1918494805 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 246 [0xf6]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 1918610191 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/18
  UVM_INFO @ 1929725709 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/18
  UVM_INFO @ 2210498309 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/18

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 2 failures.

39.uart_stress_all_with_rand_reset.64988250726631840375082976109569130809873199783824170405516938513586784394160
Line 1081, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 51093493089 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (194 [0xc2] vs 9 [0x9]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 51093493089 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (9 [0x9] vs 194 [0xc2]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_ERROR @ 51093533089 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
  UVM_INFO @ 51093553089 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/14
  UVM_INFO @ 51120813089 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 16/51

82.uart_stress_all_with_rand_reset.53854320541804073608805210938483210014758234016603339904818270914519506056113
Line 373, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6681210304 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (15 [0xf] vs 248 [0xf8]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 6681210304 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (248 [0xf8] vs 15 [0xf]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 6681270304 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/16
  UVM_INFO @ 6692700304 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/16
  UVM_INFO @ 6731260304 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 61/166

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test uart_intr has 2 failures.
  - 11.uart_intr.77231209125241461141813669582914718815164643006348960572411718655005868776782
    Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.uart_intr.18707269701442222257321092642320322423421353962761233761765550170272016665669
    Line 313, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test uart_intr has 2 failures.
  - 33.uart_intr.85584380412179188778790211999796749090194156231114127653946595605491167711714
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/33.uart_intr/latest/run.log
```
  Job ID: smart:d32b5715-2df2-4580-8812-5bbb243ca976
```
  - 43.uart_intr.66514828890270787591253307137221474365432730582232526946436807062623240572575
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/43.uart_intr/latest/run.log
```
  Job ID: smart:e5084b76-b056-4208-a724-7d7e203d937f
```

UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_perf has 1 failures.

27.uart_perf.9600340299045415905745695046576298816777932599936193550745121279994852493172
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_perf/latest/run.log

  UVM_ERROR @  17417580 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_INFO @ 648252175 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/5
  UVM_INFO @ 3502257883 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/5
  UVM_INFO @ 3599758078 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/5
  UVM_INFO @ 11166924087 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/5

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:

Test uart_stress_all has 1 failures.

35.uart_stress_all.93659183207446047442218876776795713521679772906909025557079700301883121405791
Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_stress_all/latest/run.log

  UVM_ERROR @ 9606581174 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 9606581174 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 9625810113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---