UART Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	30.710s	5.997ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.160s	1.032ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.690s	54.244us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.460s	175.629us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	125.550us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.450s	30.475us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	54.244us	20	20	100.00
		uart_csr_aliasing	0.700s	125.550us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.894m	78.042ms	50	50	100.00
V2	parity	uart_smoke	30.710s	5.997ms	50	50	100.00
		uart_tx_rx	4.894m	78.042ms	50	50	100.00
V2	parity_error	uart_intr	55.138m	2.468s	48	50	96.00
		uart_rx_parity_err	8.200m	240.029ms	50	50	100.00
V2	watermark	uart_tx_rx	4.894m	78.042ms	50	50	100.00
		uart_intr	55.138m	2.468s	48	50	96.00
V2	fifo_full	uart_fifo_full	7.020m	320.196ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	12.534m	245.283ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.254m	289.365ms	300	300	100.00
V2	rx_frame_err	uart_intr	55.138m	2.468s	48	50	96.00
V2	rx_break_err	uart_intr	55.138m	2.468s	48	50	96.00
V2	rx_timeout	uart_intr	55.138m	2.468s	48	50	96.00
V2	perf	uart_perf	27.680m	33.158ms	49	50	98.00
V2	sys_loopback	uart_loopback	30.140s	6.039ms	47	50	94.00
V2	line_loopback	uart_loopback	30.140s	6.039ms	47	50	94.00
V2	rx_noise_filter	uart_noise_filter	3.526m	98.222ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	55.120s	33.356ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	27.330s	12.818ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	38.790s	3.758ms	37	50	74.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.467m	164.940ms	50	50	100.00
V2	stress_all	uart_stress_all	35.560m	89.640ms	47	50	94.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	31.943m	57.750ms	95	100	95.00
V2	alert_test	uart_alert_test	0.610s	14.265us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	34.514us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.130s	415.737us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.130s	415.737us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.160s	1.032ms	5	5	100.00
		uart_csr_rw	0.690s	54.244us	20	20	100.00
		uart_csr_aliasing	0.700s	125.550us	5	5	100.00
		uart_same_csr_outstanding	0.840s	66.152us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.160s	1.032ms	5	5	100.00
		uart_csr_rw	0.690s	54.244us	20	20	100.00
		uart_csr_aliasing	0.700s	125.550us	5	5	100.00
		uart_same_csr_outstanding	0.840s	66.152us	20	20	100.00
V2		TOTAL			1163	1190	97.73
V2S	tl_intg_err	uart_sec_cm	0.860s	153.178us	5	5	100.00
		uart_tl_intg_err	1.500s	86.199us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.500s	86.199us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1293	1320	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	13	68.42
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.30	99.79	98.45	100.00	--	99.76	100.00	97.77

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 13 failures:

Test uart_rx_oversample has 13 failures.

0.uart_rx_oversample.29070759582069936421935182885606980735255391802883279431641272489806044795626
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 332914514 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (62343 [0xf387] vs 62347 [0xf38b]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 370030340 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/6
  UVM_INFO @ 668994757 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/6
  UVM_ERROR @ 669914177 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (48319 [0xbcbf] vs 24159 [0x5e5f]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 702744293 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/6

6.uart_rx_oversample.102281710410310630708724848072650546813853872191585097692751915078854165564212
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 145080303 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (63745 [0xf901] vs 62209 [0xf301]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 153488997 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/3
  UVM_ERROR @ 153730303 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (31238 [0x7a06] vs 27141 [0x6a05]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 171680303 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (32177 [0x7db1] vs 48856 [0xbed8]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 180380303 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (50105 [0xc3b9] vs 57816 [0xe1d8]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 11 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 8 failures:

Test uart_stress_all has 3 failures.

9.uart_stress_all.75653328458920993900090940738267746384149958306881911390145338035758896673644
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_stress_all/latest/run.log

  UVM_ERROR @ 1149518347 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (204 [0xcc] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 1149518347 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 204 [0xcc]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 1149768349 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/3
  UVM_INFO @ 1230268993 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/3
  UVM_ERROR @ 1250352487 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr

13.uart_stress_all.96802227128568272598699345388498839856260952847856323080434016107562608244664
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_stress_all/latest/run.log

  UVM_ERROR @ 833940501 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 833940501 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 3 [0x3]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 834003003 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/17
  UVM_INFO @ 2178660614 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/17
  UVM_INFO @ 2503441840 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/17

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 3 failures.

20.uart_stress_all_with_rand_reset.111365793555884596543475120167919725345693699934545316768183845166682223133231
Line 803, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33713560181 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (120 [0x78] vs 188 [0xbc]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 33713560181 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (188 [0xbc] vs 120 [0x78]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 33713622683 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 18/19
  UVM_INFO @ 33746467484 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 130/910
  UVM_INFO @ 33797250359 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 131/910

68.uart_stress_all_with_rand_reset.69439161041598110876197632603010234097041828500145671214449491467451096882213
Line 471, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 141923974717 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (121 [0x79] vs 203 [0xcb]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 141923974717 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (203 [0xcb] vs 121 [0x79]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 141924574717 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/11
  UVM_INFO @ 141969174717 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/416
  UVM_INFO @ 142447674717 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/416

... and 1 more failures.

Test uart_loopback has 2 failures.

22.uart_loopback.34880161468988368572876904424074373517224883832682104737274598404643968136645
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_loopback/latest/run.log

  UVM_ERROR @ 1474925284 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (253 [0xfd] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 1474925284 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 253 [0xfd]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 1475055718 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/4
  UVM_INFO @ 1517685897 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/4
  UVM_ERROR @ 1526794538 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr

42.uart_loopback.55548270381955778539045736221882509488976741962920661534587227642015864560165
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/42.uart_loopback/latest/run.log

  UVM_ERROR @ 2518787164 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (34 [0x22] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 2518787164 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 34 [0x22]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_ERROR @ 2518827164 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
  UVM_INFO @ 2518847164 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/9
  UVM_INFO @ 4121187164 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/9

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 2 failures:

Test uart_perf has 1 failures.

7.uart_perf.108069926372937476855315317245094399591318478541822094441522111426115519652216
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_perf/latest/run.log

  UVM_ERROR @   1392455 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 111911586 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/10
  UVM_INFO @ 3206370492 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/10
  UVM_INFO @ 3378531935 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/10
  UVM_INFO @ 4390717736 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/10

Test uart_stress_all_with_rand_reset has 1 failures.

67.uart_stress_all_with_rand_reset.2985893495698200865030883257374817399720651058126694687670085903782944000099
Line 458, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 60468997942 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @ 60561517942 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 60665237942 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/42
  UVM_INFO @ 60880797942 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/42
  UVM_INFO @ 61041797942 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/42

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

25.uart_stress_all_with_rand_reset.43519009132280093497994627884251513220244112419950543548904181396353734644454
Line 399, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 35034984788 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 35121944788 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 91/296
  UVM_INFO @ 35412864788 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 92/296
  UVM_INFO @ 35692064788 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 93/296
  UVM_INFO @ 35922664788 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 94/296

Test uart_loopback has 1 failures.

45.uart_loopback.29396720802374312648804420302468738625234185822047391133117074866103583479911
Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_loopback/latest/run.log

  UVM_ERROR @ 7456194557 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 7461234557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_intr has 1 failures.
  - 26.uart_intr.23923620672258109704076840843190473912641148176684885297936178654206804984058
    Line 315, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 36.uart_intr.22337047787084152195552926170505642993273955777176465301812848807281980822223
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_intr/latest/run.log
```
  Job ID: smart:ff4e4387-115a-48bf-bb33-1b264405c0ac
```