UART Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	46.590s	5.875ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	59.132us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	17.282us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.590s	4.970ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	47.151us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.350s	25.812us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	17.282us	20	20	100.00
		uart_csr_aliasing	0.800s	47.151us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.258m	136.294ms	50	50	100.00
V2	parity	uart_smoke	46.590s	5.875ms	50	50	100.00
		uart_tx_rx	5.258m	136.294ms	50	50	100.00
V2	parity_error	uart_intr	52.347m	1.966s	45	50	90.00
		uart_rx_parity_err	9.388m	232.082ms	50	50	100.00
V2	watermark	uart_tx_rx	5.258m	136.294ms	50	50	100.00
		uart_intr	52.347m	1.966s	45	50	90.00
V2	fifo_full	uart_fifo_full	9.354m	223.179ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	6.690m	243.077ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.208m	242.284ms	300	300	100.00
V2	rx_frame_err	uart_intr	52.347m	1.966s	45	50	90.00
V2	rx_break_err	uart_intr	52.347m	1.966s	45	50	90.00
V2	rx_timeout	uart_intr	52.347m	1.966s	45	50	90.00
V2	perf	uart_perf	23.392m	22.965ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.110s	14.264ms	45	50	90.00
V2	line_loopback	uart_loopback	27.110s	14.264ms	45	50	90.00
V2	rx_noise_filter	uart_noise_filter	4.675m	117.624ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.297m	45.263ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	24.140s	6.587ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	43.260s	5.045ms	42	50	84.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.758m	95.723ms	50	50	100.00
V2	stress_all	uart_stress_all	2.286h	4.781s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	42.898m	280.517ms	95	100	95.00
V2	alert_test	uart_alert_test	0.680s	14.623us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	11.269us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.820s	585.961us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.820s	585.961us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	59.132us	5	5	100.00
		uart_csr_rw	0.680s	17.282us	20	20	100.00
		uart_csr_aliasing	0.800s	47.151us	5	5	100.00
		uart_same_csr_outstanding	0.850s	66.403us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	59.132us	5	5	100.00
		uart_csr_rw	0.680s	17.282us	20	20	100.00
		uart_csr_aliasing	0.800s	47.151us	5	5	100.00
		uart_same_csr_outstanding	0.850s	66.403us	20	20	100.00
V2		TOTAL			1166	1190	97.98
V2S	tl_intg_err	uart_sec_cm	1.210s	587.084us	5	5	100.00
		uart_tl_intg_err	1.480s	339.018us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.480s	339.018us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1296	1320	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	14	73.68
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.79	98.45	100.00	--	99.76	100.00	97.44

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 8 failures:

Test uart_rx_oversample has 8 failures.

2.uart_rx_oversample.103230929506001982638644436670532376622107965265989077792435347718058163702350
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_rx_oversample/latest/run.log

  UVM_ERROR @  52679214 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (16504 [0x4078] vs 16506 [0x407a]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  60893721 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/12
  UVM_ERROR @  61315569 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (41989 [0xa405] vs 54917 [0xd685]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  97392435 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/12
  UVM_INFO @ 125530020 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/12

15.uart_rx_oversample.61569571624954323571489810391876739431555116824425612788363345967717986017152
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 137428198 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (15168 [0x3b40] vs 39328 [0x99a0]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 145720562 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/3
  UVM_ERROR @ 146071107 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (12536 [0x30f8] vs 10612 [0x2974]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 467152136 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/3
  UVM_INFO @ 1652437258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 7 failures:

Test uart_loopback has 3 failures.

1.uart_loopback.95429869165819003298013160943586553826079760237346328719217566890800941828314
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_loopback/latest/run.log

  UVM_ERROR @ 2304366007 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (71 [0x47] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 2304366007 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 71 [0x47]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 2304428509 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/11
  UVM_INFO @ 2931261067 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/11
  UVM_INFO @ 3421735095 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/11

19.uart_loopback.89931220236503479787509332413590604777655222695304030128593657601617373899824
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_loopback/latest/run.log

  UVM_ERROR @ 5133563571 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60 [0x3c] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 5133563571 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 60 [0x3c]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 5133790369 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/17
  UVM_INFO @ 5209489356 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/17
  UVM_INFO @ 6159638959 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/17

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 4 failures.

18.uart_stress_all_with_rand_reset.3466783427921161641253161634721156191142681651177307577330745212043140037816
Line 426, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 51094241640 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (162 [0xa2] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 51094241640 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 162 [0xa2]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 51094783311 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 14/20
  UVM_INFO @ 52136708313 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 15/20
  UVM_INFO @ 52188750396 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 16/20

35.uart_stress_all_with_rand_reset.55904721018176551073089785813743407453584751750745601359605734403360554593395
Line 730, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 293171285922 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (25 [0x19] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 293171285922 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 25 [0x19]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 293171885922 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 16/18
  UVM_INFO @ 293232585922 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 17/18
  UVM_INFO @ 293608685922 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 41/346

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test uart_intr has 3 failures.
  - 1.uart_intr.81986507881353204346202337671512067509189215634492476674294375495481119905383
    Line 309, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.uart_intr.91388797241456396114515969664779762650099714901977381169359399122386292269535
    Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_loopback has 2 failures.

0.uart_loopback.97348582029471539507896188449278052337658799154434506804967237552264314954587
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_loopback/latest/run.log

  UVM_ERROR @ 7208839441 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 7213880257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.uart_loopback.8841330199980866630851163371972485529301835995074020420260426747788734313626
Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_loopback/latest/run.log

  UVM_ERROR @ 14259354168 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 14259354168 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 14264394168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test uart_intr has 2 failures.
  - 37.uart_intr.32298846595386692541799511541001679828549395713855822335081281529157462246752
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_intr/latest/run.log
```
  Job ID: smart:d3534b9e-8fd3-41fe-983b-6f2120b27137
```
  - 45.uart_intr.30400699846139812877955357656338544513762923675596466736127103611556893713452
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_intr/latest/run.log
```
  Job ID: smart:8a3afd84-fd18-40b1-926b-21a78b49e700
```

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_fifo_full has 1 failures.

13.uart_fifo_full.20954160716085552297775373896667024361295824989156263047197369403714630394659
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_fifo_full/latest/run.log

  UVM_ERROR @   1369926 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 14164209926 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 1/7
  UVM_INFO @ 14657929926 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 2/7
  UVM_INFO @ 15266189926 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 3/7
  UVM_INFO @ 21576359926 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 4/7

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

84.uart_stress_all_with_rand_reset.35253101064263258541710663196607815777079537948990212630193038123062362120430
Line 767, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 321685052442 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 321852801771 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 322020051102 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 322186467103 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 322352966437 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])