4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | uart_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | uart_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | uart_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | uart_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0 | 20 | 0.00 | ||
| uart_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | base_random_seq | uart_tx_rx | 0 | 50 | 0.00 | ||
| V2 | parity | uart_smoke | 0 | 50 | 0.00 | ||
| uart_tx_rx | 0 | 50 | 0.00 | ||||
| V2 | parity_error | uart_intr | 0 | 50 | 0.00 | ||
| uart_rx_parity_err | 0 | 50 | 0.00 | ||||
| V2 | watermark | uart_tx_rx | 0 | 50 | 0.00 | ||
| uart_intr | 0 | 50 | 0.00 | ||||
| V2 | fifo_full | uart_fifo_full | 0 | 50 | 0.00 | ||
| V2 | fifo_overflow | uart_fifo_overflow | 0 | 50 | 0.00 | ||
| V2 | fifo_reset | uart_fifo_reset | 0 | 300 | 0.00 | ||
| V2 | rx_frame_err | uart_intr | 0 | 50 | 0.00 | ||
| V2 | rx_break_err | uart_intr | 0 | 50 | 0.00 | ||
| V2 | rx_timeout | uart_intr | 0 | 50 | 0.00 | ||
| V2 | perf | uart_perf | 0 | 50 | 0.00 | ||
| V2 | sys_loopback | uart_loopback | 0 | 50 | 0.00 | ||
| V2 | line_loopback | uart_loopback | 0 | 50 | 0.00 | ||
| V2 | rx_noise_filter | uart_noise_filter | 0 | 50 | 0.00 | ||
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 0 | 50 | 0.00 | ||
| V2 | tx_overide | uart_tx_ovrd | 0 | 50 | 0.00 | ||
| V2 | rx_oversample | uart_rx_oversample | 0 | 50 | 0.00 | ||
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 0 | 50 | 0.00 | ||
| V2 | stress_all | uart_stress_all | 0 | 50 | 0.00 | ||
| V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| V2 | alert_test | uart_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | uart_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | uart_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | uart_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0 | 5 | 0.00 | ||
| uart_csr_rw | 0 | 20 | 0.00 | ||||
| uart_csr_aliasing | 0 | 5 | 0.00 | ||||
| uart_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0 | 5 | 0.00 | ||
| uart_csr_rw | 0 | 20 | 0.00 | ||||
| uart_csr_aliasing | 0 | 5 | 0.00 | ||||
| uart_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1190 | 0.00 | |||
| V2S | tl_intg_err | uart_sec_cm | 0 | 5 | 0.00 | ||
| uart_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 1320 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 19 | 19 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1322 failures:
0.uart_smoke.54159076003668459666258246951304820029962441948227205235526412296264218949811
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_smoke/latest/run.log
1.uart_smoke.11860062757945733128809731693862270284280258368589137655981223700009480163247
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_smoke/latest/run.log
... and 48 more failures.
0.uart_tx_rx.50963762746482181799911213708680820384993053394338563446529012688170289731624
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_tx_rx/latest/run.log
1.uart_tx_rx.9724413240493824426923303698371723256227869781519869932647212515470813264696
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_tx_rx/latest/run.log
... and 48 more failures.
0.uart_fifo_full.32402307587329133690744000907925012239545525805501409979450141740284386975470
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_fifo_full/latest/run.log
1.uart_fifo_full.1465671524805365850681697736473753745240237559362666236586791945958818492663
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_fifo_full/latest/run.log
... and 48 more failures.
0.uart_fifo_overflow.114626131760962620755396057729176199315613225318720887825363658765436481457342
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_fifo_overflow/latest/run.log
1.uart_fifo_overflow.65371383692385704153742363696094173608259674698357819701631368866596449322801
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_fifo_overflow/latest/run.log
... and 48 more failures.
0.uart_fifo_reset.51558719993223809648824228958652116758999830846932461544629050278138557928676
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_fifo_reset/latest/run.log
1.uart_fifo_reset.77911118534895260446993678864367191767743396130680412412518497887796985474588
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_fifo_reset/latest/run.log
... and 298 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.