UART Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	27.530s	6.000ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.660s	92.922us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	13.914us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.600s	262.729us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	61.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.480s	102.164us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	13.914us	20	20	100.00
		uart_csr_aliasing	0.810s	61.792us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.921m	63.301ms	50	50	100.00
V2	parity	uart_smoke	27.530s	6.000ms	50	50	100.00
		uart_tx_rx	3.921m	63.301ms	50	50	100.00
V2	parity_error	uart_intr	45.958m	1.217s	49	50	98.00
		uart_rx_parity_err	7.853m	235.531ms	50	50	100.00
V2	watermark	uart_tx_rx	3.921m	63.301ms	50	50	100.00
		uart_intr	45.958m	1.217s	49	50	98.00
V2	fifo_full	uart_fifo_full	12.998m	376.757ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	6.076m	281.644ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.387m	107.838ms	300	300	100.00
V2	rx_frame_err	uart_intr	45.958m	1.217s	49	50	98.00
V2	rx_break_err	uart_intr	45.958m	1.217s	49	50	98.00
V2	rx_timeout	uart_intr	45.958m	1.217s	49	50	98.00
V2	perf	uart_perf	26.172m	30.593ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.810s	7.203ms	43	50	86.00
V2	line_loopback	uart_loopback	24.810s	7.203ms	43	50	86.00
V2	rx_noise_filter	uart_noise_filter	6.327m	132.792ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	59.000s	37.470ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	40.570s	12.981ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	39.960s	4.131ms	41	50	82.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.917m	190.513ms	50	50	100.00
V2	stress_all	uart_stress_all	1.561h	4.277s	48	50	96.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	23.445m	80.296ms	98	100	98.00
V2	alert_test	uart_alert_test	0.610s	63.654us	50	50	100.00
V2	intr_test	uart_intr_test	0.670s	53.877us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.780s	620.003us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.780s	620.003us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.660s	92.922us	5	5	100.00
		uart_csr_rw	0.650s	13.914us	20	20	100.00
		uart_csr_aliasing	0.810s	61.792us	5	5	100.00
		uart_same_csr_outstanding	0.810s	49.948us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.660s	92.922us	5	5	100.00
		uart_csr_rw	0.650s	13.914us	20	20	100.00
		uart_csr_aliasing	0.810s	61.792us	5	5	100.00
		uart_same_csr_outstanding	0.810s	49.948us	20	20	100.00
V2		TOTAL			1167	1190	98.07
V2S	tl_intg_err	uart_sec_cm	0.890s	1.027ms	5	5	100.00
		uart_tl_intg_err	1.410s	109.908us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	109.908us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1297	1320	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	12	63.16
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.79	98.45	100.00	--	99.76	100.00	97.48

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 9 failures:

Test uart_rx_oversample has 9 failures.

12.uart_rx_oversample.47484710999241102974940090093251389671474508786395338902753633080898714313375
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 240048271 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (53742 [0xd1ee] vs 54762 [0xd5ea]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 248496025 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/16
  UVM_INFO @ 649108412 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/16
  UVM_INFO @ 675928243 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/16
  UVM_INFO @ 710652125 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/16

14.uart_rx_oversample.109709286587446811248463491270416984473181814518058452677595218540998838014571
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 395113911 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (25999 [0x658f] vs 45767 [0xb2c7]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 430622679 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/15
  UVM_INFO @ 447970170 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/15
  UVM_INFO @ 758344307 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/15
  UVM_INFO @ 784611687 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 8/15

... and 7 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 8 failures:

Test uart_stress_all has 1 failures.

4.uart_stress_all.85978193335378191004205978383026065900043567655525034031923499074810913857432
Line 271, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_stress_all/latest/run.log

  UVM_ERROR @ 56677266520 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (177 [0xb1] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 56677266520 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 177 [0xb1]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 56677808191 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/13
  UVM_INFO @ 57683941240 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/13
  UVM_INFO @ 58646573941 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/13

Test uart_loopback has 5 failures.

8.uart_loopback.36372355943004743715840788643877524313926559181758386560924111103810642573495
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_loopback/latest/run.log

  UVM_ERROR @ 1645871870 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 1645871870 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 7 [0x7]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 1646797795 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/10
  UVM_INFO @ 1660834818 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/10
  UVM_INFO @ 2071575148 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/10

22.uart_loopback.11681610657348446454794932880681902686880797169308160000649055182245835836620
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_loopback/latest/run.log

  UVM_ERROR @ 2937800252 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (163 [0xa3] vs 141 [0x8d]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 2937800252 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (141 [0x8d] vs 163 [0xa3]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 2937980252 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/18
  UVM_INFO @ 2946960252 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/18
  UVM_INFO @ 3807620252 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/18

... and 3 more failures.

Test uart_stress_all_with_rand_reset has 2 failures.

11.uart_stress_all_with_rand_reset.86859365902723455814456749261354817487706437386661152056263305207312715373966
Line 565, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22389055227 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 129 [0x81]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 22389055227 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (129 [0x81] vs 2 [0x2]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 22389115227 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/15
  UVM_INFO @ 23005305227 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/15
  UVM_INFO @ 24166085227 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 13/15

16.uart_stress_all_with_rand_reset.28030050138168129394442049013125437777054147329614499466033383769604216983447
Line 1090, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 117777330562 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (29 [0x1d] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 117777330562 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 29 [0x1d]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 117777466924 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 17/19
  UVM_INFO @ 117786603178 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 64/124
  UVM_INFO @ 117789057694 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 18/19

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 3 failures:

Test uart_stress_all has 1 failures.

18.uart_stress_all.30242800995934233616529316592300672576625895966757278386833698580995946072809
Line 273, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_stress_all/latest/run.log

  UVM_ERROR @ 12899749902 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 55227999902 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/5
  UVM_INFO @ 55504374902 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/5
  UVM_INFO @ 57892874902 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/5
  UVM_INFO @ 106636249902 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 4/5

Test uart_loopback has 2 failures.

21.uart_loopback.91211455083696877598454009285257717781136047831033733755554228323954265190893
Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_loopback/latest/run.log

  UVM_ERROR @ 11803624492 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 11809541155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.uart_loopback.96591251301162083229006988080283469466486838950857086495927555964896844328035
Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_loopback/latest/run.log

  UVM_ERROR @ 7198339975 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 7203381211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_fifo_full has 1 failures.

6.uart_fifo_full.34905312326876296101012554393003586891111033498613506362963484931963785619363
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_fifo_full/latest/run.log

  UVM_ERROR @   8649545 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 36281649545 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 1/7
  UVM_INFO @ 37657889545 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 2/7
  UVM_INFO @ 82021689545 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 3/7
  UVM_INFO @ 90562569545 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 4/7

UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_noise_filter has 1 failures.

13.uart_noise_filter.69445561809368321653707799606016526410573913649035148960885508675788463237386
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_noise_filter/latest/run.log

  UVM_ERROR @   1195904 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_INFO @ 308074216 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/2
  UVM_INFO @ 2938446493 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/2
  UVM_INFO @ 5705114194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_intr has 1 failures.

33.uart_intr.90696764503968732962005933291068613730611496675194914049885518544578482322976
Line 269, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/33.uart_intr/latest/run.log

  UVM_ERROR @ 24862378107 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 24989478107 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 25079578107 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark