UART Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	25.180s	11.586ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	15.786us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.700s	54.733us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.660s	145.600us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	37.572us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.240s	84.508us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.700s	54.733us	20	20	100.00
		uart_csr_aliasing	0.750s	37.572us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.849m	155.220ms	50	50	100.00
V2	parity	uart_smoke	25.180s	11.586ms	50	50	100.00
		uart_tx_rx	6.849m	155.220ms	50	50	100.00
V2	parity_error	uart_intr	41.972m	1.519s	49	50	98.00
		uart_rx_parity_err	10.662m	177.225ms	50	50	100.00
V2	watermark	uart_tx_rx	6.849m	155.220ms	50	50	100.00
		uart_intr	41.972m	1.519s	49	50	98.00
V2	fifo_full	uart_fifo_full	8.478m	261.547ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	30.430m	290.583ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.505m	115.643ms	300	300	100.00
V2	rx_frame_err	uart_intr	41.972m	1.519s	49	50	98.00
V2	rx_break_err	uart_intr	41.972m	1.519s	49	50	98.00
V2	rx_timeout	uart_intr	41.972m	1.519s	49	50	98.00
V2	perf	uart_perf	26.442m	29.482ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.530s	9.278ms	45	50	90.00
V2	line_loopback	uart_loopback	25.530s	9.278ms	45	50	90.00
V2	rx_noise_filter	uart_noise_filter	5.324m	162.132ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.124m	43.037ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.290s	6.866ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	47.760s	5.899ms	42	50	84.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.486m	176.764ms	50	50	100.00
V2	stress_all	uart_stress_all	1.057h	872.590ms	45	50	90.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	26.482m	222.431ms	99	100	99.00
V2	alert_test	uart_alert_test	0.610s	32.402us	50	50	100.00
V2	intr_test	uart_intr_test	0.610s	17.042us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.200s	42.845us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.200s	42.845us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	15.786us	5	5	100.00
		uart_csr_rw	0.700s	54.733us	20	20	100.00
		uart_csr_aliasing	0.750s	37.572us	5	5	100.00
		uart_same_csr_outstanding	0.780s	60.678us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	15.786us	5	5	100.00
		uart_csr_rw	0.700s	54.733us	20	20	100.00
		uart_csr_aliasing	0.750s	37.572us	5	5	100.00
		uart_same_csr_outstanding	0.780s	60.678us	20	20	100.00
V2		TOTAL			1169	1190	98.24
V2S	tl_intg_err	uart_sec_cm	0.940s	522.853us	5	5	100.00
		uart_tl_intg_err	1.490s	306.297us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.490s	306.297us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1299	1320	98.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	13	68.42
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.79	98.45	100.00	--	99.76	100.00	97.61

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 8 failures:

Test uart_rx_oversample has 8 failures.

6.uart_rx_oversample.54465440641706424719229026853165332552040281065138081324323484049547718152283
Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 509193896 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (25555 [0x63d3] vs 12777 [0x31e9]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 536022104 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/7
  UVM_INFO @ 852882469 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/7
  UVM_INFO @ 2034372724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.uart_rx_oversample.52560496515657204570337120851296441311927979919236732240450311476753749135701
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 774545780 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (42785 [0xa721] vs 54160 [0xd390]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 792440660 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (40944 [0x9ff0] vs 39924 [0x9bf4]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 801124940 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (64992 [0xfde0] vs 30434 [0x76e2]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 809541386 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/18
  UVM_ERROR @ 809861852 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (2684 [0xa7c] vs 5721 [0x1659]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 6 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 6 failures:

Test uart_stress_all has 3 failures.

5.uart_stress_all.56026716140806930821685546508022213153752216639663677182242208086115128838272
Line 272, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_stress_all/latest/run.log

  UVM_ERROR @ 93879454334 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (217 [0xd9] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 93879454334 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 217 [0xd9]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 93879564334 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/16
  UVM_INFO @ 94369664334 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/16
  UVM_INFO @ 95215214334 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 13/16

30.uart_stress_all.103290227888686379531760716113914438559054658346529347080615983145895888764881
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_stress_all/latest/run.log

  UVM_ERROR @ 1019916948 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (210 [0xd2] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 1019916948 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 210 [0xd2]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 1020389174 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/2
  UVM_ERROR @ 1032194824 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 1032194824 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr

... and 1 more failures.

Test uart_loopback has 3 failures.

9.uart_loopback.39939880038476871853444975675992481563062025399298859776826782056640167931331
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_loopback/latest/run.log

  UVM_ERROR @ 7178751534 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (233 [0xe9] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 7178751534 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 233 [0xe9]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 7178973756 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/16
  UVM_INFO @ 7261788488 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/16
  UVM_INFO @ 8404268827 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/16

23.uart_loopback.77781386049909665443986668554145820775520912374833852694297772710693153261867
Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_loopback/latest/run.log

  UVM_ERROR @ 3879328234 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (145 [0x91] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 3879328234 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 145 [0x91]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 3879388234 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/12
  UVM_INFO @ 3921288234 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/12
  UVM_INFO @ 4820028234 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/12

... and 1 more failures.

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 3 failures:

Test uart_loopback has 2 failures.

4.uart_loopback.50841850279616465767846192974710874295839151343896319030224373924041588526560
Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_loopback/latest/run.log

  UVM_ERROR @ 8318798957 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 8318798957 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 8323839361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.uart_loopback.110560064893497880404287978558651670737876396302632402920825988127769255093220
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_loopback/latest/run.log

  UVM_ERROR @ 9710405381 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 9715605381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_stress_all has 1 failures.

16.uart_stress_all.3789610443489756080588676944348828014840918705909402193305422652601540865752
Line 282, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_stress_all/latest/run.log

  UVM_ERROR @ 317089825037 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 320112985037 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_start_bit_filter_vseq] finished run 1/2
  UVM_INFO @ 324748025037 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_start_bit_filter_vseq] finished run 2/2
  UVM_INFO @ 324796625037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 2 failures:

Test uart_intr has 1 failures.

47.uart_intr.37110274744253626580508277499468183503925027341162959311591639806467389365715
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_intr/latest/run.log

  UVM_ERROR @ 89283205041 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 89283205041 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: TxWatermark/0, en_intr: bb
  UVM_INFO @ 89625633270 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 89805775947 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all_with_rand_reset has 1 failures.

89.uart_stress_all_with_rand_reset.98366661650483800455991939048242890486447183830411289020766907430742052271611
Line 367, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 105242066147 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 105719266147 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 106192466147 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 106612666147 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 32/620
  UVM_ERROR @ 106669666147 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_ERROR (uart_scoreboard.sv:380) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all has 1 failures.

36.uart_stress_all.4848953930750708927384986256790501555857395461533763620037666376521212171533
Line 267, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all/latest/run.log

  UVM_ERROR @ 252502852981 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 252533676757 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 253229682325 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 257005241941 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/10
  UVM_INFO @ 266910497653 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/10

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_full has 1 failures.
  - 40.uart_fifo_full.100989686467045053117370273314863314767799469120128413656342836393517860948069
    Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_fifo_full/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```