93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | uart_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | uart_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | uart_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | uart_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0 | 20 | 0.00 | ||
| uart_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | base_random_seq | uart_tx_rx | 0 | 50 | 0.00 | ||
| V2 | parity | uart_smoke | 0 | 50 | 0.00 | ||
| uart_tx_rx | 0 | 50 | 0.00 | ||||
| V2 | parity_error | uart_intr | 0 | 50 | 0.00 | ||
| uart_rx_parity_err | 0 | 50 | 0.00 | ||||
| V2 | watermark | uart_tx_rx | 0 | 50 | 0.00 | ||
| uart_intr | 0 | 50 | 0.00 | ||||
| V2 | fifo_full | uart_fifo_full | 0 | 50 | 0.00 | ||
| V2 | fifo_overflow | uart_fifo_overflow | 0 | 50 | 0.00 | ||
| V2 | fifo_reset | uart_fifo_reset | 0 | 300 | 0.00 | ||
| V2 | rx_frame_err | uart_intr | 0 | 50 | 0.00 | ||
| V2 | rx_break_err | uart_intr | 0 | 50 | 0.00 | ||
| V2 | rx_timeout | uart_intr | 0 | 50 | 0.00 | ||
| V2 | perf | uart_perf | 0 | 50 | 0.00 | ||
| V2 | sys_loopback | uart_loopback | 0 | 50 | 0.00 | ||
| V2 | line_loopback | uart_loopback | 0 | 50 | 0.00 | ||
| V2 | rx_noise_filter | uart_noise_filter | 0 | 50 | 0.00 | ||
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 0 | 50 | 0.00 | ||
| V2 | tx_overide | uart_tx_ovrd | 0 | 50 | 0.00 | ||
| V2 | rx_oversample | uart_rx_oversample | 0 | 50 | 0.00 | ||
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 0 | 50 | 0.00 | ||
| V2 | stress_all | uart_stress_all | 0 | 50 | 0.00 | ||
| V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| V2 | alert_test | uart_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | uart_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | uart_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | uart_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0 | 5 | 0.00 | ||
| uart_csr_rw | 0 | 20 | 0.00 | ||||
| uart_csr_aliasing | 0 | 5 | 0.00 | ||||
| uart_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0 | 5 | 0.00 | ||
| uart_csr_rw | 0 | 20 | 0.00 | ||||
| uart_csr_aliasing | 0 | 5 | 0.00 | ||||
| uart_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1190 | 0.00 | |||
| V2S | tl_intg_err | uart_sec_cm | 0 | 5 | 0.00 | ||
| uart_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 1320 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 19 | 19 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1322 failures:
0.uart_smoke.76122474160597164733141262693241563993855383471310744396965796886021628019988
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_smoke/latest/run.log
1.uart_smoke.74828449653975032831744657681702175681574801095872036144166641028507091672748
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_smoke/latest/run.log
... and 48 more failures.
0.uart_tx_rx.30144165991198701862931474604030120256003484206414271390353291662705418926780
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_tx_rx/latest/run.log
1.uart_tx_rx.96045778149791656132892281453892986358026730757892173540701595996513416792038
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_tx_rx/latest/run.log
... and 48 more failures.
0.uart_fifo_full.52513247874610235063835457424926489455388961941682482175324495526958001960607
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_fifo_full/latest/run.log
1.uart_fifo_full.78249883727905598448905028923089434781211786370613096644547383470321747559005
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_fifo_full/latest/run.log
... and 48 more failures.
0.uart_fifo_overflow.100366584770665108313553418142309187503646490715403371162307851280607034677089
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_fifo_overflow/latest/run.log
1.uart_fifo_overflow.114698893776525568371984959807011700281540110344332915877779129204343618369849
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_fifo_overflow/latest/run.log
... and 48 more failures.
0.uart_fifo_reset.72493302676258267981522960591133152710661164670072707865949889054365344504107
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_fifo_reset/latest/run.log
1.uart_fifo_reset.45428219799802238604646529587852095767723855268828338854518227334721498539482
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_fifo_reset/latest/run.log
... and 298 more failures.
Job uart-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/default/build.log
Job ID: smart:067f0969-2eb2-4dc9-8e41-379e497783f2
Job uart-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/cover_reg_top/build.log
Job ID: smart:3756e49b-9263-44de-9298-17cac29b4ecb