8faf04697a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 45.610s | 5.996ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 1.310s | 1.051ms | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.690s | 27.672us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.620s | 2.716ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 0.690s | 21.000us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 2.640s | 204.822us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.690s | 27.672us | 20 | 20 | 100.00 |
| uart_csr_aliasing | 0.690s | 21.000us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | base_random_seq | uart_tx_rx | 3.884m | 107.187ms | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 45.610s | 5.996ms | 50 | 50 | 100.00 |
| uart_tx_rx | 3.884m | 107.187ms | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 59.169m | 2.537s | 46 | 50 | 92.00 |
| uart_rx_parity_err | 7.000m | 220.384ms | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 3.884m | 107.187ms | 50 | 50 | 100.00 |
| uart_intr | 59.169m | 2.537s | 46 | 50 | 92.00 | ||
| V2 | fifo_full | uart_fifo_full | 7.304m | 289.505ms | 50 | 50 | 100.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 7.600m | 299.493ms | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 7.988m | 222.452ms | 300 | 300 | 100.00 |
| V2 | rx_frame_err | uart_intr | 59.169m | 2.537s | 46 | 50 | 92.00 |
| V2 | rx_break_err | uart_intr | 59.169m | 2.537s | 46 | 50 | 92.00 |
| V2 | rx_timeout | uart_intr | 59.169m | 2.537s | 46 | 50 | 92.00 |
| V2 | perf | uart_perf | 21.317m | 25.715ms | 50 | 50 | 100.00 |
| V2 | sys_loopback | uart_loopback | 26.900s | 10.512ms | 44 | 50 | 88.00 |
| V2 | line_loopback | uart_loopback | 26.900s | 10.512ms | 44 | 50 | 88.00 |
| V2 | rx_noise_filter | uart_noise_filter | 6.262m | 176.356ms | 49 | 50 | 98.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 2.122m | 87.145ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 21.210s | 7.148ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 41.260s | 4.495ms | 41 | 50 | 82.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 19.024m | 168.565ms | 50 | 50 | 100.00 |
| V2 | stress_all | uart_stress_all | 28.600m | 2.449s | 48 | 50 | 96.00 |
| V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 33.980m | 77.286ms | 63 | 100 | 63.00 |
| V2 | alert_test | uart_alert_test | 0.620s | 43.043us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 0.650s | 16.322us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 2.470s | 1.438ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 2.470s | 1.438ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 1.310s | 1.051ms | 5 | 5 | 100.00 |
| uart_csr_rw | 0.690s | 27.672us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.690s | 21.000us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.800s | 18.361us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 1.310s | 1.051ms | 5 | 5 | 100.00 |
| uart_csr_rw | 0.690s | 27.672us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.690s | 21.000us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.800s | 18.361us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1131 | 1190 | 95.04 | |||
| V2S | tl_intg_err | uart_sec_cm | 0.870s | 234.773us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.360s | 251.130us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.360s | 251.130us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 1261 | 1320 | 95.53 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 19 | 19 | 13 | 68.42 |
| V2S | 2 | 2 | 2 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.25 | 99.79 | 98.45 | 100.00 | -- | 99.76 | 100.00 | 97.48 |
UVM_ERROR (cip_base_vseq.sv:756) [uart_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 25 failures:
0.uart_stress_all_with_rand_reset.93696887767693299893378034029300919609348438163404167944105379986939485321274
Line 627, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24662826271 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_ERROR @ 24662833627 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 24662833627 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 4/5
UVM_INFO @ 24662833627 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/5
2.uart_stress_all_with_rand_reset.107467866908318442009744348807457443248489150928084157933569331919313072565959
Line 903, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 160108623217 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_ERROR @ 160108650572 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 160108650572 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 8/10
UVM_INFO @ 160108650572 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/10
... and 23 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 9 failures:
4.uart_rx_oversample.93542296496921355937801544851522217319463604302956299883709998438020741649370
Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_rx_oversample/latest/run.log
UVM_ERROR @ 1915940078 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (28402 [0x6ef2] vs 56802 [0xdde2]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 2967213952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.uart_rx_oversample.27886299000355706382507507725150961728492294833565709976833739995980142028532
Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_rx_oversample/latest/run.log
UVM_ERROR @ 2604344118 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (3897 [0xf39] vs 3900 [0xf3c]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 2621936168 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 13/15
UVM_INFO @ 2638756716 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 14/15
UVM_INFO @ 2655029912 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 15/15
UVM_INFO @ 2763802642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 7 more failures.
UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 8 failures:
Test uart_stress_all has 2 failures.
13.uart_stress_all.32159685077866122302319763582903264417624557497057552193685941389387396811017
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_stress_all/latest/run.log
UVM_ERROR @ 682097388 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (122 [0x7a] vs 189 [0xbd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 682097388 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (189 [0xbd] vs 122 [0x7a]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 682347388 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/11
UVM_INFO @ 780257388 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/11
UVM_INFO @ 2250747388 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/11
37.uart_stress_all.11185324241125878480302964591981032716663323842454610035600887111930770594150
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_stress_all/latest/run.log
UVM_ERROR @ 57176819169 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (243 [0xf3] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 57176819169 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 243 [0xf3]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 57176881671 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/15
UVM_INFO @ 57328594859 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 13/15
UVM_INFO @ 57449754986 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 14/15
Test uart_loopback has 4 failures.
31.uart_loopback.18498549266723644323407877658521696749669582760664797420616631308884373353025
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_loopback/latest/run.log
UVM_ERROR @ 1188864247 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (81 [0x51] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1188864247 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 81 [0x51]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 1189104247 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/3
UVM_INFO @ 1273064247 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/3
UVM_ERROR @ 1286084247 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
38.uart_loopback.15430217324573176729694396516998761407441929275923117070818091424542235637309
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_loopback/latest/run.log
UVM_ERROR @ 3854465672 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (227 [0xe3] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3854465672 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 227 [0xe3]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 3854528174 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/9
UVM_ERROR @ 3861590900 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 3861590900 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
... and 2 more failures.
Test uart_stress_all_with_rand_reset has 2 failures.
51.uart_stress_all_with_rand_reset.1083882531692119608209444532626100465544963522163969752250649608911652884535
Line 324, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4146166402 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (154 [0x9a] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4146166402 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 154 [0x9a]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 4146708940 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/18
UVM_INFO @ 4159283056 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/18
UVM_INFO @ 4203249910 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/18
64.uart_stress_all_with_rand_reset.88927604699124648443423259419876162117504257273034682989539106152885023884638
Line 1341, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 450936001306 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 450936001306 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 450936376306 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/11
UVM_INFO @ 451209376306 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/266
UVM_INFO @ 451416001306 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/266
UVM_ERROR (cip_base_vseq.sv:714) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 6 failures:
10.uart_stress_all_with_rand_reset.114185531335141186108389544983473335857122325331262768175695838698399501476011
Line 770, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 41879603481 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 41879603481 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 9/10
UVM_INFO @ 41879603481 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/8
UVM_INFO @ 41879603481 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/8
32.uart_stress_all_with_rand_reset.60724744934229544940851600056557946802542797939105720878550282838364078194103
Line 850, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51832206999 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 51832206999 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 5/10
UVM_INFO @ 51832279918 ps: (cip_base_vseq.sv:725) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 5/10
... and 4 more failures.
UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 3 failures:
Test uart_intr has 1 failures.
12.uart_intr.105471637042201858939947577205288531170537372152467170440793464526618252460663
Line 273, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_intr/latest/run.log
UVM_ERROR @ 14012167195 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14309767195 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing TxWatermark
UVM_ERROR @ 14451367195 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14746567195 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Test uart_stress_all_with_rand_reset has 2 failures.
68.uart_stress_all_with_rand_reset.81082580899804941561980623889537650306090468144672668777939789688960134218373
Line 857, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 611545558769 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 611618958769 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 611691158769 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 611762358769 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 611833158769 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
75.uart_stress_all_with_rand_reset.48071470763866989787048410969609497960442741930713603562699350440145799325676
Line 1029, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 884527147750 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 884527147750 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 40
UVM_ERROR @ 884819147750 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 884819147750 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 40
UVM_ERROR @ 885110947750 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 3 failures:
Test uart_loopback has 2 failures.
12.uart_loopback.40511303503703186952193139827437719407896407676765386296056606717286880897134
Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_loopback/latest/run.log
UVM_ERROR @ 6131000838 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_INFO @ 6136225326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.uart_loopback.112677444693506098579270673140741974102347678156669676229356956180775265296800
Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/43.uart_loopback/latest/run.log
UVM_ERROR @ 4636140414 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 4636140414 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 4641307082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test uart_stress_all_with_rand_reset has 1 failures.
70.uart_stress_all_with_rand_reset.61319513909599727850980457758899093237375696194276765222055821761262316824777
Line 689, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 102263590742 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 102263590742 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 102339950742 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 31/329
UVM_INFO @ 102610110742 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 32/329
UVM_INFO @ 102905550742 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 33/329
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
45.uart_intr.103668390249620027496581709076659620450124390576731300908623178248444156687911
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_intr/latest/run.log
Job ID: smart:7f87919d-143d-4138-a9e8-870d28eea48a
47.uart_intr.29820391593246403393195022686306540745699304412550483598828417523106532538273
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_intr/latest/run.log
Job ID: smart:111f4147-6c0d-4ad4-ba18-5a39ff048aa6
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
4.uart_intr.77647124566705859828256278385034303958377356016648304099827095953792644948255
Line 301, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_intr/latest/run.log
UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:
32.uart_noise_filter.102063285436022425058783103933111763624685325641452117382997603795284534573095
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/32.uart_noise_filter/latest/run.log
UVM_ERROR @ 45518337865 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: TxWatermark
UVM_INFO @ 55830949108 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 8/14
UVM_INFO @ 56056800085 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 9/14
UVM_INFO @ 85941370944 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 10/14
UVM_INFO @ 89517454125 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 11/14
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 1 failures:
36.uart_stress_all_with_rand_reset.47189885086889543193657521057243529508316802893775161506874004146619749141402
Line 530, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29608892448 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_INFO @ 29698953507 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 107/587
UVM_INFO @ 29750119355 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 108/587
UVM_INFO @ 29904741881 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 109/587
UVM_INFO @ 29911700103 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 1/17