UART Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	31.040s	6.340ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	38.751us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	16.472us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.200s	227.696us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	211.406us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.380s	144.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	16.472us	20	20	100.00
		uart_csr_aliasing	0.750s	211.406us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.310m	152.425ms	50	50	100.00
V2	parity	uart_smoke	31.040s	6.340ms	50	50	100.00
		uart_tx_rx	4.310m	152.425ms	50	50	100.00
V2	parity_error	uart_intr	31.200m	3.000s	45	50	90.00
		uart_rx_parity_err	12.171m	346.051ms	50	50	100.00
V2	watermark	uart_tx_rx	4.310m	152.425ms	50	50	100.00
		uart_intr	31.200m	3.000s	45	50	90.00
V2	fifo_full	uart_fifo_full	7.486m	274.991ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.914m	338.391ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.902m	202.681ms	300	300	100.00
V2	rx_frame_err	uart_intr	31.200m	3.000s	45	50	90.00
V2	rx_break_err	uart_intr	31.200m	3.000s	45	50	90.00
V2	rx_timeout	uart_intr	31.200m	3.000s	45	50	90.00
V2	perf	uart_perf	33.651m	38.236ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.550s	9.074ms	44	50	88.00
V2	line_loopback	uart_loopback	24.550s	9.074ms	44	50	88.00
V2	rx_noise_filter	uart_noise_filter	4.835m	128.280ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.066m	75.605ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	25.880s	12.411ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	47.680s	5.172ms	39	50	78.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.207m	165.363ms	50	50	100.00
V2	stress_all	uart_stress_all	1.288h	2.674s	48	50	96.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	26.313m	548.906ms	41	100	41.00
V2	alert_test	uart_alert_test	0.620s	12.443us	50	50	100.00
V2	intr_test	uart_intr_test	0.700s	25.330us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.420s	101.686us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.420s	101.686us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	38.751us	5	5	100.00
		uart_csr_rw	0.650s	16.472us	20	20	100.00
		uart_csr_aliasing	0.750s	211.406us	5	5	100.00
		uart_same_csr_outstanding	0.780s	36.041us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	38.751us	5	5	100.00
		uart_csr_rw	0.650s	16.472us	20	20	100.00
		uart_csr_aliasing	0.750s	211.406us	5	5	100.00
		uart_same_csr_outstanding	0.780s	36.041us	20	20	100.00
V2		TOTAL			1107	1190	93.03
V2S	tl_intg_err	uart_sec_cm	0.850s	176.695us	5	5	100.00
		uart_tl_intg_err	1.330s	147.717us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	147.717us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1237	1320	93.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	14	73.68
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.79	98.45	100.00	--	99.76	100.00	97.54

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 57 failures:

Test uart_stress_all_with_rand_reset has 57 failures.

0.uart_stress_all_with_rand_reset.13885487841009081030922053018863289410809795313722117238080277177176379033193
Line 384, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 41279123675 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 41279139919 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 41279139919 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 41279436215 ps: (cip_base_vseq.sv:730) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

3.uart_stress_all_with_rand_reset.23293165800638549701400438532571790383729351496846524329406705856456365405822
Line 562, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 99108256388 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 99108273857 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 99108273857 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 99108367607 ps: (cip_base_vseq.sv:730) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

... and 55 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 11 failures:

Test uart_rx_oversample has 11 failures.

0.uart_rx_oversample.109492787907038101252402367940949890914858222622011120037924952476057457879473
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 506434677 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (10236 [0x27fc] vs 9716 [0x25f4]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 515116582 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (11836 [0x2e3c] vs 11884 [0x2e6c]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 523556916 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/14
  UVM_ERROR @ 523843942 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (5925 [0x1725] vs 2866 [0xb32]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 542253217 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (47882 [0xbb0a] vs 46602 [0xb60a]) Regname: uart_reg_block.val.rx reset value: 0x0

10.uart_rx_oversample.104327462286737674963419786807541326890161682221328571505215875433857819154242
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_rx_oversample/latest/run.log

  UVM_ERROR @  23141898 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (64636 [0xfc7c] vs 56378 [0xdc3a]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  31553292 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/18
  UVM_ERROR @  31808634 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (17849 [0x45b9] vs 17832 [0x45a8]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 346524753 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/18
  UVM_ERROR @ 373144698 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (21015 [0x5217] vs 23063 [0x5a17]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 9 more failures.

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 7 failures:

Test uart_loopback has 6 failures.

5.uart_loopback.110836751987810791248799554827151318594725711168141350067958199756579003120145
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_loopback/latest/run.log

  UVM_ERROR @ 5008813023 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 5013853839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.uart_loopback.43139716138346373142341562084491035613298417725383942413752408481677593927884
Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_loopback/latest/run.log

  UVM_ERROR @ 6373965711 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 6373965711 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 6379132382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

96.uart_stress_all_with_rand_reset.30932149922886385572985784748406248070255252773578983125625824109410033061887
Line 279, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5090952884 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 5091112885 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 1/3
  UVM_INFO @ 5092232884 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 2/3
  UVM_INFO @ 5093072884 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 3/3
  UVM_INFO @ 5276952884 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 16/309

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test uart_intr has 3 failures.
  - 11.uart_intr.1857032518392761157990432130241001616845682636413457460594225767048502501767
    Line 320, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.uart_intr.23673339604151908310903308210289162628887011174351509848588325606332488814681
    Line 298, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 3 failures:

Test uart_stress_all has 2 failures.

38.uart_stress_all.70733917135329313256069182599596513561243655712921292338369313451916438603078
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_stress_all/latest/run.log

  UVM_ERROR @ 51563280721 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (218 [0xda] vs 105 [0x69]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 51563280721 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (105 [0x69] vs 218 [0xda]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_ERROR @ 51563433781 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
  UVM_INFO @ 51563515413 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/7
  UVM_INFO @ 51581770409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

39.uart_stress_all.30474998794117623010580039667152329321773374504162978468563748181085335810902
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_stress_all/latest/run.log

  UVM_ERROR @ 43875660637 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (40 [0x28] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 43875660637 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 40 [0x28]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 43878660637 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/7
  UVM_INFO @ 43991785637 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/7
  UVM_INFO @ 44104160637 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/7

Test uart_stress_all_with_rand_reset has 1 failures.

85.uart_stress_all_with_rand_reset.40358951169334875040417494392276892954430695470730493087025316549387310045738
Line 406, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 39036987806 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (127 [0x7f] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 39036987806 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 127 [0x7f]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 39037237808 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/20
  UVM_INFO @ 39121530149 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/20
  UVM_INFO @ 39157738772 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 21/679

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test uart_intr has 2 failures.
  - 30.uart_intr.20768121931777825911736910695888930500137035346910360730072059048221369015043
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_intr/latest/run.log
```
  Job ID: smart:df1892f8-f3e1-4818-8b21-17a2bbe238eb
```
  - 40.uart_intr.86096338654281594735328969211295354784639811643715623416966459035824683943832
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_intr/latest/run.log
```
  Job ID: smart:456fdea3-b643-4552-8831-e50f923b8a0f
```