UART Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	34.230s	11.625ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	15.806us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	15.255us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.360s	355.686us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	26.143us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.520s	54.256us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	15.255us	20	20	100.00
		uart_csr_aliasing	0.790s	26.143us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.686m	110.088ms	50	50	100.00
V2	parity	uart_smoke	34.230s	11.625ms	50	50	100.00
		uart_tx_rx	3.686m	110.088ms	50	50	100.00
V2	parity_error	uart_intr	54.886m	1.736s	46	50	92.00
		uart_rx_parity_err	13.558m	377.422ms	50	50	100.00
V2	watermark	uart_tx_rx	3.686m	110.088ms	50	50	100.00
		uart_intr	54.886m	1.736s	46	50	92.00
V2	fifo_full	uart_fifo_full	14.994m	303.808ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	10.244m	237.049ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.688m	277.776ms	300	300	100.00
V2	rx_frame_err	uart_intr	54.886m	1.736s	46	50	92.00
V2	rx_break_err	uart_intr	54.886m	1.736s	46	50	92.00
V2	rx_timeout	uart_intr	54.886m	1.736s	46	50	92.00
V2	perf	uart_perf	21.876m	25.141ms	50	50	100.00
V2	sys_loopback	uart_loopback	37.510s	10.820ms	43	50	86.00
V2	line_loopback	uart_loopback	37.510s	10.820ms	43	50	86.00
V2	rx_noise_filter	uart_noise_filter	3.153m	82.386ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	57.480s	34.746ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.870s	12.581ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	54.210s	6.184ms	40	50	80.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.613m	181.428ms	49	50	98.00
V2	stress_all	uart_stress_all	2.309h	5.149s	49	50	98.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	38.184m	105.145ms	43	100	43.00
V2	alert_test	uart_alert_test	0.610s	51.616us	50	50	100.00
V2	intr_test	uart_intr_test	0.670s	14.171us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.390s	182.229us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.390s	182.229us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	15.806us	5	5	100.00
		uart_csr_rw	0.640s	15.255us	20	20	100.00
		uart_csr_aliasing	0.790s	26.143us	5	5	100.00
		uart_same_csr_outstanding	0.800s	36.777us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	15.806us	5	5	100.00
		uart_csr_rw	0.640s	15.255us	20	20	100.00
		uart_csr_aliasing	0.790s	26.143us	5	5	100.00
		uart_same_csr_outstanding	0.800s	36.777us	20	20	100.00
V2		TOTAL			1110	1190	93.28
V2S	tl_intg_err	uart_sec_cm	0.860s	208.098us	5	5	100.00
		uart_tl_intg_err	1.610s	1.667ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.610s	1.667ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1240	1320	93.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	13	68.42
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.79	98.45	100.00	--	99.76	100.00	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 55 failures:

Test uart_stress_all_with_rand_reset has 55 failures.

0.uart_stress_all_with_rand_reset.6006262722753884842818024995424336247704856386234925751457015952928476510270
Line 447, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 52624111088 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 52624151087 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 52624151087 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 52624151087 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/8

1.uart_stress_all_with_rand_reset.64056352415637649673441026920407580711277432524627631947308150313567711651969
Line 454, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16882000178 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 16882000560 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16882000560 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 16882041414 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 2/2

... and 53 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 10 failures:

Test uart_rx_oversample has 10 failures.

0.uart_rx_oversample.56809645087987070767794042578198573250072570234176631330201543367876075348017
Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 1007325241 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (35647 [0x8b3f] vs 50591 [0xc59f]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 1035653375 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/9
  UVM_INFO @ 1250721080 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/9
  UVM_INFO @ 1550262752 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 8/9
  UVM_INFO @ 1586583935 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 9/9

1.uart_rx_oversample.13528472750495680222136508481921483519196528172024449775465348873573840075279
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_rx_oversample/latest/run.log

  UVM_ERROR @  21985341 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (24239 [0x5eaf] vs 24235 [0x5eab]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @  30637463 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (7261 [0x1c5d] vs 6237 [0x185d]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  39113655 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/19
  UVM_ERROR @  39376541 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (50161 [0xc3f1] vs 58224 [0xe370]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  74852571 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/19

... and 8 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 6 failures:

Test uart_loopback has 4 failures.

13.uart_loopback.104069752124000384794885694432390264273145046319106733792215649975446483254037
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_loopback/latest/run.log

  UVM_ERROR @ 5855649624 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (155 [0x9b] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 5855649624 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 155 [0x9b]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 5855774622 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/15
  UVM_INFO @ 6908278615 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/15
  UVM_INFO @ 7197107327 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/15

22.uart_loopback.91687206571722599654876541731997058883225065442958746431951613164562445748747
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_loopback/latest/run.log

  UVM_ERROR @ 837671056 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (244 [0xf4] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 837671056 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 244 [0xf4]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 837893278 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/14
  UVM_INFO @ 880596939 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/14
  UVM_INFO @ 2167262319 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/14

... and 2 more failures.

Test uart_stress_all has 1 failures.

33.uart_stress_all.15683825294933554542341763536493383272408020446633743696396921606237357076257
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/33.uart_stress_all/latest/run.log

  UVM_ERROR @ 62834118127 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (186 [0xba] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 62834118127 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 186 [0xba]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 62834179981 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/16
  UVM_INFO @ 62879848851 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/16
  UVM_INFO @ 62918837489 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/16

Test uart_stress_all_with_rand_reset has 1 failures.

87.uart_stress_all_with_rand_reset.13966104438980705284057439303063379083234077512839673017651757267828161486862
Line 348, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13183827861 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (158 [0x9e] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 13183827861 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 158 [0x9e]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 13184202855 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/17
  UVM_INFO @ 13211764914 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 23/620
  UVM_INFO @ 13473364895 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 24/620

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 3 failures:

Test uart_loopback has 3 failures.

10.uart_loopback.7002794416498612521458522668660990431621009160750786592027992411830974511391
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_loopback/latest/run.log

  UVM_ERROR @ 12244234370 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 12249599759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.uart_loopback.45087343178442608744509001684595039879292764980784658812609834350752475474651
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_loopback/latest/run.log

  UVM_ERROR @ 1438815389 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 1444050685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test uart_intr has 2 failures.
  - 4.uart_intr.102828085221581112077829352561198906767058332769167944678371283562631869805110
    Line 324, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.uart_intr.47916858991512492104317077184948074934200245099348393540705566963251696769394
    Line 311, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_intr has 1 failures.

22.uart_intr.3985023128999290953451211640618480904134587861935788018301979051303095766425
Line 303, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_intr/latest/run.log

  UVM_ERROR @ 1428823231797 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1428966031797 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1429110231797 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1429254031797 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1429400431797 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_ERROR (uart_scoreboard.sv:380) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

31.uart_long_xfer_wo_dly.76692725910141431201355607526441255237601984493672434859545273929077398715418
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 302420441 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 425362601 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 742423961 ps: (uart_scoreboard.sv:380) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 3450798569 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/6
  UVM_INFO @ 40172268809 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/6

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 39.uart_intr.337420312081358080024108663514690214210269329286681165414368192626597613467
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_intr/latest/run.log
```
  Job ID: smart:81caede4-f98e-4fb2-a04b-7104fe77cf69
```

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

77.uart_stress_all_with_rand_reset.112114132784331756609808628221933058467322403940155599101886753755139944961958
Line 328, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6827634359 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_INFO @ 6827769952 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 1/6
  UVM_INFO @ 6828193676 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 2/6
  UVM_INFO @ 6828617401 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 3/6
  UVM_INFO @ 6829007228 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 4/6