UART Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	32.330s	5.390ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.210s	1.035ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	39.372us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.560s	344.755us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	31.065us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.320s	27.283us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	39.372us	20	20	100.00
		uart_csr_aliasing	0.830s	31.065us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.300m	260.067ms	50	50	100.00
V2	parity	uart_smoke	32.330s	5.390ms	50	50	100.00
		uart_tx_rx	3.300m	260.067ms	50	50	100.00
V2	parity_error	uart_intr	51.362m	1.959s	48	50	96.00
		uart_rx_parity_err	6.788m	242.818ms	50	50	100.00
V2	watermark	uart_tx_rx	3.300m	260.067ms	50	50	100.00
		uart_intr	51.362m	1.959s	48	50	96.00
V2	fifo_full	uart_fifo_full	6.013m	216.847ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.697m	269.827ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.391m	137.870ms	299	300	99.67
V2	rx_frame_err	uart_intr	51.362m	1.959s	48	50	96.00
V2	rx_break_err	uart_intr	51.362m	1.959s	48	50	96.00
V2	rx_timeout	uart_intr	51.362m	1.959s	48	50	96.00
V2	perf	uart_perf	27.618m	31.785ms	50	50	100.00
V2	sys_loopback	uart_loopback	37.310s	13.501ms	45	50	90.00
V2	line_loopback	uart_loopback	37.310s	13.501ms	45	50	90.00
V2	rx_noise_filter	uart_noise_filter	4.240m	77.959ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.054m	76.842ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	36.560s	6.578ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	32.560s	4.078ms	43	50	86.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.284m	158.339ms	50	50	100.00
V2	stress_all	uart_stress_all	1.883h	3.603s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	36.019m	88.118ms	28	100	28.00
V2	alert_test	uart_alert_test	0.640s	115.369us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	13.126us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.460s	121.563us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.460s	121.563us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.210s	1.035ms	5	5	100.00
		uart_csr_rw	0.680s	39.372us	20	20	100.00
		uart_csr_aliasing	0.830s	31.065us	5	5	100.00
		uart_same_csr_outstanding	0.790s	28.636us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.210s	1.035ms	5	5	100.00
		uart_csr_rw	0.680s	39.372us	20	20	100.00
		uart_csr_aliasing	0.830s	31.065us	5	5	100.00
		uart_same_csr_outstanding	0.790s	28.636us	20	20	100.00
V2		TOTAL			1102	1190	92.61
V2S	tl_intg_err	uart_sec_cm	0.880s	148.503us	5	5	100.00
		uart_tl_intg_err	1.570s	289.446us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.570s	289.446us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1232	1320	93.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	13	68.42
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.79	98.45	100.00	--	99.76	100.00	97.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 70 failures:

Test uart_stress_all_with_rand_reset has 70 failures.

1.uart_stress_all_with_rand_reset.7046438830397640925427127299626668954447034854484775433801197338803163427348
Line 555, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 197872807208 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 197872837407 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 197872837407 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 197873185231 ps: (cip_base_vseq.sv:730) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

2.uart_stress_all_with_rand_reset.86278282837110095530531439065656498129839248381673545538304614559696606783653
Line 394, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43725218150 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 43725231156 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 43725231156 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 43725503886 ps: (cip_base_vseq.sv:730) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

... and 68 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 7 failures:

Test uart_rx_oversample has 7 failures.

6.uart_rx_oversample.95779689294611545862407577995509117904393849376152329355255728109204536507442
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 1321186880 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (711 [0x2c7] vs 715 [0x2cb]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 1339326282 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/18
  UVM_INFO @ 1373507950 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 8/18
  UVM_INFO @ 1408780576 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 9/18
  UVM_INFO @ 1728286927 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 10/18

13.uart_rx_oversample.47340638068141859950466640639333380835267093533317609816505535959195049939568
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 760087026 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (19665 [0x4cd1] vs 42600 [0xa668]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 780584600 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/11
  UVM_INFO @ 987857865 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/11
  UVM_INFO @ 1196257865 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/11
  UVM_INFO @ 1411057865 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/11

... and 5 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 5 failures:

Test uart_loopback has 4 failures.

6.uart_loopback.97488278153153019317991701357239089048372209795999576848540352283683260997514
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_loopback/latest/run.log

  UVM_ERROR @ 8339897083 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (96 [0x60] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 8339897083 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 96 [0x60]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 8340137083 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 16/20
  UVM_INFO @ 9548057083 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 17/20
  UVM_INFO @ 10136697083 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 18/20

24.uart_loopback.56349257478092362935555781161882395164725330672392699402827020104988346744897
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_loopback/latest/run.log

  UVM_ERROR @ 287622830 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (34 [0x22] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 287622830 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 34 [0x22]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 287862830 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/11
  UVM_INFO @ 1601222830 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/11
  UVM_INFO @ 2361862830 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/11

... and 2 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

86.uart_stress_all_with_rand_reset.27789838076349067430499691852232317826086321270023657956303992594371583146929
Line 349, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12578588879 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (91 [0x5b] vs 253 [0xfd]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 12578588879 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (253 [0xfd] vs 91 [0x5b]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 12579308879 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/13
  UVM_INFO @ 12759348879 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 25/951
  UVM_INFO @ 12847928879 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 26/951

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test uart_intr has 1 failures.
  - 36.uart_intr.13794293804328502463100341275155956729647107401735581494205665582175766248219
    Line 322, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test uart_noise_filter has 1 failures.
  - 39.uart_noise_filter.115239731938243209477781992234183596888134004905002416953935924491280509757853
    Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:
- Test uart_loopback has 1 failures.
  - 23.uart_loopback.83808196143117318349409368086591138775734109272395578401373907172274448615500
    Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_loopback/latest/run.log
```
  UVM_ERROR @ 13496361673 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 13501412178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:719) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

24.uart_stress_all_with_rand_reset.74643922309832242272899826193541479678445117877553858310520066640675516835190
Line 292, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15936880712 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15936880712 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 15937005713 ps: (cip_base_vseq.sv:730) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/10

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 47.uart_intr.81382333608246610658190385997481685042896275702433573681903460525884143944570
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_intr/latest/run.log
```
  Job ID: smart:ac79bf0d-1e3c-44d5-b16d-7e66d6173cfe
```

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_fifo_reset has 1 failures.

278.uart_fifo_reset.5098956171208848546501915255652846608313470635500035651282451339002512937045
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/278.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1428708 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 798728708 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
  UVM_INFO @ 1508278708 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
  UVM_INFO @ 1938578708 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7
  UVM_INFO @ 1963778708 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7