0cdf265eaa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 27.110s | 6.337ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.610s | 68.782us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.640s | 15.181us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.640s | 504.822us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 0.790s | 33.184us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.310s | 49.728us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.640s | 15.181us | 20 | 20 | 100.00 |
| uart_csr_aliasing | 0.790s | 33.184us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | base_random_seq | uart_tx_rx | 12.217m | 147.644ms | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 27.110s | 6.337ms | 50 | 50 | 100.00 |
| uart_tx_rx | 12.217m | 147.644ms | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 39.031m | 1.179s | 48 | 50 | 96.00 |
| uart_rx_parity_err | 6.012m | 137.295ms | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 12.217m | 147.644ms | 50 | 50 | 100.00 |
| uart_intr | 39.031m | 1.179s | 48 | 50 | 96.00 | ||
| V2 | fifo_full | uart_fifo_full | 5.605m | 139.233ms | 50 | 50 | 100.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 7.990m | 427.752ms | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 6.818m | 86.380ms | 298 | 300 | 99.33 |
| V2 | rx_frame_err | uart_intr | 39.031m | 1.179s | 48 | 50 | 96.00 |
| V2 | rx_break_err | uart_intr | 39.031m | 1.179s | 48 | 50 | 96.00 |
| V2 | rx_timeout | uart_intr | 39.031m | 1.179s | 48 | 50 | 96.00 |
| V2 | perf | uart_perf | 24.256m | 25.525ms | 50 | 50 | 100.00 |
| V2 | sys_loopback | uart_loopback | 31.680s | 10.268ms | 46 | 50 | 92.00 |
| V2 | line_loopback | uart_loopback | 31.680s | 10.268ms | 46 | 50 | 92.00 |
| V2 | rx_noise_filter | uart_noise_filter | 4.692m | 166.789ms | 49 | 50 | 98.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 47.070s | 28.349ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 42.070s | 12.562ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 32.090s | 4.339ms | 37 | 50 | 74.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 20.151m | 159.899ms | 50 | 50 | 100.00 |
| V2 | stress_all | uart_stress_all | 59.604m | 2.294s | 46 | 50 | 92.00 |
| V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 39.422m | 339.503ms | 38 | 100 | 38.00 |
| V2 | alert_test | uart_alert_test | 0.630s | 42.401us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 0.650s | 13.837us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 2.810s | 1.011ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 2.810s | 1.011ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.610s | 68.782us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.640s | 15.181us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.790s | 33.184us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.770s | 59.567us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.610s | 68.782us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.640s | 15.181us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.790s | 33.184us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.770s | 59.567us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1102 | 1190 | 92.61 | |||
| V2S | tl_intg_err | uart_sec_cm | 0.910s | 264.809us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.420s | 124.208us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.420s | 124.208us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 1232 | 1320 | 93.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 19 | 19 | 12 | 63.16 |
| V2S | 2 | 2 | 2 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.26 | 99.79 | 98.45 | 100.00 | -- | 99.76 | 100.00 | 97.56 |
UVM_ERROR (cip_base_vseq.sv:815) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 59 failures:
1.uart_stress_all_with_rand_reset.100053374646686811145788025650324831394701776296843674787868895702131770256754
Line 451, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38988329451 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 38988353145 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 38988353145 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 2/10
UVM_INFO @ 38988353145 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/5
2.uart_stress_all_with_rand_reset.73525503037164696648055523171202235608954999233299330929277987025687401660747
Line 622, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 78137600339 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 78137622825 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 78137622825 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 6/10
UVM_INFO @ 78137840339 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/8
... and 57 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 13 failures:
0.uart_rx_oversample.104180263365825196944501648276212826179407135330606347210819182168808908044938
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_rx_oversample/latest/run.log
UVM_ERROR @ 52061224 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (50395 [0xc4db] vs 25197 [0x626d]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_ERROR @ 70489777 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (47360 [0xb900] vs 39040 [0x9880]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 78496492 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/20
UVM_ERROR @ 79204054 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (59376 [0xe7f0] vs 54768 [0xd5f0]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 270260523 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/20
5.uart_rx_oversample.44734764871121289581712071683133777841267085507058773478835292504449442402541
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_rx_oversample/latest/run.log
UVM_ERROR @ 2635920200 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1134 [0x46e] vs 1262 [0x4ee]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 2644360534 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 11/19
UVM_ERROR @ 2644647560 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (48259 [0xbc83] vs 57025 [0xdec1]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 2662817954 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 12/19
UVM_ERROR @ 2663102290 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (6729 [0x1a49] vs 36132 [0x8d24]) Regname: uart_reg_block.val.rx reset value: 0x0
... and 11 more failures.
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 5 failures:
Test uart_stress_all has 1 failures.
0.uart_stress_all.107002780929386177585346874496181136714403569207060365545924616328352668654043
Line 276, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all/latest/run.log
UVM_ERROR @ 124822088512 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 124822088512 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 124822128513 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 1/3
UVM_INFO @ 124822258512 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 2/3
UVM_INFO @ 124822378512 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 3/3
Test uart_loopback has 3 failures.
14.uart_loopback.56351162590112700804143770555753371126733214782880783325237039934337613178597
Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_loopback/latest/run.log
UVM_ERROR @ 9357034338 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 9357034338 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 9362111262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.uart_loopback.31348776461525998079597062565707049609566987208647566711420428352428262166580
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_loopback/latest/run.log
UVM_ERROR @ 1444011780 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_INFO @ 1449053016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test uart_stress_all_with_rand_reset has 1 failures.
95.uart_stress_all_with_rand_reset.20014773508872924423138052806966861123283871338664929063383578751435038580697
Line 415, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18724563228 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_INFO @ 18724646561 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 1/6
UVM_INFO @ 18724917389 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 2/6
UVM_INFO @ 18725167385 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 3/6
UVM_INFO @ 18725417381 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 4/6
UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 4 failures:
Test uart_loopback has 1 failures.
31.uart_loopback.106918797670969972774297709710591343204769454055709842780435221204661504623076
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_loopback/latest/run.log
UVM_ERROR @ 6788344523 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (15 [0xf] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6788344523 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 15 [0xf]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 6788404523 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/11
UVM_INFO @ 6829644523 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/11
UVM_INFO @ 6838004523 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/11
Test uart_stress_all has 3 failures.
40.uart_stress_all.114809860507938494475214998738693824534569482162469787410782835081920023713922
Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_stress_all/latest/run.log
UVM_ERROR @ 6211026346 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (125 [0x7d] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6211026346 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 125 [0x7d]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_ERROR @ 6211106346 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
UVM_INFO @ 6211146346 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/17
UVM_ERROR @ 6298066346 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (246 [0xf6] vs 125 [0x7d]) reg name: uart_reg_block.rdata
41.uart_stress_all.6338977539216488123197418892338444342973469516706353918514465917973470929647
Line 279, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/41.uart_stress_all/latest/run.log
UVM_ERROR @ 156638160395 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (215 [0xd7] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 156638160395 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 215 [0xd7]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 156638221001 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/18
UVM_INFO @ 157329190007 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/18
UVM_INFO @ 158442865661 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/18
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test uart_noise_filter has 1 failures.
0.uart_noise_filter.96591728449610003438914512419156592056885551788448183274790102951797595442990
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_noise_filter/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test uart_intr has 2 failures.
23.uart_intr.28677689859162810614064174946359876730071440069795782226418667394412402549518
Line 271, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_intr/latest/run.log
UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.uart_intr.47653756648376844667139260591810456536787259862564850374446040927945248286934
Line 277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/48.uart_intr/latest/run.log
UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:741) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
3.uart_stress_all_with_rand_reset.30330774088859280321168214208005978301117216082407387643008435163267387994083
Line 390, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9181483872 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9181483872 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 1/5
UVM_INFO @ 9181483872 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
UVM_INFO @ 9181483872 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/5
85.uart_stress_all_with_rand_reset.58456949386744630720748881335067416590408609530148414081892474021093886655587
Line 572, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45300530932 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 45300530932 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 4/10
UVM_INFO @ 45300530932 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/6
UVM_INFO @ 45300530932 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/6
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 2 failures:
21.uart_fifo_reset.44361714665050040422171763003794289909185408900705177867286308374891400742082
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_fifo_reset/latest/run.log
UVM_ERROR @ 930650 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
UVM_INFO @ 839430650 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8
UVM_INFO @ 969250650 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
UVM_INFO @ 1012770650 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
UVM_INFO @ 4997540650 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8
212.uart_fifo_reset.61754300161815067528001716793704053678713678300169760721177000152730641008283
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/212.uart_fifo_reset/latest/run.log
UVM_ERROR @ 1032764 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
UVM_INFO @ 3878306164 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
UVM_INFO @ 44104288259 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
UVM_INFO @ 113925963169 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
UVM_INFO @ 119921583644 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6