c30684b3ca| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 36.060s | 11.624ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.630s | 15.817us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.670s | 45.856us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.560s | 943.868us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 0.790s | 104.527us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.150s | 42.058us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.670s | 45.856us | 20 | 20 | 100.00 |
| uart_csr_aliasing | 0.790s | 104.527us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | base_random_seq | uart_tx_rx | 3.897m | 144.037ms | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 36.060s | 11.624ms | 50 | 50 | 100.00 |
| uart_tx_rx | 3.897m | 144.037ms | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 55.732m | 2.144s | 42 | 50 | 84.00 |
| uart_rx_parity_err | 6.879m | 198.882ms | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 3.897m | 144.037ms | 50 | 50 | 100.00 |
| uart_intr | 55.732m | 2.144s | 42 | 50 | 84.00 | ||
| V2 | fifo_full | uart_fifo_full | 5.488m | 199.645ms | 50 | 50 | 100.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 12.658m | 171.305ms | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 6.129m | 211.711ms | 300 | 300 | 100.00 |
| V2 | rx_frame_err | uart_intr | 55.732m | 2.144s | 42 | 50 | 84.00 |
| V2 | rx_break_err | uart_intr | 55.732m | 2.144s | 42 | 50 | 84.00 |
| V2 | rx_timeout | uart_intr | 55.732m | 2.144s | 42 | 50 | 84.00 |
| V2 | perf | uart_perf | 27.607m | 34.509ms | 50 | 50 | 100.00 |
| V2 | sys_loopback | uart_loopback | 57.290s | 7.411ms | 46 | 50 | 92.00 |
| V2 | line_loopback | uart_loopback | 57.290s | 7.411ms | 46 | 50 | 92.00 |
| V2 | rx_noise_filter | uart_noise_filter | 6.163m | 146.854ms | 50 | 50 | 100.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 1.192m | 39.468ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 26.660s | 6.508ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 35.000s | 3.403ms | 43 | 50 | 86.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 23.003m | 129.208ms | 49 | 50 | 98.00 |
| V2 | stress_all | uart_stress_all | 28.171m | 940.133ms | 48 | 50 | 96.00 |
| V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 35.243m | 191.692ms | 34 | 100 | 34.00 |
| V2 | alert_test | uart_alert_test | 0.610s | 19.656us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 0.630s | 52.390us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 2.260s | 179.264us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 2.260s | 179.264us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.630s | 15.817us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.670s | 45.856us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.790s | 104.527us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.810s | 32.240us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.630s | 15.817us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.670s | 45.856us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.790s | 104.527us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.810s | 32.240us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1102 | 1190 | 92.61 | |||
| V2S | tl_intg_err | uart_sec_cm | 0.880s | 268.361us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.440s | 302.722us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.440s | 302.722us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 1232 | 1320 | 93.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 19 | 19 | 13 | 68.42 |
| V2S | 2 | 2 | 2 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.94 | 99.38 | 97.89 | 100.00 | -- | 98.83 | 100.00 | 97.52 |
UVM_ERROR (cip_base_vseq.sv:827) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 62 failures:
0.uart_stress_all_with_rand_reset.39162129438542741415424128625622290629768975665492423186578541861596744991620
Line 423, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16194557406 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10021 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 16194558129 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 16194558129 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 4/5
UVM_INFO @ 16194574073 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 2/2
4.uart_stress_all_with_rand_reset.115573389627907812523535633065345036822678250493636262672236116708401953208233
Line 526, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 73571562221 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 73571597300 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 73571597300 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 5/10
UVM_INFO @ 73571837300 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
... and 60 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 7 failures:
6.uart_rx_oversample.45905982840118911666969119497427939142626406295891830205420745211457535414549
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest/run.log
UVM_ERROR @ 547600714 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4135 [0x1027] vs 34835 [0x8813]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 584716540 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/4
UVM_INFO @ 799228551 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/4
UVM_INFO @ 1911599355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.uart_rx_oversample.92436611175809105538391316351988343124047140147259145869047843730276617484430
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_rx_oversample/latest/run.log
UVM_ERROR @ 2635298746 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (17596 [0x44bc] vs 17852 [0x45bc]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 2661626950 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 16/20
UVM_INFO @ 2697474394 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 17/20
UVM_INFO @ 2715905227 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 18/20
UVM_INFO @ 3012945924 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 19/20
... and 5 more failures.
UVM_ERROR (uart_scoreboard.sv:441) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 7 failures:
Test uart_stress_all has 1 failures.
10.uart_stress_all.56314856785382666494917412381620561316932292472215991028352410784850066423654
Line 276, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all/latest/run.log
UVM_ERROR @ 454474728134 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
UVM_ERROR @ 454474728134 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 454564186602 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing TxEmpty
UVM_INFO @ 456343845834 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Test uart_intr has 5 failures.
13.uart_intr.60192679711104342543087630095778957798550932862707990114833691023440091452891
Line 273, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_intr/latest/run.log
UVM_ERROR @ 21578584123 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
UVM_ERROR @ 21578584123 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21755944123 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing TxEmpty
UVM_INFO @ 23492384123 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
18.uart_intr.56587430762422570052131396254505911447051681014669567624990441377238711153986
Line 277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_intr/latest/run.log
UVM_ERROR @ 87589376176 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
UVM_ERROR @ 87589376176 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 87745630028 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing RxTimeout
UVM_INFO @ 99089692336 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
... and 3 more failures.
Test uart_stress_all_with_rand_reset has 1 failures.
72.uart_stress_all_with_rand_reset.26411333716788733702697424164353377454520775163248342079785377513115946051580
Line 356, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33124389049 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
UVM_ERROR @ 33124389049 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 33621189049 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 33621217497 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 33621217497 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
UVM_ERROR (uart_scoreboard.sv:441) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 5 failures:
Test uart_stress_all_with_rand_reset has 2 failures.
14.uart_stress_all_with_rand_reset.83239627100725215074915291806406161952609863789477081658066407855954779816756
Line 1202, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 132089807145 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 132089807145 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 132090011226 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 1/3
UVM_INFO @ 132090521425 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 2/3
UVM_INFO @ 132090990809 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 3/3
49.uart_stress_all_with_rand_reset.86470427080072051002677073406012194341468277887427138247559480451187434224871
Line 432, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21234206518 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 21234206518 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 21275726518 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 53/242
UVM_INFO @ 21459146518 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 54/242
UVM_INFO @ 21642186518 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 55/242
Test uart_loopback has 3 failures.
17.uart_loopback.60319643542443076872416089349975006681834348927222968489308697113104720359802
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_loopback/latest/run.log
UVM_ERROR @ 8495418217 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 8495418217 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 8500459885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.uart_loopback.96636012342182902801408831045393556149935675295555563945505069639131114745719
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/32.uart_loopback/latest/run.log
UVM_ERROR @ 7543846703 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 7543846703 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 7549013371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
7.uart_intr.109000593982562307984734727171446092796646246821835021412299665895643221393440
Line 292, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_intr/latest/run.log
UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.uart_intr.30499011793429287650103979450574981779062439500450506871102959124584327584196
Line 264, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/41.uart_intr/latest/run.log
UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uart_scoreboard.sv:527) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 2 failures:
Test uart_stress_all has 1 failures.
12.uart_stress_all.40067588921106329334564447294105036921843754664175222000696964631515180493207
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_stress_all/latest/run.log
UVM_ERROR @ 59165830749 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (207 [0xcf] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 59165830749 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (254 [0xfe] vs 207 [0xcf]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 59165958411 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/14
UVM_INFO @ 59639286553 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/14
UVM_INFO @ 59877780446 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/14
Test uart_loopback has 1 failures.
28.uart_loopback.76681973576970723822440579625940884347052842232549326421766574475038290931672
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_loopback/latest/run.log
UVM_ERROR @ 4537430349 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (103 [0x67] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4537430349 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 103 [0x67]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 4537491573 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/7
UVM_INFO @ 5800410041 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/7
UVM_INFO @ 5895521525 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/7
UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
8.uart_long_xfer_wo_dly.11095236439256994415132293035466943900638010294148605168900763282877452789672
Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest/run.log
UVM_ERROR @ 75029686559 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 75096981215 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 75265570799 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 75377806991 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 75411689615 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
16.uart_intr.112359826028498019756588886249648787137326476666046962685053395457044944654296
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_intr/latest/run.log
Job ID: smart:c036aadc-b95a-40c7-9b1e-82d256462ac7
UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
69.uart_stress_all_with_rand_reset.41573218955158551463864543686065780396182770257778876970003299006046511869145
Line 812, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 126811438867 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 126811438867 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 7/10
UVM_INFO @ 126811438867 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/8
UVM_INFO @ 126811438867 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/8