UART Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.370s	5.992ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.060s	1.032ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	49.373us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.540s	255.749us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	16.896us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.290s	95.140us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	49.373us	20	20	100.00
		uart_csr_aliasing	0.820s	16.896us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.554m	111.247ms	50	50	100.00
V2	parity	uart_smoke	24.370s	5.992ms	50	50	100.00
		uart_tx_rx	3.554m	111.247ms	50	50	100.00
V2	parity_error	uart_intr	40.569m	3.000s	41	50	82.00
		uart_rx_parity_err	6.893m	402.044ms	50	50	100.00
V2	watermark	uart_tx_rx	3.554m	111.247ms	50	50	100.00
		uart_intr	40.569m	3.000s	41	50	82.00
V2	fifo_full	uart_fifo_full	14.178m	310.491ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.872m	125.674ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.646m	199.882ms	300	300	100.00
V2	rx_frame_err	uart_intr	40.569m	3.000s	41	50	82.00
V2	rx_break_err	uart_intr	40.569m	3.000s	41	50	82.00
V2	rx_timeout	uart_intr	40.569m	3.000s	41	50	82.00
V2	perf	uart_perf	35.048m	40.533ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.350s	10.813ms	45	50	90.00
V2	line_loopback	uart_loopback	21.350s	10.813ms	45	50	90.00
V2	rx_noise_filter	uart_noise_filter	2.868m	76.474ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.120m	37.874ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	31.050s	6.573ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.210m	7.701ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	15.226m	142.957ms	50	50	100.00
V2	stress_all	uart_stress_all	1.258h	2.442s	46	50	92.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	27.589m	217.481ms	39	100	39.00
V2	alert_test	uart_alert_test	0.640s	14.885us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	38.076us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.510s	558.015us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.510s	558.015us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.060s	1.032ms	5	5	100.00
		uart_csr_rw	0.650s	49.373us	20	20	100.00
		uart_csr_aliasing	0.820s	16.896us	5	5	100.00
		uart_same_csr_outstanding	0.820s	121.145us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.060s	1.032ms	5	5	100.00
		uart_csr_rw	0.650s	49.373us	20	20	100.00
		uart_csr_aliasing	0.820s	16.896us	5	5	100.00
		uart_same_csr_outstanding	0.820s	121.145us	20	20	100.00
V2		TOTAL			1110	1190	93.28
V2S	tl_intg_err	uart_sec_cm	0.920s	692.622us	5	5	100.00
		uart_tl_intg_err	1.350s	132.354us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	132.354us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1240	1320	93.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	14	73.68
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.93	99.38	97.89	100.00	--	98.83	100.00	97.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 53 failures:

Test uart_stress_all_with_rand_reset has 53 failures.

1.uart_stress_all_with_rand_reset.101397475566441551106824585351606359687683104746778732213985837002692484863636
Line 317, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6663309504 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 6663318560 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6663318560 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 6663318560 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/5

4.uart_stress_all_with_rand_reset.114462774953148851119486751310677966934824570533853451287961400919970865667411
Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3142585204 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3142606718 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3142606718 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 3142606718 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9

... and 51 more failures.

UVM_ERROR (uart_scoreboard.sv:527) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 8 failures:

Test uart_loopback has 3 failures.

12.uart_loopback.89976067114985717317250129703379492429079960226593215096589814778906544136647
Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_loopback/latest/run.log

  UVM_ERROR @ 10163576828 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (43 [0x2b] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 10163576828 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 43 [0x2b]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 10163837696 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 19/19
  UVM_ERROR @ 10185315828 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 10190489740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

25.uart_loopback.40181872234368150696328022009624048664812827192973551423397471757107243107128
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_loopback/latest/run.log

  UVM_ERROR @ 3492464566 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (33 [0x21] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 3492464566 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 33 [0x21]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 3492554566 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/16
  UVM_INFO @ 3582374566 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/16
  UVM_INFO @ 3676044566 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/16

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 2 failures.

13.uart_stress_all_with_rand_reset.20287581291025634359852200527800470237695610970996744736549736853005593156402
Line 437, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33742975052 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (136 [0x88] vs 253 [0xfd]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 33742975052 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (253 [0xfd] vs 136 [0x88]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 33743100050 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/20
  UVM_INFO @ 33809578153 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/736
  UVM_INFO @ 33837431874 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/20

39.uart_stress_all_with_rand_reset.37021666116387411088132347991681699799771892841009887395576206731706566761675
Line 302, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16236166798 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (28 [0x1c] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 16236166798 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 28 [0x1c]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 16236666796 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 17/20
  UVM_INFO @ 16282166614 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 18/20
  UVM_INFO @ 16324916443 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 19/20

Test uart_stress_all has 3 failures.

24.uart_stress_all.5875457408407194281441677091380467337682704829093447797537796081697264182889
Line 278, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_stress_all/latest/run.log

  UVM_ERROR @ 57281683757 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (145 [0x91] vs 254 [0xfe]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 57281683757 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (254 [0xfe] vs 145 [0x91]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 57281969471 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/18
  UVM_INFO @ 57325874189 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 13/18
  UVM_INFO @ 57368302718 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 14/18

25.uart_stress_all.109076437177896353268277989309229136782235623846531442154160055401826015774283
Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_stress_all/latest/run.log

  UVM_ERROR @ 19679544509 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (248 [0xf8] vs 252 [0xfc]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 19679544509 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (252 [0xfc] vs 248 [0xf8]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 19679711177 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/12
  UVM_INFO @ 19894629563 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/12
  UVM_INFO @ 20195409747 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/12

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
- Test uart_noise_filter has 1 failures.
  - 6.uart_noise_filter.35320430184753425011777107282131504895944365241887372057434802313609798222410
    Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test uart_intr has 4 failures.
  - 21.uart_intr.54239623567919442990919577050567023617940118198964001648068679630424474043180
    Line 279, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.uart_intr.115033981075007248051744525827281646471120221200149353765557498086150099743880
    Line 284, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (uart_scoreboard.sv:441) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 5 failures:

Test uart_intr has 3 failures.

14.uart_intr.60806183120716331745432460147927156820558911757408281596620964217146400855324
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_intr/latest/run.log

  UVM_ERROR @ 574572985 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @ 574572985 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 771672985 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 13089822985 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

15.uart_intr.86376459600123842143123073607243327040776736850944631507842522582180454365768
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_intr/latest/run.log

  UVM_ERROR @   1728010 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @   1728010 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 163726714 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 5867089250 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

34.uart_stress_all_with_rand_reset.92707615523238725733786293508418091611485524893334034817725739674349328000847
Line 383, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 75833868885 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @ 75833868885 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 75856268885 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 25/682
  UVM_INFO @ 76241168885 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr

Test uart_stress_all has 1 failures.

38.uart_stress_all.22724086513440645814331856844414740686188111801450332252930268309952757415507
Line 279, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_stress_all/latest/run.log

  UVM_ERROR @ 168047641027 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @ 168047641027 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 168207313219 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_ERROR @ 168207415259 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark

UVM_ERROR (uart_scoreboard.sv:441) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 3 failures:

Test uart_loopback has 2 failures.

14.uart_loopback.84502531104793006918944683287968048286618800182686203067472472385455889454708
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_loopback/latest/run.log

  UVM_ERROR @ 3692929103 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_INFO @ 3698095771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.uart_loopback.92454056685620886318361592409382533838174069825714834790605140648573351662257
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_loopback/latest/run.log

  UVM_ERROR @ 8240444522 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 8240444522 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 8245621611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_stress_all_with_rand_reset has 1 failures.

44.uart_stress_all_with_rand_reset.65576920888781644454233494396438367122000812171044743040211611249298674532565
Line 324, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3787703774 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 3787703774 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 3858519534 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 56/296
  UVM_INFO @ 3930763854 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 57/296
  UVM_INFO @ 4016201946 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 58/296

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:

Test uart_stress_all_with_rand_reset has 3 failures.

30.uart_stress_all_with_rand_reset.74673709783059009103130766385102346377999801887056604085148892766807228172819
Line 278, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1433633169 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1433633169 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 1433633169 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/8
  UVM_INFO @ 1433633169 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/8

72.uart_stress_all_with_rand_reset.48503501415569825190367852831893997448723335811673211105239005523745533566832
Line 734, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 121161305634 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 121161305634 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 121161489774 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/10
  UVM_INFO @ 121161489774 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/10

... and 1 more failures.

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test uart_intr has 2 failures.
  - 0.uart_intr.42225992749639364002763223818071372567844466605009636830007174633852564204459
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_intr/latest/run.log
```
  Job ID: smart:e2439ee1-c1aa-4652-bc06-717e858347a4
```
  - 36.uart_intr.21710832708177477621674604336429495113620930518586440145451750358248370252405
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_intr/latest/run.log
```
  Job ID: smart:0e5c5de5-715b-4080-ac1d-4045da76371a
```

UVM_ERROR (uart_intr_vseq.sv:267) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

20.uart_stress_all_with_rand_reset.106999106436662586730704970428424398113740506220858717116144643377876565666690
Line 1120, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1012589954040 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1012765354040 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1012940354040 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1013115354040 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 1013290154040 ps: (uart_intr_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])