UART Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	39.900s	10.578ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.300s	1.044ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	55.216us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.530s	507.665us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	52.203us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.290s	119.869us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	55.216us	20	20	100.00
		uart_csr_aliasing	0.820s	52.203us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.185m	162.539ms	50	50	100.00
V2	parity	uart_smoke	39.900s	10.578ms	50	50	100.00
		uart_tx_rx	4.185m	162.539ms	50	50	100.00
V2	parity_error	uart_intr	31.007m	1.091s	50	50	100.00
		uart_rx_parity_err	3.951m	136.619ms	50	50	100.00
V2	watermark	uart_tx_rx	4.185m	162.539ms	50	50	100.00
		uart_intr	31.007m	1.091s	50	50	100.00
V2	fifo_full	uart_fifo_full	9.351m	247.771ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.051m	228.223ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.540m	277.434ms	300	300	100.00
V2	rx_frame_err	uart_intr	31.007m	1.091s	50	50	100.00
V2	rx_break_err	uart_intr	31.007m	1.091s	50	50	100.00
V2	rx_timeout	uart_intr	31.007m	1.091s	50	50	100.00
V2	perf	uart_perf	30.769m	35.678ms	49	50	98.00
V2	sys_loopback	uart_loopback	24.920s	10.767ms	47	50	94.00
V2	line_loopback	uart_loopback	24.920s	10.767ms	47	50	94.00
V2	rx_noise_filter	uart_noise_filter	3.981m	63.238ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.484m	61.571ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	45.970s	7.359ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.078m	5.992ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.270m	234.480ms	50	50	100.00
V2	stress_all	uart_stress_all	38.709m	585.250ms	49	50	98.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	40.138m	835.259ms	43	100	43.00
V2	alert_test	uart_alert_test	0.610s	39.879us	50	50	100.00
V2	intr_test	uart_intr_test	0.690s	27.113us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.470s	472.359us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.470s	472.359us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.300s	1.044ms	5	5	100.00
		uart_csr_rw	0.640s	55.216us	20	20	100.00
		uart_csr_aliasing	0.820s	52.203us	5	5	100.00
		uart_same_csr_outstanding	0.800s	29.976us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.300s	1.044ms	5	5	100.00
		uart_csr_rw	0.640s	55.216us	20	20	100.00
		uart_csr_aliasing	0.820s	52.203us	5	5	100.00
		uart_same_csr_outstanding	0.800s	29.976us	20	20	100.00
V2		TOTAL			1128	1190	94.79
V2S	tl_intg_err	uart_sec_cm	0.830s	73.684us	5	5	100.00
		uart_tl_intg_err	1.400s	97.551us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	97.551us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1258	1320	95.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	15	78.95
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.95	99.38	97.89	100.00	--	98.83	100.00	97.61

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 53 failures:

Test uart_stress_all_with_rand_reset has 53 failures.

2.uart_stress_all_with_rand_reset.59344288274857763248287637660869807736215712678774386766405567242093930695379
Line 502, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 44878046172 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 44878060460 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 44878060460 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 44878109240 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

3.uart_stress_all_with_rand_reset.31052320853771181725223449508833823715207064845151046641337209212975260831488
Line 723, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 130573131758 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 130573156168 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 130573156168 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 130573156168 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/10

... and 51 more failures.

UVM_ERROR (uart_scoreboard.sv:527) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 5 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

4.uart_stress_all_with_rand_reset.88983177146548331289091969171440314101402668512741950688206564132938475326845
Line 497, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32617433212 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (83 [0x53] vs 234 [0xea]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 32617433212 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (234 [0xea] vs 83 [0x53]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 32617933204 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/16
  UVM_INFO @ 32622724794 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 36/987
  UVM_INFO @ 32709765068 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/16

65.uart_stress_all_with_rand_reset.109535142053185656939937431793414315495198560628271890650286145372356996676375
Line 589, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20052485739 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (213 [0xd5] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 20052485739 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 213 [0xd5]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 20052546963 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/10
  UVM_INFO @ 20072812107 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 45/159
  UVM_INFO @ 20171913355 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 46/159

Test uart_stress_all has 1 failures.

8.uart_stress_all.43693122235075899654480951811440310773022241515372146119661180155172276306005
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_stress_all/latest/run.log

  UVM_ERROR @ 3857153070 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (23 [0x17] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 3857153070 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 23 [0x17]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 3858028070 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/15
  UVM_INFO @ 3951403070 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/15
  UVM_INFO @ 4959903070 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/15

Test uart_loopback has 2 failures.

15.uart_loopback.67264340327105625765614322940016064677934051251577759891786433352640774821902
Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_loopback/latest/run.log

  UVM_ERROR @ 3863790093 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (84 [0x54] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 3863790093 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 84 [0x54]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 3864251631 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/14
  UVM_INFO @ 3908943894 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/14
  UVM_INFO @ 3957636153 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/14

44.uart_loopback.764912045190038442425504472410721256983081145293158754448931351057426865544
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_loopback/latest/run.log

  UVM_ERROR @ 1966782503 ps: (uart_scoreboard.sv:527) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (51 [0x33] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 1966782503 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 51 [0x33]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 1966970000 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/9
  UVM_INFO @ 2057093558 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/9
  UVM_INFO @ 2143092182 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/9

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

70.uart_stress_all_with_rand_reset.3558735083366973390655673335513304524024065371608425777872239112529477649312
Line 307, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4044367307 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4044367307 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 4044387715 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/10

93.uart_stress_all_with_rand_reset.17662311509740794310523551251828521705701354084126741105157528994686074567554
Line 2791, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 626825410673 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 626825410673 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 9/10
  UVM_INFO @ 626825410673 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/6
  UVM_INFO @ 626825410673 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/6

UVM_ERROR (uart_scoreboard.sv:441) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:

Test uart_loopback has 1 failures.

7.uart_loopback.88249563535456307928169383254552975393067287724791073513001234382381000297622
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_loopback/latest/run.log

  UVM_ERROR @ 10762155120 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 10762155120 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 10767195936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_scoreboard.sv:497) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_perf has 1 failures.

30.uart_perf.21071531300526706454291387363156204785986903685823233977967646783997448541084
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_perf/latest/run.log

  UVM_ERROR @ 2804973536 ps: (uart_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 2872032896 ps: (uart_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 2939209904 ps: (uart_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 3095917040 ps: (uart_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 3174152960 ps: (uart_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0