UART Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	33.370s	6.214ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	16.257us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	15.578us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.710s	485.793us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	76.001us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.320s	46.284us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	15.578us	20	20	100.00
		uart_csr_aliasing	0.800s	76.001us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.188m	125.782ms	50	50	100.00
V2	parity	uart_smoke	33.370s	6.214ms	50	50	100.00
		uart_tx_rx	4.188m	125.782ms	50	50	100.00
V2	parity_error	uart_intr	9.330m	364.801ms	50	50	100.00
		uart_rx_parity_err	4.643m	206.858ms	50	50	100.00
V2	watermark	uart_tx_rx	4.188m	125.782ms	50	50	100.00
		uart_intr	9.330m	364.801ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.420m	198.590ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.690m	221.890ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.194m	210.237ms	299	300	99.67
V2	rx_frame_err	uart_intr	9.330m	364.801ms	50	50	100.00
V2	rx_break_err	uart_intr	9.330m	364.801ms	50	50	100.00
V2	rx_timeout	uart_intr	9.330m	364.801ms	50	50	100.00
V2	perf	uart_perf	27.651m	31.984ms	50	50	100.00
V2	sys_loopback	uart_loopback	30.970s	12.040ms	50	50	100.00
V2	line_loopback	uart_loopback	30.970s	12.040ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.007m	84.702ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.295m	45.821ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	28.260s	6.686ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.109m	7.877ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.029m	129.694ms	50	50	100.00
V2	stress_all	uart_stress_all	33.492m	191.088ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	31.879m	415.458ms	40	100	40.00
V2	alert_test	uart_alert_test	0.640s	13.816us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	14.414us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.490s	621.455us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.490s	621.455us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	16.257us	5	5	100.00
		uart_csr_rw	0.670s	15.578us	20	20	100.00
		uart_csr_aliasing	0.800s	76.001us	5	5	100.00
		uart_same_csr_outstanding	0.810s	31.521us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	16.257us	5	5	100.00
		uart_csr_rw	0.670s	15.578us	20	20	100.00
		uart_csr_aliasing	0.800s	76.001us	5	5	100.00
		uart_same_csr_outstanding	0.810s	31.521us	20	20	100.00
V2		TOTAL			1129	1190	94.87
V2S	tl_intg_err	uart_sec_cm	0.960s	69.912us	5	5	100.00
		uart_tl_intg_err	1.520s	311.690us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.520s	311.690us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1259	1320	95.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	17	89.47
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.89	99.38	97.89	100.00	--	98.83	100.00	97.27

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 58 failures:

Test uart_stress_all_with_rand_reset has 58 failures.

0.uart_stress_all_with_rand_reset.108265895482387918247376561116365629205188126591107036699383203382039321281114
Line 455, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14895544284 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 14895552172 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 14895552172 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 14895572172 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

3.uart_stress_all_with_rand_reset.101874064420635566199264741762731468023604711775112853389116925632469130891000
Line 491, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15474339362 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10045 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 15474346530 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15474346530 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 15474417958 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

... and 56 more failures.

UVM_ERROR (uart_scoreboard.sv:441) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_fifo_reset has 1 failures.

63.uart_fifo_reset.50121143506507833874567542111222609991174543442402728555385697567624804095671
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/63.uart_fifo_reset/latest/run.log

  UVM_ERROR @ 17552000231 ps: (uart_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 18595085245 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8
  UVM_INFO @ 23593060231 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 5/8
  UVM_INFO @ 32467620231 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 6/8
  UVM_INFO @ 36141160231 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 7/8

UVM_ERROR (uart_intr_vseq.sv:289) [uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

74.uart_stress_all_with_rand_reset.7540560984285463927409843488261909470738668859329455675853762790115366328248
Line 459, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 299159850883 ps: (uart_intr_vseq.sv:289) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (16 [0x10] vs 0 [0x0])
  UVM_ERROR @ 299159850883 ps: (uart_intr_vseq.sv:291) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[NumUartIntr-1:0] & exp_mask == exp_pin (16 [0x10] vs 0 [0x0]) uart_intr val: 0, en_intr: 3d
  UVM_INFO @ 299854050883 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 299944650883 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

85.uart_stress_all_with_rand_reset.35615898799336557857461568675711281761327688611870602800753647004631610652845
Line 397, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 65621411213 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 66184415717 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 67241071229 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 68742612653 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/5
  UVM_INFO @ 69802150542 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running intr test iteration 1/6