UART Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	23.010s	6.268ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	22.977us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.730s	23.184us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.230s	58.859us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.930s	52.157us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.080s	50.157us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.730s	23.184us	20	20	100.00
		uart_csr_aliasing	0.930s	52.157us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.084m	122.721ms	50	50	100.00
V2	parity	uart_smoke	23.010s	6.268ms	50	50	100.00
		uart_tx_rx	3.084m	122.721ms	50	50	100.00
V2	parity_error	uart_intr	8.016m	277.308ms	45	50	90.00
		uart_rx_parity_err	3.628m	122.840ms	50	50	100.00
V2	watermark	uart_tx_rx	3.084m	122.721ms	50	50	100.00
		uart_intr	8.016m	277.308ms	45	50	90.00
V2	fifo_full	uart_fifo_full	10.347m	175.040ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.402m	165.201ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.911m	261.683ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.016m	277.308ms	45	50	90.00
V2	rx_break_err	uart_intr	8.016m	277.308ms	45	50	90.00
V2	rx_timeout	uart_intr	8.016m	277.308ms	45	50	90.00
V2	perf	uart_perf	16.765m	23.360ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.720s	11.220ms	50	50	100.00
V2	line_loopback	uart_loopback	21.720s	11.220ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.857m	339.522ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.403m	51.197ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	35.870s	6.643ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.063m	6.893ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.182m	137.109ms	50	50	100.00
V2	stress_all	uart_stress_all	34.673m	380.608ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	37.307m	136.742ms	33	100	33.00
V2	alert_test	uart_alert_test	0.590s	228.765us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	38.696us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.790s	516.512us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.790s	516.512us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	22.977us	5	5	100.00
		uart_csr_rw	0.730s	23.184us	20	20	100.00
		uart_csr_aliasing	0.930s	52.157us	5	5	100.00
		uart_same_csr_outstanding	0.850s	25.949us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	22.977us	5	5	100.00
		uart_csr_rw	0.730s	23.184us	20	20	100.00
		uart_csr_aliasing	0.930s	52.157us	5	5	100.00
		uart_same_csr_outstanding	0.850s	25.949us	20	20	100.00
V2		TOTAL			1118	1190	93.95
V2S	tl_intg_err	uart_sec_cm	0.830s	63.065us	5	5	100.00
		uart_tl_intg_err	1.440s	164.746us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.440s	164.746us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1248	1320	94.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	17	89.47
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.31	99.38	97.90	100.00	--	99.04	100.00	99.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 64 failures:

Test uart_stress_all_with_rand_reset has 64 failures.

4.uart_stress_all_with_rand_reset.42118435926296390858984323414649633630708688788315194235363513503939703531243
Line 1237, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 284092544348 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 284092547621 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 284092547621 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 284092823485 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

6.uart_stress_all_with_rand_reset.70939107422219474541151177665994755203106407920826769533478384563030983980426
Line 363, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15250084314 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 15250084980 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15250084980 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 15250184980 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

... and 62 more failures.

UVM_ERROR (uart_intr_vseq.sv:276) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 6 failures:

Test uart_intr has 5 failures.

4.uart_intr.86722217990549130773828330259454550048509850471126541389041679185099058517709
Line 277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_intr/latest/run.log

  UVM_ERROR @ 38943568205 ps: (uart_intr_vseq.sv:276) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 39021941864 ps: (uart_intr_vseq.sv:276) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 39022881257 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 39180073019 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

20.uart_intr.25766910714125194295053737106736404746577354286217883264605583390490359777282
Line 269, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_intr/latest/run.log

  UVM_ERROR @ 39386751416 ps: (uart_intr_vseq.sv:276) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 39386751416 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: RxWatermark/1, en_intr: 7b
  UVM_ERROR @ 39474351416 ps: (uart_intr_vseq.sv:276) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 39474351416 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: RxWatermark/1, en_intr: 7b
  UVM_INFO @ 39477051416 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

... and 3 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

80.uart_stress_all_with_rand_reset.42549497961406920047122799802893310434180502424772551771611905847424915410265
Line 699, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 247406949847 ps: (uart_intr_vseq.sv:276) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 247406949847 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: RxWatermark/1, en_intr: 72
  UVM_ERROR @ 247455149847 ps: (uart_intr_vseq.sv:276) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 247455149847 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: RxWatermark/1, en_intr: 72
  UVM_INFO @ 247456549847 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

24.uart_stress_all_with_rand_reset.28408112065067579083459145701039472585628993646302640469209119655118244670090
Line 379, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 35368571720 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 35368571720 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 35368571720 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/6
  UVM_INFO @ 35368571720 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/6

76.uart_stress_all_with_rand_reset.2522761111682726325298943557418959265298710803162951699744853841501102896586
Line 380, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15163348001 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15163348001 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 15163348001 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/9
  UVM_INFO @ 15163348001 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/9