UART Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	35.450s	11.110ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	18.488us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	17.243us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.630s	335.686us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	36.023us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.330s	180.565us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	17.243us	20	20	100.00
		uart_csr_aliasing	0.820s	36.023us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.755m	189.841ms	50	50	100.00
V2	parity	uart_smoke	35.450s	11.110ms	50	50	100.00
		uart_tx_rx	2.755m	189.841ms	50	50	100.00
V2	parity_error	uart_intr	11.435m	521.692ms	50	50	100.00
		uart_rx_parity_err	4.886m	160.589ms	50	50	100.00
V2	watermark	uart_tx_rx	2.755m	189.841ms	50	50	100.00
		uart_intr	11.435m	521.692ms	50	50	100.00
V2	fifo_full	uart_fifo_full	10.385m	230.196ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	5.012m	193.734ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.861m	157.077ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.435m	521.692ms	50	50	100.00
V2	rx_break_err	uart_intr	11.435m	521.692ms	50	50	100.00
V2	rx_timeout	uart_intr	11.435m	521.692ms	50	50	100.00
V2	perf	uart_perf	22.750m	21.834ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.280s	11.433ms	50	50	100.00
V2	line_loopback	uart_loopback	21.280s	11.433ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.119m	294.488ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.052m	79.736ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.860s	6.380ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	54.600s	5.925ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.306m	152.921ms	50	50	100.00
V2	stress_all	uart_stress_all	25.863m	399.088ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	29.200m	721.002ms	29	100	29.00
V2	alert_test	uart_alert_test	0.630s	35.189us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	33.287us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.510s	580.708us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.510s	580.708us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	18.488us	5	5	100.00
		uart_csr_rw	0.670s	17.243us	20	20	100.00
		uart_csr_aliasing	0.820s	36.023us	5	5	100.00
		uart_same_csr_outstanding	0.830s	25.583us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	18.488us	5	5	100.00
		uart_csr_rw	0.670s	17.243us	20	20	100.00
		uart_csr_aliasing	0.820s	36.023us	5	5	100.00
		uart_same_csr_outstanding	0.830s	25.583us	20	20	100.00
V2		TOTAL			1118	1190	93.95
V2S	tl_intg_err	uart_sec_cm	0.890s	65.090us	5	5	100.00
		uart_tl_intg_err	1.450s	92.770us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.450s	92.770us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1248	1320	94.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	17	89.47
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.27	97.90	100.00	--	98.80	100.00	99.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 68 failures:

Test uart_stress_all_with_rand_reset has 68 failures.

0.uart_stress_all_with_rand_reset.59159291736563156295201810425666984674114910497985654416024485250037771832220
Line 392, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19766587775 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10016 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 19766588597 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 19766588597 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 19766734428 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

1.uart_stress_all_with_rand_reset.52718863154390912803889067543932055713977383487049190267991326653901040247053
Line 1012, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 88634628138 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 88634634092 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 88634634092 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 88634634092 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/10

... and 66 more failures.

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

36.uart_stress_all_with_rand_reset.109899185508349093896281091269772944446592048720804306352757877934249794762824
Line 676, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 39151091423 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 39151091423 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 39151091423 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr

54.uart_stress_all_with_rand_reset.43640228633757967846031385924278353436803626353606856375931055748529333184196
Line 616, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28530341785 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28530341785 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 9/10
  UVM_INFO @ 28530341903 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/7
  UVM_INFO @ 28530341903 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/7

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_full has 1 failures.
  - 21.uart_fifo_full.104874319456620759083815847044238538626452840639125905463081697624295005847726
    Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_fifo_full/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

38.uart_stress_all_with_rand_reset.61644958326244845304060860502518023987246067525528072682460427072131061614061
Line 664, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 154235965498 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 154371143050 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 154390966738 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 101/745
  UVM_INFO @ 154908323818 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 102/745
  UVM_INFO @ 155364798058 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 103/745