UART Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	30.010s	5.497ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	190.860us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	58.907us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.700s	259.250us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	54.842us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.280s	91.615us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	58.907us	20	20	100.00
		uart_csr_aliasing	0.810s	54.842us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.313m	90.075ms	50	50	100.00
V2	parity	uart_smoke	30.010s	5.497ms	50	50	100.00
		uart_tx_rx	3.313m	90.075ms	50	50	100.00
V2	parity_error	uart_intr	11.940m	393.055ms	49	50	98.00
		uart_rx_parity_err	6.265m	93.536ms	50	50	100.00
V2	watermark	uart_tx_rx	3.313m	90.075ms	50	50	100.00
		uart_intr	11.940m	393.055ms	49	50	98.00
V2	fifo_full	uart_fifo_full	7.226m	205.015ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.739m	229.431ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.169m	108.265ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.940m	393.055ms	49	50	98.00
V2	rx_break_err	uart_intr	11.940m	393.055ms	49	50	98.00
V2	rx_timeout	uart_intr	11.940m	393.055ms	49	50	98.00
V2	perf	uart_perf	26.747m	27.803ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.680s	10.777ms	50	50	100.00
V2	line_loopback	uart_loopback	21.680s	10.777ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	10.126m	156.921ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.348m	81.184ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	1.018m	7.162ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.084m	7.125ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	32.533m	253.163ms	49	50	98.00
V2	stress_all	uart_stress_all	27.305m	421.660ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	25.411m	111.605ms	32	100	32.00
V2	alert_test	uart_alert_test	0.630s	34.873us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	31.065us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.500s	181.797us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.500s	181.797us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	190.860us	5	5	100.00
		uart_csr_rw	0.650s	58.907us	20	20	100.00
		uart_csr_aliasing	0.810s	54.842us	5	5	100.00
		uart_same_csr_outstanding	0.810s	102.650us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	190.860us	5	5	100.00
		uart_csr_rw	0.650s	58.907us	20	20	100.00
		uart_csr_aliasing	0.810s	54.842us	5	5	100.00
		uart_same_csr_outstanding	0.810s	102.650us	20	20	100.00
V2		TOTAL			1120	1190	94.12
V2S	tl_intg_err	uart_sec_cm	0.830s	71.574us	5	5	100.00
		uart_tl_intg_err	1.450s	93.589us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.450s	93.589us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1250	1320	94.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	16	84.21
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.27	97.90	100.00	--	98.80	100.00	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 66 failures:

Test uart_stress_all_with_rand_reset has 66 failures.

1.uart_stress_all_with_rand_reset.55221229656969309882430045015418754040282882741138425915081026900594537840914
Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4329981143 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4329996437 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4329996437 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 4330306784 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

2.uart_stress_all_with_rand_reset.106737230955753971567282406176250644901966932577603018619198144600384880292822
Line 1368, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 291460852441 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 291460860313 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 291460860313 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 291460860941 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9

... and 64 more failures.

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

0.uart_stress_all_with_rand_reset.93940449516922090965140958833533907235087178193051905616194272019572462454978
Line 835, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 252118337066 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 252118337066 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 252118479923 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 3/10

99.uart_stress_all_with_rand_reset.43951824333061993748330891839633096049186887837855385270786419285751909197619
Line 348, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15188719672 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15188719672 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 15188719672 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/9
  UVM_INFO @ 15188719672 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/9

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_intr has 1 failures.

28.uart_intr.24256417441073597033069274074798061028377048025673355683788484387768196973537
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_intr/latest/run.log

  UVM_ERROR @ 81415737294 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 82562538135 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 94022129811 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

49.uart_long_xfer_wo_dly.5429489460961924640663342180394141535280458939975692662056112701599860651549
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @  38106128 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 218166392 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 274166840 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 330167288 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 386226560 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1