UART Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	23.020s	5.766ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	20.380us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	15.109us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.260s	217.479us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	29.613us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.220s	45.084us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	15.109us	20	20	100.00
		uart_csr_aliasing	0.770s	29.613us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.701m	205.161ms	50	50	100.00
V2	parity	uart_smoke	23.020s	5.766ms	50	50	100.00
		uart_tx_rx	4.701m	205.161ms	50	50	100.00
V2	parity_error	uart_intr	6.224m	240.020ms	50	50	100.00
		uart_rx_parity_err	5.585m	191.762ms	50	50	100.00
V2	watermark	uart_tx_rx	4.701m	205.161ms	50	50	100.00
		uart_intr	6.224m	240.020ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.510m	164.569ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	2.894m	111.900ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.066m	82.461ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.224m	240.020ms	50	50	100.00
V2	rx_break_err	uart_intr	6.224m	240.020ms	50	50	100.00
V2	rx_timeout	uart_intr	6.224m	240.020ms	50	50	100.00
V2	perf	uart_perf	24.674m	31.656ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.090s	12.023ms	50	50	100.00
V2	line_loopback	uart_loopback	25.090s	12.023ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.562m	112.468ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.131m	40.326ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	39.120s	6.558ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.073m	6.463ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.915m	204.721ms	50	50	100.00
V2	stress_all	uart_stress_all	54.863m	667.848ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	38.104m	188.735ms	41	100	41.00
V2	alert_test	uart_alert_test	0.600s	38.335us	50	50	100.00
V2	intr_test	uart_intr_test	0.590s	12.574us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.180s	119.869us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.180s	119.869us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	20.380us	5	5	100.00
		uart_csr_rw	0.650s	15.109us	20	20	100.00
		uart_csr_aliasing	0.770s	29.613us	5	5	100.00
		uart_same_csr_outstanding	0.810s	27.950us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	20.380us	5	5	100.00
		uart_csr_rw	0.650s	15.109us	20	20	100.00
		uart_csr_aliasing	0.770s	29.613us	5	5	100.00
		uart_same_csr_outstanding	0.810s	27.950us	20	20	100.00
V2		TOTAL			1131	1190	95.04
V2S	tl_intg_err	uart_sec_cm	0.930s	188.758us	5	5	100.00
		uart_tl_intg_err	1.420s	164.543us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	164.543us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1261	1320	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	18	94.74
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.27	97.90	100.00	--	98.80	100.00	99.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 56 failures:

Test uart_stress_all_with_rand_reset has 56 failures.

0.uart_stress_all_with_rand_reset.716097089663219426385924687215326726686198582261873966421672613623823500282
Line 652, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43879654879 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 43879668650 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 43879668650 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 43879668650 ps: (uart_intr_vseq.sv:34) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

2.uart_stress_all_with_rand_reset.105798475382889534129825417628789764949795919762533788516786394579822670697918
Line 703, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 27862543589 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 27862551838 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 27862551838 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 27862571838 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

... and 54 more failures.

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 3 failures:

Test uart_stress_all_with_rand_reset has 3 failures.

1.uart_stress_all_with_rand_reset.12150919887825302386143375826004003231322802016968167567136732111060496299396
Line 669, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 99642902000 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 99642902000 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 99643102000 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 8/10

10.uart_stress_all_with_rand_reset.29092173706226851390894975703743625283667878486922570463680910605436437787971
Line 423, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13706085131 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13706085131 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 13706085131 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
  UVM_INFO @ 13706085131 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/5

... and 1 more failures.