UART Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	37.380s	6.283ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	167.495us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	79.797us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.490s	346.980us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	16.250us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.220s	24.477us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	79.797us	20	20	100.00
		uart_csr_aliasing	0.770s	16.250us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.919m	100.790ms	50	50	100.00
V2	parity	uart_smoke	37.380s	6.283ms	50	50	100.00
		uart_tx_rx	3.919m	100.790ms	50	50	100.00
V2	parity_error	uart_intr	10.188m	359.165ms	50	50	100.00
		uart_rx_parity_err	6.840m	139.458ms	50	50	100.00
V2	watermark	uart_tx_rx	3.919m	100.790ms	50	50	100.00
		uart_intr	10.188m	359.165ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.951m	259.964ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	14.916m	220.505ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	20.596m	222.464ms	300	300	100.00
V2	rx_frame_err	uart_intr	10.188m	359.165ms	50	50	100.00
V2	rx_break_err	uart_intr	10.188m	359.165ms	50	50	100.00
V2	rx_timeout	uart_intr	10.188m	359.165ms	50	50	100.00
V2	perf	uart_perf	28.366m	30.195ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.140s	9.242ms	50	50	100.00
V2	line_loopback	uart_loopback	22.140s	9.242ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.605m	101.379ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.461m	56.392ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.570s	6.783ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.127m	6.554ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	30.491m	167.760ms	50	50	100.00
V2	stress_all	uart_stress_all	30.174m	111.009ms	50	50	100.00
V2	alert_test	uart_alert_test	0.640s	13.580us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	42.492us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.600s	126.836us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.600s	126.836us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	167.495us	5	5	100.00
		uart_csr_rw	0.680s	79.797us	20	20	100.00
		uart_csr_aliasing	0.770s	16.250us	5	5	100.00
		uart_same_csr_outstanding	0.990s	310.830us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	167.495us	5	5	100.00
		uart_csr_rw	0.680s	79.797us	20	20	100.00
		uart_csr_aliasing	0.770s	16.250us	5	5	100.00
		uart_same_csr_outstanding	0.990s	310.830us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.900s	62.912us	5	5	100.00
		uart_tl_intg_err	1.400s	314.621us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	314.621us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	36.013m	274.099ms	36	100	36.00
V3		TOTAL			36	100	36.00
		TOTAL			1256	1320	95.15

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.27	97.95	100.00	--	98.80	100.00	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 62 failures:

Test uart_stress_all_with_rand_reset has 62 failures.

0.uart_stress_all_with_rand_reset.94613160073915782484787140124217302356397236513136628091256785905210906688657
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 211320301 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 211323737 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 211323737 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 211323737 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/10

1.uart_stress_all_with_rand_reset.61301375560964168329346696009806127163426201474944037275408200133428588293859
Line 373, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11118238711 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10024 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 11118241221 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11118241221 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 11118315846 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

... and 60 more failures.

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

49.uart_stress_all_with_rand_reset.31632869143521219494426175121232882368975225687062232616046494697774222521778
Line 975, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 64717994074 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 64717994074 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 9/10
  UVM_INFO @ 64718044074 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 9/10

84.uart_stress_all_with_rand_reset.90487846155095065067878791867282753664800602075178503358186630466128501620202
Line 348, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 53078095673 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 53078095673 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 53078095673 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/9
  UVM_INFO @ 53078095673 ps: (uart_tx_rx_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/9