UART Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	42.690s	5.543ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.630s	1.038ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	33.825us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.740s	1.975ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	47.126us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.490s	58.091us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	33.825us	20	20	100.00
		uart_csr_aliasing	0.820s	47.126us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.303m	97.098ms	50	50	100.00
V2	parity	uart_smoke	42.690s	5.543ms	50	50	100.00
		uart_tx_rx	3.303m	97.098ms	50	50	100.00
V2	parity_error	uart_intr	9.071m	376.476ms	50	50	100.00
		uart_rx_parity_err	5.125m	183.523ms	50	50	100.00
V2	watermark	uart_tx_rx	3.303m	97.098ms	50	50	100.00
		uart_intr	9.071m	376.476ms	50	50	100.00
V2	fifo_full	uart_fifo_full	10.394m	279.286ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.576m	236.320ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.796m	87.838ms	300	300	100.00
V2	rx_frame_err	uart_intr	9.071m	376.476ms	50	50	100.00
V2	rx_break_err	uart_intr	9.071m	376.476ms	50	50	100.00
V2	rx_timeout	uart_intr	9.071m	376.476ms	50	50	100.00
V2	perf	uart_perf	25.644m	25.911ms	50	50	100.00
V2	sys_loopback	uart_loopback	34.280s	10.873ms	50	50	100.00
V2	line_loopback	uart_loopback	34.280s	10.873ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.243m	138.950ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.245m	44.893ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	22.710s	7.327ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.051m	6.913ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.579m	185.272ms	50	50	100.00
V2	stress_all	uart_stress_all	26.636m	85.904ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	14.650us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	49.660us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.310s	143.023us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.310s	143.023us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.630s	1.038ms	5	5	100.00
		uart_csr_rw	0.640s	33.825us	20	20	100.00
		uart_csr_aliasing	0.820s	47.126us	5	5	100.00
		uart_same_csr_outstanding	0.840s	30.901us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.630s	1.038ms	5	5	100.00
		uart_csr_rw	0.640s	33.825us	20	20	100.00
		uart_csr_aliasing	0.820s	47.126us	5	5	100.00
		uart_same_csr_outstanding	0.840s	30.901us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.920s	222.258us	5	5	100.00
		uart_tl_intg_err	1.350s	373.883us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	373.883us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	34.112m	219.888ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.59

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 35.uart_noise_filter.2715195224334252899058832254500392169597047027785159233691701790513447198652
      Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_noise_filter/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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