UART Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 52.840s 10.571ms 50 50 100.00
V1 csr_hw_reset uart_csr_hw_reset 0.590s 26.869us 5 5 100.00
V1 csr_rw uart_csr_rw 0.640s 43.156us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 2.450s 227.384us 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 0.780s 94.646us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.130s 67.539us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.640s 43.156us 20 20 100.00
uart_csr_aliasing 0.780s 94.646us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 base_random_seq uart_tx_rx 6.605m 138.376ms 50 50 100.00
V2 parity uart_smoke 52.840s 10.571ms 50 50 100.00
uart_tx_rx 6.605m 138.376ms 50 50 100.00
V2 parity_error uart_intr 6.486m 248.502ms 50 50 100.00
uart_rx_parity_err 6.715m 172.405ms 50 50 100.00
V2 watermark uart_tx_rx 6.605m 138.376ms 50 50 100.00
uart_intr 6.486m 248.502ms 50 50 100.00
V2 fifo_full uart_fifo_full 8.634m 217.768ms 50 50 100.00
V2 fifo_overflow uart_fifo_overflow 14.234m 182.231ms 50 50 100.00
V2 fifo_reset uart_fifo_reset 9.037m 203.793ms 300 300 100.00
V2 rx_frame_err uart_intr 6.486m 248.502ms 50 50 100.00
V2 rx_break_err uart_intr 6.486m 248.502ms 50 50 100.00
V2 rx_timeout uart_intr 6.486m 248.502ms 50 50 100.00
V2 perf uart_perf 18.857m 25.088ms 50 50 100.00
V2 sys_loopback uart_loopback 27.660s 10.783ms 50 50 100.00
V2 line_loopback uart_loopback 27.660s 10.783ms 50 50 100.00
V2 rx_noise_filter uart_noise_filter 4.500m 185.604ms 50 50 100.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 1.913m 83.701ms 50 50 100.00
V2 tx_overide uart_tx_ovrd 29.330s 12.038ms 50 50 100.00
V2 rx_oversample uart_rx_oversample 1.128m 7.017ms 50 50 100.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 24.677m 163.214ms 50 50 100.00
V2 stress_all uart_stress_all 38.834m 352.930ms 50 50 100.00
V2 alert_test uart_alert_test 0.630s 29.892us 50 50 100.00
V2 intr_test uart_intr_test 0.640s 14.598us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 2.560s 45.988us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 2.560s 45.988us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.590s 26.869us 5 5 100.00
uart_csr_rw 0.640s 43.156us 20 20 100.00
uart_csr_aliasing 0.780s 94.646us 5 5 100.00
uart_same_csr_outstanding 0.780s 37.669us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.590s 26.869us 5 5 100.00
uart_csr_rw 0.640s 43.156us 20 20 100.00
uart_csr_aliasing 0.780s 94.646us 5 5 100.00
uart_same_csr_outstanding 0.780s 37.669us 20 20 100.00
V2 TOTAL 1090 1090 100.00
V2S tl_intg_err uart_sec_cm 0.850s 153.665us 5 5 100.00
uart_tl_intg_err 1.440s 97.256us 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 1.440s 97.256us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset uart_stress_all_with_rand_reset 22.909m 238.844ms 100 100 100.00
V3 TOTAL 100 100 100.00
TOTAL 1320 1320 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 18 18 18 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.27 99.27 97.95 100.00 -- 98.80 100.00 99.59

Past Results