UART Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	54.030s	11.111ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	26.051us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	28.711us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.420s	177.550us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	33.631us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.420s	118.892us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	28.711us	20	20	100.00
		uart_csr_aliasing	0.760s	33.631us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.153m	116.021ms	50	50	100.00
V2	parity	uart_smoke	54.030s	11.111ms	50	50	100.00
		uart_tx_rx	5.153m	116.021ms	50	50	100.00
V2	parity_error	uart_intr	7.923m	233.928ms	49	50	98.00
		uart_rx_parity_err	3.824m	126.415ms	50	50	100.00
V2	watermark	uart_tx_rx	5.153m	116.021ms	50	50	100.00
		uart_intr	7.923m	233.928ms	49	50	98.00
V2	fifo_full	uart_fifo_full	12.797m	214.135ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.711m	209.377ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.265m	229.777ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.923m	233.928ms	49	50	98.00
V2	rx_break_err	uart_intr	7.923m	233.928ms	49	50	98.00
V2	rx_timeout	uart_intr	7.923m	233.928ms	49	50	98.00
V2	perf	uart_perf	19.819m	19.763ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.010s	11.362ms	50	50	100.00
V2	line_loopback	uart_loopback	24.010s	11.362ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.822m	180.075ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.297m	46.255ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	42.930s	6.300ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.068m	7.518ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	15.248m	112.506ms	50	50	100.00
V2	stress_all	uart_stress_all	42.665m	354.453ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	41.348us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	36.278us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.040s	214.105us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.040s	214.105us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	26.051us	5	5	100.00
		uart_csr_rw	0.640s	28.711us	20	20	100.00
		uart_csr_aliasing	0.760s	33.631us	5	5	100.00
		uart_same_csr_outstanding	0.800s	33.974us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	26.051us	5	5	100.00
		uart_csr_rw	0.640s	28.711us	20	20	100.00
		uart_csr_aliasing	0.760s	33.631us	5	5	100.00
		uart_same_csr_outstanding	0.800s	33.974us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.860s	130.640us	5	5	100.00
		uart_tl_intg_err	1.340s	95.576us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.340s	95.576us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	32.693m	101.324ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.59

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark

has 1 failures:

Test uart_intr has 1 failures.

4.uart_intr.55381347968579371024764794166398583960689478543973461628057747985282807238338
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_intr/latest/run.log

  UVM_ERROR @ 4589853197 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 5710471124 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 44670336926 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr