UART Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.780s	5.895ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.170s	1.053ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	14.539us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.510s	527.462us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.730s	29.348us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	31.699us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	14.539us	20	20	100.00
		uart_csr_aliasing	0.730s	29.348us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.407m	151.812ms	50	50	100.00
V2	parity	uart_smoke	21.780s	5.895ms	50	50	100.00
		uart_tx_rx	4.407m	151.812ms	50	50	100.00
V2	parity_error	uart_intr	16.294m	303.123ms	50	50	100.00
		uart_rx_parity_err	6.743m	108.014ms	50	50	100.00
V2	watermark	uart_tx_rx	4.407m	151.812ms	50	50	100.00
		uart_intr	16.294m	303.123ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.644m	232.893ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.319m	205.944ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.647m	184.851ms	300	300	100.00
V2	rx_frame_err	uart_intr	16.294m	303.123ms	50	50	100.00
V2	rx_break_err	uart_intr	16.294m	303.123ms	50	50	100.00
V2	rx_timeout	uart_intr	16.294m	303.123ms	50	50	100.00
V2	perf	uart_perf	25.229m	31.398ms	50	50	100.00
V2	sys_loopback	uart_loopback	23.730s	7.262ms	50	50	100.00
V2	line_loopback	uart_loopback	23.730s	7.262ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.020m	281.036ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.246m	51.455ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	25.250s	6.176ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.212m	7.916ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	32.352m	169.124ms	50	50	100.00
V2	stress_all	uart_stress_all	34.800m	470.524ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	80.358us	50	50	100.00
V2	intr_test	uart_intr_test	0.690s	14.682us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.300s	112.120us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.300s	112.120us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.170s	1.053ms	5	5	100.00
		uart_csr_rw	0.630s	14.539us	20	20	100.00
		uart_csr_aliasing	0.730s	29.348us	5	5	100.00
		uart_same_csr_outstanding	0.750s	75.110us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.170s	1.053ms	5	5	100.00
		uart_csr_rw	0.630s	14.539us	20	20	100.00
		uart_csr_aliasing	0.730s	29.348us	5	5	100.00
		uart_same_csr_outstanding	0.750s	75.110us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.860s	234.489us	5	5	100.00
		uart_tl_intg_err	1.420s	252.288us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	252.288us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.773m	112.485ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.64

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:495) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

36.uart_stress_all_with_rand_reset.47803215112557527080276825981702295950846507671414230901366915074351733247762
Line 281, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4781590909 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 4851120877 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/731
  UVM_INFO @ 5205123709 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/6
  UVM_INFO @ 5688833461 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/6
  UVM_INFO @ 5797422565 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/731

UVM_ERROR (cip_base_vseq.sv:829) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

43.uart_stress_all_with_rand_reset.11694719668007438592398768872529680461315834538629180813474777783751407382385
Line 1295, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 133296758878 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 133296777102 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 133296777102 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 9/10
  UVM_INFO @ 133296778878 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2