UART Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	41.550s	11.094ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	16.609us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.690s	44.544us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.360s	566.303us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	350.319us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.240s	27.991us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	44.544us	20	20	100.00
		uart_csr_aliasing	0.790s	350.319us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.840m	106.413ms	50	50	100.00
V2	parity	uart_smoke	41.550s	11.094ms	50	50	100.00
		uart_tx_rx	3.840m	106.413ms	50	50	100.00
V2	parity_error	uart_intr	11.710m	412.891ms	50	50	100.00
		uart_rx_parity_err	4.214m	152.601ms	50	50	100.00
V2	watermark	uart_tx_rx	3.840m	106.413ms	50	50	100.00
		uart_intr	11.710m	412.891ms	50	50	100.00
V2	fifo_full	uart_fifo_full	15.045m	288.547ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.056m	185.793ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.733m	149.439ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.710m	412.891ms	50	50	100.00
V2	rx_break_err	uart_intr	11.710m	412.891ms	50	50	100.00
V2	rx_timeout	uart_intr	11.710m	412.891ms	50	50	100.00
V2	perf	uart_perf	25.406m	25.204ms	50	50	100.00
V2	sys_loopback	uart_loopback	38.730s	13.146ms	50	50	100.00
V2	line_loopback	uart_loopback	38.730s	13.146ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.724m	117.041ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.264m	49.271ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	51.200s	13.089ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.173m	7.537ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	30.285m	183.441ms	49	50	98.00
V2	stress_all	uart_stress_all	25.649m	351.042ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	14.815us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	17.136us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.670s	101.263us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.670s	101.263us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	16.609us	5	5	100.00
		uart_csr_rw	0.690s	44.544us	20	20	100.00
		uart_csr_aliasing	0.790s	350.319us	5	5	100.00
		uart_same_csr_outstanding	0.790s	28.533us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	16.609us	5	5	100.00
		uart_csr_rw	0.690s	44.544us	20	20	100.00
		uart_csr_aliasing	0.790s	350.319us	5	5	100.00
		uart_same_csr_outstanding	0.790s	28.533us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.880s	389.981us	5	5	100.00
		uart_tl_intg_err	1.620s	1.251ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.620s	1.251ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	29.420m	144.805ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.64

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *

has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

18.uart_long_xfer_wo_dly.18490450795023248331167875753528880939695514785529798987272736268646309527304
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 37744769430 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 38948190822 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 38993073534 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 39229075422 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 39824962542 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1