UART Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 21.570s 6.006ms 50 50 100.00
V1 csr_hw_reset uart_csr_hw_reset 0.600s 30.347us 5 5 100.00
V1 csr_rw uart_csr_rw 0.650s 15.745us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 1.660s 240.241us 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 0.770s 18.736us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.100s 47.532us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.650s 15.745us 20 20 100.00
uart_csr_aliasing 0.770s 18.736us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 base_random_seq uart_tx_rx 5.115m 62.995ms 50 50 100.00
V2 parity uart_smoke 21.570s 6.006ms 50 50 100.00
uart_tx_rx 5.115m 62.995ms 50 50 100.00
V2 parity_error uart_intr 8.812m 332.126ms 50 50 100.00
uart_rx_parity_err 7.393m 228.462ms 50 50 100.00
V2 watermark uart_tx_rx 5.115m 62.995ms 50 50 100.00
uart_intr 8.812m 332.126ms 50 50 100.00
V2 fifo_full uart_fifo_full 9.971m 138.735ms 50 50 100.00
V2 fifo_overflow uart_fifo_overflow 5.129m 291.867ms 50 50 100.00
V2 fifo_reset uart_fifo_reset 7.340m 111.096ms 300 300 100.00
V2 rx_frame_err uart_intr 8.812m 332.126ms 50 50 100.00
V2 rx_break_err uart_intr 8.812m 332.126ms 50 50 100.00
V2 rx_timeout uart_intr 8.812m 332.126ms 50 50 100.00
V2 perf uart_perf 23.144m 25.492ms 50 50 100.00
V2 sys_loopback uart_loopback 27.110s 6.294ms 50 50 100.00
V2 line_loopback uart_loopback 27.110s 6.294ms 50 50 100.00
V2 rx_noise_filter uart_noise_filter 7.454m 126.581ms 50 50 100.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 1.205m 43.104ms 50 50 100.00
V2 tx_overide uart_tx_ovrd 22.870s 6.659ms 50 50 100.00
V2 rx_oversample uart_rx_oversample 1.114m 6.678ms 50 50 100.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 23.607m 139.285ms 50 50 100.00
V2 stress_all uart_stress_all 26.242m 872.666ms 50 50 100.00
V2 alert_test uart_alert_test 0.640s 19.339us 50 50 100.00
V2 intr_test uart_intr_test 0.650s 16.144us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 2.380s 132.191us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 2.380s 132.191us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.600s 30.347us 5 5 100.00
uart_csr_rw 0.650s 15.745us 20 20 100.00
uart_csr_aliasing 0.770s 18.736us 5 5 100.00
uart_same_csr_outstanding 0.800s 60.553us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.600s 30.347us 5 5 100.00
uart_csr_rw 0.650s 15.745us 20 20 100.00
uart_csr_aliasing 0.770s 18.736us 5 5 100.00
uart_same_csr_outstanding 0.800s 60.553us 20 20 100.00
V2 TOTAL 1090 1090 100.00
V2S tl_intg_err uart_sec_cm 0.850s 61.292us 5 5 100.00
uart_tl_intg_err 1.440s 4.492ms 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 1.440s 4.492ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset uart_stress_all_with_rand_reset 34.259m 111.091ms 100 100 100.00
V3 TOTAL 100 100 100.00
TOTAL 1320 1320 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 18 18 18 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.27 99.27 97.95 100.00 -- 98.80 100.00 99.59

Past Results