UART Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	42.240s	11.626ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	46.269us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	63.269us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.530s	171.512us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	28.510us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.270s	101.664us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	63.269us	20	20	100.00
		uart_csr_aliasing	0.780s	28.510us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.624m	87.635ms	50	50	100.00
V2	parity	uart_smoke	42.240s	11.626ms	50	50	100.00
		uart_tx_rx	3.624m	87.635ms	50	50	100.00
V2	parity_error	uart_intr	6.049m	262.727ms	50	50	100.00
		uart_rx_parity_err	5.957m	135.204ms	50	50	100.00
V2	watermark	uart_tx_rx	3.624m	87.635ms	50	50	100.00
		uart_intr	6.049m	262.727ms	50	50	100.00
V2	fifo_full	uart_fifo_full	10.430m	171.014ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.215m	211.655ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.910m	112.359ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.049m	262.727ms	50	50	100.00
V2	rx_break_err	uart_intr	6.049m	262.727ms	50	50	100.00
V2	rx_timeout	uart_intr	6.049m	262.727ms	50	50	100.00
V2	perf	uart_perf	18.300m	18.300ms	50	50	100.00
V2	sys_loopback	uart_loopback	41.300s	14.000ms	50	50	100.00
V2	line_loopback	uart_loopback	41.300s	14.000ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.368m	109.798ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.175m	41.105ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	1.120m	12.789ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.125m	7.401ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	13.527m	102.333ms	50	50	100.00
V2	stress_all	uart_stress_all	47.644m	287.967ms	49	50	98.00
V2	alert_test	uart_alert_test	0.600s	76.761us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	35.178us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.550s	456.709us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.550s	456.709us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	46.269us	5	5	100.00
		uart_csr_rw	0.640s	63.269us	20	20	100.00
		uart_csr_aliasing	0.780s	28.510us	5	5	100.00
		uart_same_csr_outstanding	0.800s	32.282us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	46.269us	5	5	100.00
		uart_csr_rw	0.640s	63.269us	20	20	100.00
		uart_csr_aliasing	0.780s	28.510us	5	5	100.00
		uart_same_csr_outstanding	0.800s	32.282us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	1.030s	1.875ms	5	5	100.00
		uart_tl_intg_err	1.610s	512.816us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.610s	512.816us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.159m	660.112ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.61

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_stress_all has 1 failures.

26.uart_stress_all.43787202245636351024616048331626418686042351441631885861004601887216208808022
Line 329, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_stress_all/latest/run.log

  UVM_ERROR @ 497701127333 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 497784627333 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 498487814833 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 3/3
  UVM_INFO @ 498523502333 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_fifo_full_vseq

UVM_ERROR (cip_base_vseq.sv:829) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

39.uart_stress_all_with_rand_reset.64783198503428037070375003318566240080485858238397361407288815434564430855517
Line 1202, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 98188274014 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 98188279828 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 98188279828 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 98188284218 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

98.uart_stress_all_with_rand_reset.14603006944980156225023903050815664323309396814047453327695525510013327242456
Line 910, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 199956615218 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 199956615218 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 199956999838 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 8/10