UART Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 40.280s 5.904ms 50 50 100.00
V1 csr_hw_reset uart_csr_hw_reset 0.610s 15.728us 5 5 100.00
V1 csr_rw uart_csr_rw 0.670s 29.585us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 2.500s 357.904us 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 0.780s 43.305us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.270s 28.545us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.670s 29.585us 20 20 100.00
uart_csr_aliasing 0.780s 43.305us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 base_random_seq uart_tx_rx 3.626m 131.709ms 50 50 100.00
V2 parity uart_smoke 40.280s 5.904ms 50 50 100.00
uart_tx_rx 3.626m 131.709ms 50 50 100.00
V2 parity_error uart_intr 7.769m 282.422ms 50 50 100.00
uart_rx_parity_err 10.242m 307.512ms 50 50 100.00
V2 watermark uart_tx_rx 3.626m 131.709ms 50 50 100.00
uart_intr 7.769m 282.422ms 50 50 100.00
V2 fifo_full uart_fifo_full 12.669m 220.223ms 50 50 100.00
V2 fifo_overflow uart_fifo_overflow 4.813m 121.855ms 50 50 100.00
V2 fifo_reset uart_fifo_reset 11.666m 265.439ms 300 300 100.00
V2 rx_frame_err uart_intr 7.769m 282.422ms 50 50 100.00
V2 rx_break_err uart_intr 7.769m 282.422ms 50 50 100.00
V2 rx_timeout uart_intr 7.769m 282.422ms 50 50 100.00
V2 perf uart_perf 19.364m 21.094ms 50 50 100.00
V2 sys_loopback uart_loopback 35.290s 10.506ms 50 50 100.00
V2 line_loopback uart_loopback 35.290s 10.506ms 50 50 100.00
V2 rx_noise_filter uart_noise_filter 4.622m 140.168ms 50 50 100.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 1.212m 44.662ms 50 50 100.00
V2 tx_overide uart_tx_ovrd 41.950s 12.370ms 50 50 100.00
V2 rx_oversample uart_rx_oversample 1.091m 7.255ms 50 50 100.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 26.463m 125.903ms 50 50 100.00
V2 stress_all uart_stress_all 33.470m 328.247ms 50 50 100.00
V2 alert_test uart_alert_test 0.630s 15.078us 50 50 100.00
V2 intr_test uart_intr_test 0.640s 15.048us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 2.480s 420.238us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 2.480s 420.238us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.610s 15.728us 5 5 100.00
uart_csr_rw 0.670s 29.585us 20 20 100.00
uart_csr_aliasing 0.780s 43.305us 5 5 100.00
uart_same_csr_outstanding 0.870s 124.252us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.610s 15.728us 5 5 100.00
uart_csr_rw 0.670s 29.585us 20 20 100.00
uart_csr_aliasing 0.780s 43.305us 5 5 100.00
uart_same_csr_outstanding 0.870s 124.252us 20 20 100.00
V2 TOTAL 1090 1090 100.00
V2S tl_intg_err uart_sec_cm 0.850s 282.699us 5 5 100.00
uart_tl_intg_err 1.700s 955.791us 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 1.700s 955.791us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset uart_stress_all_with_rand_reset 30.320m 68.154ms 100 100 100.00
V3 TOTAL 100 100 100.00
TOTAL 1320 1320 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 18 18 18 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.27 99.27 97.95 100.00 -- 98.80 100.00 99.61

Past Results