UART Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	23.690s	5.451ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	16.008us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	18.904us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.510s	1.129ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	31.281us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.480s	30.572us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	18.904us	20	20	100.00
		uart_csr_aliasing	0.820s	31.281us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.741m	127.511ms	50	50	100.00
V2	parity	uart_smoke	23.690s	5.451ms	50	50	100.00
		uart_tx_rx	7.741m	127.511ms	50	50	100.00
V2	parity_error	uart_intr	12.304m	465.988ms	50	50	100.00
		uart_rx_parity_err	9.670m	104.469ms	50	50	100.00
V2	watermark	uart_tx_rx	7.741m	127.511ms	50	50	100.00
		uart_intr	12.304m	465.988ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.736m	146.063ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	9.119m	142.560ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.079m	126.503ms	300	300	100.00
V2	rx_frame_err	uart_intr	12.304m	465.988ms	50	50	100.00
V2	rx_break_err	uart_intr	12.304m	465.988ms	50	50	100.00
V2	rx_timeout	uart_intr	12.304m	465.988ms	50	50	100.00
V2	perf	uart_perf	21.768m	26.078ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.830s	7.058ms	50	50	100.00
V2	line_loopback	uart_loopback	25.830s	7.058ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.933m	97.012ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.169m	43.064ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.120s	6.491ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	58.700s	5.921ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	28.485m	152.712ms	50	50	100.00
V2	stress_all	uart_stress_all	41.439m	265.566ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	12.233us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	35.603us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.750s	498.746us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.750s	498.746us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	16.008us	5	5	100.00
		uart_csr_rw	0.650s	18.904us	20	20	100.00
		uart_csr_aliasing	0.820s	31.281us	5	5	100.00
		uart_same_csr_outstanding	0.780s	29.091us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	16.008us	5	5	100.00
		uart_csr_rw	0.650s	18.904us	20	20	100.00
		uart_csr_aliasing	0.820s	31.281us	5	5	100.00
		uart_same_csr_outstanding	0.780s	29.091us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.830s	67.912us	5	5	100.00
		uart_tl_intg_err	1.370s	84.177us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	84.177us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	36.424m	146.894ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.61

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

26.uart_stress_all_with_rand_reset.24158130291572132971597040597428030123993979539863185391089486338955211543549
Line 361, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6381202644 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 6387313749 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/955
  UVM_INFO @ 6495828792 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/955
  UVM_INFO @ 6554313582 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/955
  UVM_INFO @ 6594757986 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/955

UVM_ERROR (cip_base_vseq.sv:829) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

70.uart_stress_all_with_rand_reset.38683244150921800413039727504673274244735746376654783195745452182883864397108
Line 497, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 168242350344 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 168242356970 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 168242356970 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 168242393822 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/2

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

80.uart_stress_all_with_rand_reset.79036962201826347857356097497201202838018743525243767612223601557451766314873
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3027414329 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3027414329 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 3027414329 ps: (uart_loopback_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 1/6
  UVM_INFO @ 3027654329 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]