UART Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.890s	5.374ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	112.980us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	12.257us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.620s	1.039ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	132.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.370s	164.848us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	12.257us	20	20	100.00
		uart_csr_aliasing	0.750s	132.156us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.438m	121.271ms	50	50	100.00
V2	parity	uart_smoke	24.890s	5.374ms	50	50	100.00
		uart_tx_rx	4.438m	121.271ms	50	50	100.00
V2	parity_error	uart_intr	11.377m	390.034ms	50	50	100.00
		uart_rx_parity_err	7.346m	218.554ms	50	50	100.00
V2	watermark	uart_tx_rx	4.438m	121.271ms	50	50	100.00
		uart_intr	11.377m	390.034ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.999m	150.628ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.358m	176.134ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.085m	70.128ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.377m	390.034ms	50	50	100.00
V2	rx_break_err	uart_intr	11.377m	390.034ms	50	50	100.00
V2	rx_timeout	uart_intr	11.377m	390.034ms	50	50	100.00
V2	perf	uart_perf	33.084m	37.056ms	50	50	100.00
V2	sys_loopback	uart_loopback	32.310s	12.024ms	50	50	100.00
V2	line_loopback	uart_loopback	32.310s	12.024ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.157m	111.581ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.085m	73.301ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	47.820s	6.752ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.157m	8.244ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	33.608m	207.932ms	50	50	100.00
V2	stress_all	uart_stress_all	39.490m	329.446ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	14.999us	50	50	100.00
V2	intr_test	uart_intr_test	0.700s	59.136us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.340s	462.699us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.340s	462.699us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	112.980us	5	5	100.00
		uart_csr_rw	0.640s	12.257us	20	20	100.00
		uart_csr_aliasing	0.750s	132.156us	5	5	100.00
		uart_same_csr_outstanding	0.840s	91.020us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	112.980us	5	5	100.00
		uart_csr_rw	0.640s	12.257us	20	20	100.00
		uart_csr_aliasing	0.750s	132.156us	5	5	100.00
		uart_same_csr_outstanding	0.840s	91.020us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.950s	2.121ms	5	5	100.00
		uart_tl_intg_err	1.400s	373.189us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	373.189us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	37.290m	158.137ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1320	1320	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.64

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