UART Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.440s	6.068ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	40.815us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	30.312us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.590s	861.841us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	32.155us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.560s	33.017us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	30.312us	20	20	100.00
		uart_csr_aliasing	0.820s	32.155us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.805m	59.063ms	49	50	98.00
V2	parity	uart_smoke	21.440s	6.068ms	50	50	100.00
		uart_tx_rx	7.805m	59.063ms	49	50	98.00
V2	parity_error	uart_intr	7.113m	228.604ms	50	50	100.00
		uart_rx_parity_err	8.866m	215.805ms	50	50	100.00
V2	watermark	uart_tx_rx	7.805m	59.063ms	49	50	98.00
		uart_intr	7.113m	228.604ms	50	50	100.00
V2	fifo_full	uart_fifo_full	13.792m	235.284ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.756m	302.021ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.674m	236.745ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.113m	228.604ms	50	50	100.00
V2	rx_break_err	uart_intr	7.113m	228.604ms	50	50	100.00
V2	rx_timeout	uart_intr	7.113m	228.604ms	50	50	100.00
V2	perf	uart_perf	18.009m	18.457ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.100s	10.546ms	50	50	100.00
V2	line_loopback	uart_loopback	24.100s	10.546ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.898m	111.465ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.090m	41.133ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	23.030s	6.261ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.236m	7.437ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	27.241m	190.750ms	49	50	98.00
V2	stress_all	uart_stress_all	39.065m	281.095ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	14.204us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	35.978us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.580s	48.756us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.580s	48.756us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	40.815us	5	5	100.00
		uart_csr_rw	0.660s	30.312us	20	20	100.00
		uart_csr_aliasing	0.820s	32.155us	5	5	100.00
		uart_same_csr_outstanding	0.860s	54.153us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	40.815us	5	5	100.00
		uart_csr_rw	0.660s	30.312us	20	20	100.00
		uart_csr_aliasing	0.820s	32.155us	5	5	100.00
		uart_same_csr_outstanding	0.860s	54.153us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.890s	667.193us	5	5	100.00
		uart_tl_intg_err	1.400s	593.111us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	593.111us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.931m	93.298ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	14	77.78
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.61

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test uart_noise_filter has 1 failures.
  - 35.uart_noise_filter.111471762920659673512329885495038438907859971091825435943663147622526126083572
    Line 267, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test uart_tx_rx has 1 failures.
  - 43.uart_tx_rx.30848492912104595342800857100564662657763385829366587049621859342665343983490
    Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/43.uart_tx_rx/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_scoreboard.sv:495) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 2 failures:

Test uart_long_xfer_wo_dly has 1 failures.

41.uart_long_xfer_wo_dly.83544463564029285688206225740196110974903952374730744706935599191581990802875
Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 86766606741 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 87798497349 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/7
  UVM_INFO @ 120260521749 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/7
  UVM_INFO @ 127036105325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_stress_all_with_rand_reset has 1 failures.

80.uart_stress_all_with_rand_reset.91360620701929884055143598913358447417589226616717921389613499476514887832854
Line 290, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12314153569 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 12358859809 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 12493860889 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/10
  UVM_INFO @ 12538567129 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/10
  UVM_INFO @ 12546743665 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 30/433

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_fifo_reset has 1 failures.

17.uart_fifo_reset.91010825813132305308472005606021740894870578904421885685857632939332261322054
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_fifo_reset/latest/run.log

  UVM_ERROR @   4605858 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 92432405858 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
  UVM_INFO @ 92994055858 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
  UVM_INFO @ 94883555858 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7
  UVM_INFO @ 95988655858 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7