UART Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 39.010s 11.098ms 50 50 100.00
V1 csr_hw_reset uart_csr_hw_reset 0.600s 49.758us 5 5 100.00
V1 csr_rw uart_csr_rw 0.620s 17.232us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 2.580s 978.871us 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 0.760s 98.149us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.460s 197.143us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.620s 17.232us 20 20 100.00
uart_csr_aliasing 0.760s 98.149us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 base_random_seq uart_tx_rx 5.429m 134.359ms 50 50 100.00
V2 parity uart_smoke 39.010s 11.098ms 50 50 100.00
uart_tx_rx 5.429m 134.359ms 50 50 100.00
V2 parity_error uart_intr 9.754m 388.156ms 49 50 98.00
uart_rx_parity_err 5.833m 228.501ms 50 50 100.00
V2 watermark uart_tx_rx 5.429m 134.359ms 50 50 100.00
uart_intr 9.754m 388.156ms 49 50 98.00
V2 fifo_full uart_fifo_full 10.030m 85.633ms 50 50 100.00
V2 fifo_overflow uart_fifo_overflow 5.859m 228.337ms 50 50 100.00
V2 fifo_reset uart_fifo_reset 10.607m 118.169ms 300 300 100.00
V2 rx_frame_err uart_intr 9.754m 388.156ms 49 50 98.00
V2 rx_break_err uart_intr 9.754m 388.156ms 49 50 98.00
V2 rx_timeout uart_intr 9.754m 388.156ms 49 50 98.00
V2 perf uart_perf 33.838m 36.405ms 50 50 100.00
V2 sys_loopback uart_loopback 34.610s 11.937ms 50 50 100.00
V2 line_loopback uart_loopback 34.610s 11.937ms 50 50 100.00
V2 rx_noise_filter uart_noise_filter 4.747m 81.144ms 50 50 100.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 2.309m 77.041ms 50 50 100.00
V2 tx_overide uart_tx_ovrd 37.800s 7.074ms 50 50 100.00
V2 rx_oversample uart_rx_oversample 57.100s 7.706ms 50 50 100.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 23.261m 141.119ms 49 50 98.00
V2 stress_all uart_stress_all 23.848m 312.473ms 50 50 100.00
V2 alert_test uart_alert_test 0.600s 30.545us 50 50 100.00
V2 intr_test uart_intr_test 0.650s 22.565us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 2.120s 142.437us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 2.120s 142.437us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.600s 49.758us 5 5 100.00
uart_csr_rw 0.620s 17.232us 20 20 100.00
uart_csr_aliasing 0.760s 98.149us 5 5 100.00
uart_same_csr_outstanding 0.760s 26.931us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.600s 49.758us 5 5 100.00
uart_csr_rw 0.620s 17.232us 20 20 100.00
uart_csr_aliasing 0.760s 98.149us 5 5 100.00
uart_same_csr_outstanding 0.760s 26.931us 20 20 100.00
V2 TOTAL 1088 1090 99.82
V2S tl_intg_err uart_sec_cm 0.840s 378.298us 5 5 100.00
uart_tl_intg_err 1.370s 172.936us 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 1.370s 172.936us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset uart_stress_all_with_rand_reset 33.661m 184.698ms 99 100 99.00
V3 TOTAL 99 100 99.00
TOTAL 1317 1320 99.77

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 18 18 16 88.89
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.27 99.27 97.95 100.00 -- 98.80 100.00 99.59

Failure Buckets

Past Results