UART Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	39.010s	11.098ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	49.758us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.620s	17.232us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.580s	978.871us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	98.149us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	197.143us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.620s	17.232us	20	20	100.00
		uart_csr_aliasing	0.760s	98.149us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.429m	134.359ms	50	50	100.00
V2	parity	uart_smoke	39.010s	11.098ms	50	50	100.00
		uart_tx_rx	5.429m	134.359ms	50	50	100.00
V2	parity_error	uart_intr	9.754m	388.156ms	49	50	98.00
		uart_rx_parity_err	5.833m	228.501ms	50	50	100.00
V2	watermark	uart_tx_rx	5.429m	134.359ms	50	50	100.00
		uart_intr	9.754m	388.156ms	49	50	98.00
V2	fifo_full	uart_fifo_full	10.030m	85.633ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.859m	228.337ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.607m	118.169ms	300	300	100.00
V2	rx_frame_err	uart_intr	9.754m	388.156ms	49	50	98.00
V2	rx_break_err	uart_intr	9.754m	388.156ms	49	50	98.00
V2	rx_timeout	uart_intr	9.754m	388.156ms	49	50	98.00
V2	perf	uart_perf	33.838m	36.405ms	50	50	100.00
V2	sys_loopback	uart_loopback	34.610s	11.937ms	50	50	100.00
V2	line_loopback	uart_loopback	34.610s	11.937ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.747m	81.144ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.309m	77.041ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	37.800s	7.074ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	57.100s	7.706ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.261m	141.119ms	49	50	98.00
V2	stress_all	uart_stress_all	23.848m	312.473ms	50	50	100.00
V2	alert_test	uart_alert_test	0.600s	30.545us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	22.565us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.120s	142.437us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.120s	142.437us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	49.758us	5	5	100.00
		uart_csr_rw	0.620s	17.232us	20	20	100.00
		uart_csr_aliasing	0.760s	98.149us	5	5	100.00
		uart_same_csr_outstanding	0.760s	26.931us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	49.758us	5	5	100.00
		uart_csr_rw	0.620s	17.232us	20	20	100.00
		uart_csr_aliasing	0.760s	98.149us	5	5	100.00
		uart_same_csr_outstanding	0.760s	26.931us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.840s	378.298us	5	5	100.00
		uart_tl_intg_err	1.370s	172.936us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	172.936us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.661m	184.698ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

7.uart_stress_all_with_rand_reset.76063236395635670387585219479458080595819506794048556075537987467042251679137
Line 1788, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 435979881268 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 435979881268 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 435980047936 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/5

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_intr has 1 failures.

9.uart_intr.2692434515545328019685405568167102705117116947540118179893708795764501344392
Line 309, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_intr/latest/run.log

  UVM_ERROR @ 52501534625 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 52586574625 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 53715944625 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout

UVM_ERROR (uart_scoreboard.sv:495) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

30.uart_long_xfer_wo_dly.3290020420015531499671438388109980131940826345536806185665902561268457626288
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 43279629891 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 45353705307 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/6
  UVM_INFO @ 51311400027 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/6
  UVM_INFO @ 61511599275 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/6
  UVM_INFO @ 65605632027 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/6