UART Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	30.770s	6.309ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.660s	33.219us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	38.095us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.580s	1.655ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	54.676us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.430s	30.213us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	38.095us	20	20	100.00
		uart_csr_aliasing	0.800s	54.676us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.285m	148.123ms	50	50	100.00
V2	parity	uart_smoke	30.770s	6.309ms	50	50	100.00
		uart_tx_rx	6.285m	148.123ms	50	50	100.00
V2	parity_error	uart_intr	7.860m	628.791ms	50	50	100.00
		uart_rx_parity_err	3.916m	91.807ms	50	50	100.00
V2	watermark	uart_tx_rx	6.285m	148.123ms	50	50	100.00
		uart_intr	7.860m	628.791ms	50	50	100.00
V2	fifo_full	uart_fifo_full	9.732m	285.111ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	10.198m	197.603ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.828m	108.955ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.860m	628.791ms	50	50	100.00
V2	rx_break_err	uart_intr	7.860m	628.791ms	50	50	100.00
V2	rx_timeout	uart_intr	7.860m	628.791ms	50	50	100.00
V2	perf	uart_perf	19.261m	23.316ms	50	50	100.00
V2	sys_loopback	uart_loopback	31.730s	13.236ms	50	50	100.00
V2	line_loopback	uart_loopback	31.730s	13.236ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.430m	129.518ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	53.780s	36.157ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	31.520s	6.956ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.125m	6.787ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.487m	203.134ms	50	50	100.00
V2	stress_all	uart_stress_all	19.446m	251.786ms	50	50	100.00
V2	alert_test	uart_alert_test	0.640s	21.463us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	13.264us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.120s	42.016us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.120s	42.016us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.660s	33.219us	5	5	100.00
		uart_csr_rw	0.660s	38.095us	20	20	100.00
		uart_csr_aliasing	0.800s	54.676us	5	5	100.00
		uart_same_csr_outstanding	0.850s	127.502us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.660s	33.219us	5	5	100.00
		uart_csr_rw	0.660s	38.095us	20	20	100.00
		uart_csr_aliasing	0.800s	54.676us	5	5	100.00
		uart_same_csr_outstanding	0.850s	127.502us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.890s	112.562us	5	5	100.00
		uart_tl_intg_err	1.640s	655.295us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.640s	655.295us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	30.730m	150.279ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.66

Failure Buckets

UVM_ERROR (uart_intr_vseq.sv:280) [uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (* [*] vs * [*]) uart_intr name/val: RxTimeout/*, en_intr: *

has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

82.uart_stress_all_with_rand_reset.46922012945253219932620866814109922458639657208694347940789848661077969813951
Line 683, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 676752548603 ps: (uart_intr_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 57
  UVM_ERROR @ 678124148603 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 678124148603 ps: (uart_intr_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 57
  UVM_ERROR @ 678550148603 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 678550148603 ps: (uart_intr_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 57