UART Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	34.750s	5.911ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	38.591us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	24.572us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.540s	1.548ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	114.564us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.020s	69.700us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	24.572us	20	20	100.00
		uart_csr_aliasing	0.780s	114.564us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.327m	94.226ms	50	50	100.00
V2	parity	uart_smoke	34.750s	5.911ms	50	50	100.00
		uart_tx_rx	3.327m	94.226ms	50	50	100.00
V2	parity_error	uart_intr	5.563m	206.501ms	50	50	100.00
		uart_rx_parity_err	5.622m	202.502ms	50	50	100.00
V2	watermark	uart_tx_rx	3.327m	94.226ms	50	50	100.00
		uart_intr	5.563m	206.501ms	50	50	100.00
V2	fifo_full	uart_fifo_full	12.642m	142.847ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	9.569m	103.600ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	14.322m	221.717ms	300	300	100.00
V2	rx_frame_err	uart_intr	5.563m	206.501ms	50	50	100.00
V2	rx_break_err	uart_intr	5.563m	206.501ms	50	50	100.00
V2	rx_timeout	uart_intr	5.563m	206.501ms	50	50	100.00
V2	perf	uart_perf	16.831m	18.167ms	50	50	100.00
V2	sys_loopback	uart_loopback	31.660s	8.311ms	50	50	100.00
V2	line_loopback	uart_loopback	31.660s	8.311ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.418m	109.608ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.534m	55.089ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	23.000s	6.484ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.150m	7.451ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.978m	164.878ms	50	50	100.00
V2	stress_all	uart_stress_all	25.094m	82.385ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	11.977us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	36.128us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.290s	137.670us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.290s	137.670us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	38.591us	5	5	100.00
		uart_csr_rw	0.630s	24.572us	20	20	100.00
		uart_csr_aliasing	0.780s	114.564us	5	5	100.00
		uart_same_csr_outstanding	0.770s	106.717us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	38.591us	5	5	100.00
		uart_csr_rw	0.630s	24.572us	20	20	100.00
		uart_csr_aliasing	0.780s	114.564us	5	5	100.00
		uart_same_csr_outstanding	0.770s	106.717us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.830s	57.221us	5	5	100.00
		uart_tl_intg_err	1.400s	442.580us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	442.580us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	35.660m	568.789ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1320	1320	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.59

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